mirror of
https://github.com/spicyjpeg/573in1.git
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65 lines
1.3 KiB
Plaintext
65 lines
1.3 KiB
Plaintext
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# This script is roughly similar to the built-in synth_xilinx command, with the
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# appropriate modifications made in order to output gate netlists rather than
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# precompiled LUTs. Note that more advanced features such as fast carry or
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# distributed LUT RAM are not yet supported.
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## Input and preliminary optimization
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read_verilog src/main.v
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hierarchy -check -top FPGA
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proc
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flatten -noscopeinfo
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tribuf -logic
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deminout
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt
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wreduce
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peepopt
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opt_clean
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## Conversion to gate-level representation
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alumacc
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share
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opt
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memory -nomap
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opt_clean
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opt -full
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simplemap
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techmap -D NOLUT -D LUT_SIZE=4 -map +/techmap.v -map +/xilinx/arith_map.v
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opt -fast
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clean
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## FPGA-specific mapping
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dfflegalize -cell $_DFFE_PP?P_ r -cell $_DLATCH_PP?_ r
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opt_expr -mux_undef -noclkinv
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abc -g gates
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techmap -map src/techmap.v
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clean
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xilinx_dffopt -lut4
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clkbufmap -buf BUFGLS O:I
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iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad OBUFT ~T:I:O -tinoutpad IOBUFT ~T:O:I:IO -ignore IFD D -ignore IFDX D -ignore OFD Q -ignore OFDX Q -ignore OFDTX O
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extractinv -inv INV O:I
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techmap -map src/techmap.v
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clean
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## Output
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autoname
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hierarchy -check
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stat -tech xilinx
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check -noinit
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blackbox =A:whitebox
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write_verilog -noattr build/synth.v
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write_edif -top FPGA -pvector bra -lsbidx build/synth.edf
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