# 573in1 - Copyright (C) 2022-2024 spicyjpeg
#
# 573in1 is free software: you can redistribute it and/or modify it under the
# terms of the GNU General Public License as published by the Free Software
# Foundation, either version 3 of the License, or (at your option) any later
# version.
#
# 573in1 is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along with
# 573in1. If not, see <https://www.gnu.org/licenses/>.

# This script is roughly similar to the built-in synth_xilinx command, with the
# appropriate modifications made in order to output gate netlists rather than
# precompiled LUTs (which are not supported by the ISE mapper for Spartan-XL
# devices).

## Input and preliminary optimization

read_verilog src/primitives/carry.v
read_verilog src/primitives/io.v
read_verilog src/primitives/logic.v
read_verilog src/primitives/memory.v
read_verilog src/spartanxl/alu.v
read_verilog src/spartanxl/compare.v
read_verilog src/spartanxl/counter.v
read_verilog src/spartanxl/mux.v
read_verilog src/spartanxl/register.v
read_verilog src/main/dram.v
read_verilog src/main/main.v
read_verilog src/main/mp3.v
read_verilog src/main/uart.v
read_verilog src/main/util.v
hierarchy -check -top FPGA

proc
flatten -noscopeinfo
tribuf
deminout
opt_expr
opt_clean
#check
opt -nodffe -nosdff
fsm
opt
wreduce
peepopt
opt_clean

## Conversion to gate-level representation

techmap -D LUT_WIDTH=4 -map +/cmp2lut.v -map +/cmp2lcu.v
alumacc
share
opt
memory -nomap
opt_clean

memory_libmap -lib yosys/lutram.txt
opt -fast -full
memory_map

opt -full
techmap -map +/techmap.v
opt -fast
clean

## FPGA-specific mapping

dfflegalize -cell $_DFFE_PP?P_ r -cell $_DLATCH_PP?_ r
opt_expr -mux_undef -noclkinv
abc -liberty yosys/logic.lib

#hilomap -hicell VCC P -locell GND G
#clkbufmap -buf BUFGLS O:I
iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad _OBUFE E:I:O -tinoutpad _IOBUFE E:O:I:IO -ignore BUFGLS I -ignore IFDX D -ignore IFDXI D -ignore OFDX Q -ignore OFDXI Q -ignore OFDTX O -ignore OFDTXI O

techmap -map yosys/cellmap.v
clean

## Output

# HACK: Yosys complains or inserts extraneous cells if these attributes, which
# have already been processed, are not stripped out manually.
setattr -unset init
setattr -unset wand
setattr -unset wor

hierarchy -check
autoname
stat
#check -mapped -noinit
blackbox =A:whitebox

write_verilog -norename build/synth.v

iopadmap -bits -inpad IPAD IPAD -outpad OPAD OPAD -inoutpad IOPAD IOPAD -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD
write_edif -attrprop -top FPGA -pvector bra -lsbidx build/synth.edf