# This script is roughly similar to the built-in synth_xilinx command, with the
# appropriate modifications made in order to output gate netlists rather than
# precompiled LUTs (which are not supported by the ISE mapper for Spartan-XL
# devices). Note that more advanced features such as fast carry or distributed
# LUT RAMs are not yet supported.

## Input and preliminary optimization

read_verilog src/main.v
read_verilog src/spartanxl/primitives.v
hierarchy -check -top FPGA

proc
flatten
tribuf -logic
deminout
opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt
wreduce
peepopt
opt_clean

## Conversion to gate-level representation

techmap -D LUT_WIDTH=4 -map +/cmp2lut.v -map +/cmp2lcu.v
alumacc
share
opt
memory -nomap
opt_clean
memory_map
opt -full

techmap -map +/techmap.v
opt -fast
clean

## FPGA-specific mapping

dfflegalize -cell $_DFFE_PP?P_ r -cell $_DLATCH_PP?_ r
opt_expr -mux_undef -noclkinv
abc -liberty src/spartanxl/primitives.lib
clean

#hilomap -hicell VCC P -locell GND G
iopadmap -bits -inpad IBUF O:I -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD -ignore IFDX D -ignore IFDXI D -ignore BUFGLS I
iopadmap -bits -outpad OBUF I:O -toutpad OBUFE E:I:O -tinoutpad IOBUFE E:O:I:IO -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD -ignore OFDX Q -ignore OFDXI Q -ignore OFDTX O -ignore OFDTXI O
clkbufmap -buf BUFGLS O:I
#extractinv -inv INV O:I

techmap -map src/spartanxl/map.v
clean

## Output

hierarchy -check
autoname
stat -tech xilinx
check -noinit
blackbox =A:whitebox

show -notitle -colors 1 -format dot -viewer none -prefix build/synth
write_verilog -noattr build/synth.v
write_edif -top FPGA -pvector bra -lsbidx build/synth.edf