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69 lines
1.6 KiB
Plaintext
69 lines
1.6 KiB
Plaintext
# This script is roughly similar to the built-in synth_xilinx command, with the
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# appropriate modifications made in order to output gate netlists rather than
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# precompiled LUTs (which are not supported by the ISE mapper for Spartan-XL
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# devices). Note that more advanced features such as fast carry or distributed
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# LUT RAMs are not yet supported.
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## Input and preliminary optimization
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read_verilog src/main.v
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read_verilog src/spartanxl/primitives.v
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hierarchy -check -top FPGA
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proc
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flatten
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tribuf -logic
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deminout
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt
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wreduce
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peepopt
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opt_clean
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## Conversion to gate-level representation
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techmap -D LUT_WIDTH=4 -map +/cmp2lut.v -map +/cmp2lcu.v
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alumacc
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share
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opt
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memory -nomap
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opt_clean
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memory_map
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opt -full
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techmap -map +/techmap.v
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opt -fast
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clean
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## FPGA-specific mapping
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dfflegalize -cell $_DFFE_PP?P_ r -cell $_DLATCH_PP?_ r
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opt_expr -mux_undef -noclkinv
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abc -liberty src/spartanxl/primitives.lib
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clean
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#hilomap -hicell VCC P -locell GND G
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iopadmap -bits -inpad IBUF O:I -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD -ignore IFDX D -ignore IFDXI D -ignore BUFGLS I
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iopadmap -bits -outpad OBUF I:O -toutpad OBUFE E:I:O -tinoutpad IOBUFE E:O:I:IO -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD -ignore OFDX Q -ignore OFDXI Q -ignore OFDTX O -ignore OFDTXI O
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clkbufmap -buf BUFGLS O:I
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#extractinv -inv INV O:I
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techmap -map src/spartanxl/map.v
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clean
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## Output
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hierarchy -check
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autoname
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stat -tech xilinx
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check -noinit
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blackbox =A:whitebox
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show -notitle -colors 1 -format dot -viewer none -prefix build/synth
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write_verilog -noattr build/synth.v
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write_edif -top FPGA -pvector bra -lsbidx build/synth.edf
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