2020-05-05 08:33:16 +02:00
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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2021-08-28 08:20:46 +02:00
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#include "tsec_registers.hpp"
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#include "../kfuse/kfuse_registers.hpp"
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2020-05-05 08:33:16 +02:00
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namespace ams::tsec {
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namespace {
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2021-08-28 08:20:46 +02:00
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constexpr inline const uintptr_t KFUSE = 0x7000FC00;
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constexpr inline const uintptr_t TSEC = 0x54500000;
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enum TsecResult : u32 {
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2021-08-22 00:49:36 +02:00
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TsecResult_Success = 0xB0B0B0B0,
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TsecResult_Failure = 0xD0D0D0D0,
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};
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2020-05-05 08:33:16 +02:00
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2021-08-28 08:20:46 +02:00
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enum TsecMemory {
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TsecMemory_Imem,
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TsecMemory_Dmem,
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};
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bool WaitForKfuseReady() {
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constexpr auto KfuseTimeout = 10 * 1000; /* 10 ms. */
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const u32 end_time = util::GetMicroSeconds() + KfuseTimeout;
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/* Wait for STATE_DONE. */
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while (!reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_DONE, DONE))) {
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if (util::GetMicroSeconds() >= end_time) {
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return false;
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}
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}
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/* Check for STATE_CRCPASS. */
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return reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_CRCPASS, PASS));
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}
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void WaitForDmaIdle() {
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constexpr auto DmaTimeout = 10 * 1000 * 1000; /* 10 Seconds. */
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u32 cur_time = util::GetMicroSeconds();
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const u32 end_time = cur_time + DmaTimeout;
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while (cur_time <= end_time) {
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if (reg::HasValue(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_BUSY, IDLE))) {
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return;
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}
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cur_time = util::GetMicroSeconds();
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}
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AMS_ABORT("tsec dma timeout");
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}
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void WaitForTsecIdle() {
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constexpr auto TsecTimeout = 2 * 1000 * 1000; /* 2 Seconds. */
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u32 cur_time = util::GetMicroSeconds();
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const u32 end_time = cur_time + TsecTimeout;
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while (cur_time <= end_time) {
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if (reg::HasValue(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_HALTED, TRUE))) {
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return;
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}
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cur_time = util::GetMicroSeconds();
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}
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AMS_ABORT("tsec timeout");
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}
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void DoDma256(TsecMemory memory, u32 dst_offset, u32 src_offset) {
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reg::Write(TSEC + TSEC_FALCON_DMATRFMOFFS, TSEC_REG_BITS_VALUE(FALCON_DMATRFMOFFS_OFFSET, dst_offset));
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reg::Write(TSEC + TSEC_FALCON_DMATRFFBOFFS, src_offset);
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if (memory == TsecMemory_Imem) {
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reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, IMEM),
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TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 4B));
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} else {
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reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, DMEM),
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TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 256B));
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}
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WaitForDmaIdle();
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2021-08-22 00:49:36 +02:00
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}
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}
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bool RunTsecFirmware(const void *fw, size_t fw_size) {
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2021-08-28 08:20:46 +02:00
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/* Enable relevant clocks. */
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clkrst::EnableHost1xClock();
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clkrst::EnableTsecClock();
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clkrst::EnableSorSafeClock();
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clkrst::EnableSor0Clock();
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clkrst::EnableSor1Clock();
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clkrst::EnableKfuseClock();
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/* Disable clocks once we're done. */
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ON_SCOPE_EXIT {
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clkrst::DisableHost1xClock();
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clkrst::DisableTsecClock();
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clkrst::DisableSorSafeClock();
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clkrst::DisableSor0Clock();
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clkrst::DisableSor1Clock();
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clkrst::DisableKfuseClock();
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};
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/* Wait for kfuse to be ready. */
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if (!WaitForKfuseReady()) {
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return false;
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}
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/* Configure falcon. */
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reg::Write(TSEC + TSEC_FALCON_DMACTL, 0);
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reg::Write(TSEC + TSEC_FALCON_IRQMSET, 0xFFF2);
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reg::Write(TSEC + TSEC_FALCON_IRQDEST, 0xFFF0);
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reg::Write(TSEC + TSEC_FALCON_ITFEN, 0x3);
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/* Wait for TSEC dma to be idle. */
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WaitForDmaIdle();
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/* Set the base address for transfers. */
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reg::Write(TSEC + TSEC_FALCON_DMATRFBASE, reinterpret_cast<uintptr_t>(fw) >> 8);
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/* Transfer all data to TSEC imem. */
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for (size_t i = 0; i < fw_size; i += 0x100) {
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DoDma256(TsecMemory_Imem, i, i);
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}
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/* Write the magic value to host1x syncpoint 160. */
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reg::Write(0x50003300, 0x34C2E1DA);
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/* Execute the firmware. */
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reg::Write(TSEC + TSEC_FALCON_MAILBOX0, 0);
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reg::Write(TSEC + TSEC_FALCON_MAILBOX1, 0);
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reg::Write(TSEC + TSEC_FALCON_BOOTVEC, 0);
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reg::Write(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_STARTCPU, TRUE));
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/* Wait for TSEC dma to be idle. */
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WaitForDmaIdle();
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/* Wait for TSEC to complete. */
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WaitForTsecIdle();
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/* Clear magic value from host1x syncpoint 160. */
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reg::Write(0x50003300, 0);
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/* Return whether the tsec firmware succeeded. */
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return reg::Read(TSEC + TSEC_FALCON_MAILBOX1) == TsecResult_Success;
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2020-05-05 08:33:16 +02:00
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}
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void Lock() {
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/* Set the tsec host1x syncpoint (160) to be secure. */
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/* TODO: constexpr value. */
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reg::ReadWrite(0x500038F8, REG_BITS_VALUE(0, 1, 0));
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/* Clear the tsec host1x syncpoint. */
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reg::Write(0x50003300, 0);
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}
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}
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