2020-05-05 08:33:16 +02:00
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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2020-05-12 09:32:09 +02:00
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#include "secmon_boot.hpp"
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2020-05-05 08:33:16 +02:00
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#include "secmon_boot_functions.hpp"
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namespace ams::secmon::boot {
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2020-05-12 09:32:09 +02:00
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namespace {
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constexpr inline uintptr_t SYSCTR0 = MemoryRegionVirtualDeviceSysCtr0.GetAddress();
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constinit const u8 BootConfigRsaPublicModulus[se::RsaSize] = {
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0xB5, 0x96, 0x87, 0x31, 0x39, 0xAA, 0xBB, 0x3C, 0x28, 0xF3, 0xF0, 0x65, 0xF1, 0x50, 0x70, 0x64,
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0xE6, 0x6C, 0x97, 0x50, 0xCD, 0xA6, 0xEE, 0xEA, 0xC3, 0x8F, 0xE6, 0xB5, 0x81, 0x54, 0x65, 0x33,
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0x1B, 0x88, 0x4B, 0xCE, 0x9F, 0x53, 0xDF, 0xE4, 0xF6, 0xAD, 0xC3, 0x78, 0xD7, 0x3C, 0xD1, 0xDB,
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0x27, 0x21, 0xA0, 0x24, 0x30, 0x2D, 0x98, 0x41, 0xA8, 0xDF, 0x50, 0x7D, 0xAB, 0xCE, 0x00, 0xD9,
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0xCB, 0xAC, 0x8F, 0x37, 0xF5, 0x53, 0xE4, 0x97, 0x1F, 0x13, 0x3C, 0x19, 0xFF, 0x05, 0xA7, 0x3B,
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0xF6, 0xF4, 0x01, 0xDE, 0xF0, 0xC3, 0x77, 0x7B, 0x83, 0xBA, 0xAF, 0x99, 0x30, 0x94, 0x87, 0x25,
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0x4E, 0x54, 0x42, 0x3F, 0xAC, 0x27, 0xF9, 0xCC, 0x87, 0xDD, 0xAE, 0xF2, 0x54, 0xF3, 0x97, 0x49,
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0xF4, 0xB0, 0xF8, 0x6D, 0xDA, 0x60, 0xE0, 0xFD, 0x57, 0xAE, 0x55, 0xA9, 0x76, 0xEA, 0x80, 0x24,
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0xA0, 0x04, 0x7D, 0xBE, 0xD1, 0x81, 0xD3, 0x0C, 0x95, 0xCF, 0xB7, 0xE0, 0x2D, 0x21, 0x21, 0xFF,
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0x97, 0x1E, 0xB3, 0xD7, 0x9F, 0xBB, 0x33, 0x0C, 0x23, 0xC5, 0x88, 0x4A, 0x33, 0xB9, 0xC9, 0x4E,
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0x1E, 0x65, 0x51, 0x45, 0xDE, 0xF9, 0x64, 0x7C, 0xF0, 0xBF, 0x11, 0xB4, 0x93, 0x8D, 0x5D, 0xC6,
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0xAB, 0x37, 0x9E, 0xE9, 0x39, 0xC1, 0xC8, 0xDB, 0xB9, 0xFE, 0x45, 0xCE, 0x7B, 0xDD, 0x72, 0xD9,
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0x6F, 0x68, 0x13, 0xC0, 0x4B, 0xBA, 0x00, 0xF4, 0x1E, 0x89, 0x71, 0x91, 0x26, 0xA6, 0x46, 0x12,
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0xDF, 0x29, 0x6B, 0xC2, 0x5A, 0x53, 0xAF, 0xB9, 0x5B, 0xFD, 0x13, 0x9F, 0xD1, 0x8A, 0x7C, 0xB5,
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0x04, 0xFD, 0x69, 0xEA, 0x23, 0xB4, 0x6D, 0x16, 0x21, 0x98, 0x54, 0xB4, 0xDF, 0xE6, 0xAB, 0x93,
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0x36, 0xB6, 0xD2, 0x43, 0xCF, 0x2B, 0x98, 0x1D, 0x45, 0xC9, 0xBB, 0x20, 0x42, 0xB1, 0x9D, 0x1D
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};
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}
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2020-05-05 08:33:16 +02:00
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void ClearIram() {
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/* Clear the boot code image from where it was loaded in IRAM. */
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util::ClearMemory(MemoryRegionPhysicalIramBootCodeImage.GetPointer(), MemoryRegionPhysicalIramBootCodeImage.GetSize());
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}
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2020-05-12 09:32:09 +02:00
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void WaitForNxBootloader(const pkg1::SecureMonitorParameters ¶ms, pkg1::BootloaderState state) {
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/* Check NX Bootloader's state once per microsecond until it's advanced enough. */
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while (params.bootloader_state < state) {
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util::WaitMicroSeconds(1);
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}
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}
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void LoadBootConfig(const void *src) {
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pkg1::BootConfig * const dst = secmon::impl::GetBootConfigStorage();
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if (pkg1::IsProduction()) {
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std::memset(dst, 0, sizeof(*dst));
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} else {
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hw::FlushDataCache(src, sizeof(*dst));
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hw::DataSynchronizationBarrierInnerShareable();
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std::memcpy(dst, src, sizeof(*dst));
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}
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}
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void VerifyOrClearBootConfig() {
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/* On production hardware, the boot config is already cleared. */
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if (pkg1::IsProduction()) {
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return;
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}
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pkg1::BootConfig * const bc = secmon::impl::GetBootConfigStorage();
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/* Determine if the bc is valid for the device. */
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bool valid_for_device = false;
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{
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const bool valid_signature = secmon::boot::VerifyBootConfigSignature(*bc, BootConfigRsaPublicModulus, util::size(BootConfigRsaPublicModulus));
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if (valid_signature) {
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valid_for_device = secmon::boot::VerifyBootConfigEcid(*bc);
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}
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}
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/* If the boot config is not valid for the device, clear its signed data. */
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if (!valid_for_device) {
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util::ClearMemory(std::addressof(bc->signed_data), sizeof(bc->signed_data));
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}
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}
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void EnableTsc(u64 initial_tsc_value) {
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/* Write the initial value to the CNTCV registers. */
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const u32 lo = static_cast<u32>(initial_tsc_value >> 0);
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const u32 hi = static_cast<u32>(initial_tsc_value >> 32);
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reg::Write(SYSCTR0 + SYSCTR0_CNTCV0, lo);
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reg::Write(SYSCTR0 + SYSCTR0_CNTCV1, hi);
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/* Configure the system counter control register. */
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reg::Write(SYSCTR0 + SYSCTR0_CNTCR, SYSCTR0_REG_BITS_ENUM(CNTCR_HDBG, ENABLE),
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SYSCTR0_REG_BITS_ENUM(CNTCR_EN, ENABLE));
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}
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2020-05-05 08:33:16 +02:00
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}
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