From 3e8688e19e42f7204cb46a29ae47d1c68e613268 Mon Sep 17 00:00:00 2001 From: hexkyz Date: Mon, 30 Nov 2020 19:05:39 +0000 Subject: [PATCH] fusee: update display code for mariko --- .../fusee-primary/fusee-primary-main/src/di.c | 437 +++++- .../fusee-primary/fusee-primary-main/src/di.h | 55 +- .../fusee-primary-main/src/di.inl | 1199 ++++++++++------- .../fusee-primary-main/src/main.c | 14 +- .../fusee-primary-main/src/panic.c | 12 +- .../fusee-primary-main/src/utils.c | 6 +- fusee/fusee-secondary/src/console.c | 12 +- fusee/fusee-secondary/src/di.c | 437 +++++- fusee/fusee-secondary/src/di.h | 55 +- fusee/fusee-secondary/src/di.inl | 1197 +++++++++------- fusee/fusee-secondary/src/panic.c | 6 +- sept/sept-secondary/src/di.c | 477 +++++-- sept/sept-secondary/src/di.h | 55 +- sept/sept-secondary/src/di.inl | 1199 ++++++++++------- sept/sept-secondary/src/main.c | 4 +- 15 files changed, 3347 insertions(+), 1818 deletions(-) diff --git a/fusee/fusee-primary/fusee-primary-main/src/di.c b/fusee/fusee-primary/fusee-primary-main/src/di.c index ddc8ebf47..2463626b6 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/di.c +++ b/fusee/fusee-primary/fusee-primary-main/src/di.c @@ -15,7 +15,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #include #include "di.h" @@ -26,28 +26,37 @@ #include "gpio.h" #include "pinmux.h" #include "car.h" +#include "apb_misc.h" #include "di.inl" -static uint32_t _display_ver = 0; +static uint32_t g_lcd_vendor = 0; -static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops) -{ - for (uint32_t i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; +static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + if (writes[i].kind == 1) { + udelay(1000 * writes[i].offset); + } else { + *(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value; + } + } } -static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask) -{ +static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + *(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value; + } +} + +static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) { uint32_t end = get_time_us() + timeout; - while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) { + while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) { /* Wait. */ } - udelay(5); + udelay(delay); } -void display_init() -{ +void display_init_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); @@ -55,8 +64,6 @@ void display_init() /* Power on. */ uint8_t val = 0xD0; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); - val = 0x09; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO7, &val, 1); /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ car->rst_dev_h_clr = 0x1010000; @@ -107,11 +114,19 @@ void display_init() gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); /* Configure display interface and display. */ - MAKE_MIPI_CAL_REG(0x60) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; - exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4); - exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94); - exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60); + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); udelay(10000); @@ -123,57 +138,235 @@ void display_init() MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; MAKE_DSI_REG(DSI_WR_DATA) = 0x337; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_WR_DATA) = 0x406; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); - _display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); - udelay(5000); + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } - _display_ver = MAKE_DSI_REG(DSI_RD_DATA); + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x1105; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - - udelay(180000); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x2905; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - udelay(20000); - - exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21); - exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3); + do_register_writes(CAR_BASE, display_config_plld_02_erista, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; - exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10); + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); udelay(10000); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); +} + +void display_init_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Power on. */ + uint8_t val = 0x3A; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1); + val = 0x71; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1); + val = 0xD0; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); + + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ + car->rst_dev_h_clr = 0x1010000; + car->clk_enb_h_set = 0x1010000; + car->rst_dev_l_clr = 0x18000000; + car->clk_enb_l_set = 0x18000000; + car->clk_enb_x_set = 0x20000; + car->clk_source_uart_fst_mipi_cal = 0xA; + car->clk_enb_w_set = 0x80000; + car->clk_source_dsia_lp = 0xA; + + /* DPD idle. */ + pmc->io_dpd_req = 0x40000000; + pmc->io_dpd2_req = 0x40000000; + + /* Configure pins. */ + pinmux->nfc_en &= ~PINMUX_TRISTATE; + pinmux->nfc_int &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; + pinmux->lcd_rst &= ~PINMUX_TRISTATE; + + /* Configure Backlight +-5V GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); udelay(10000); - exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113); + /* Enable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + + udelay(10000); + + /* Configure Backlight PWM, EN and RST GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight EN. */ + gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); + + /* Configure display interface and display. */ + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0; + MAKE_APB_MISC_REG(0xAC0) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); + + udelay(10000); + + /* Enable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); + + udelay(60000); + + MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; + MAKE_DSI_REG(DSI_WR_DATA) = 0x337; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x406; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); + + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } + + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } + + udelay(20000); + + do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); + MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); + + udelay(10000); + + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); } -void display_backlight(bool enable) -{ - /* Enable Backlight PWM. */ - gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); -} - -void display_end() -{ +void display_end_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); @@ -182,17 +375,42 @@ void display_end() MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; - - exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); - exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16); + + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); udelay(10000); - - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; @@ -230,9 +448,95 @@ void display_end() pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); } -void display_color_screen(uint32_t color) -{ - exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8); +void display_end_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Disable Backlight. */ + display_backlight(false); + + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; + MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } + + MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); + + udelay(10000); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(50000); + + /* Disable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable clocks. */ + car->rst_dev_h_set = 0x1010000; + car->clk_enb_h_clr = 0x1010000; + car->rst_dev_l_set = 0x18000000; + car->clk_enb_l_clr = 0x18000000; + + MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)); + MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; + + /* Backlight PWM. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); + + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); + pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); +} + +void display_backlight(bool enable) { + /* Enable Backlight PWM. */ + gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} + +void display_color_screen(uint32_t color) { + do_register_writes(DI_BASE, display_config_solid_color, 8); /* Configure display to show single color. */ MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; @@ -246,20 +550,19 @@ void display_color_screen(uint32_t color) display_backlight(true); } -uint32_t *display_init_framebuffer(void *address) -{ - static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; - if (conf[0].val == 0) { - for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { - conf[i] = cfg_display_framebuffer[i]; +uint32_t *display_init_framebuffer(void *address) { + static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0}; + if (conf[0].value == 0) { + for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) { + conf[i] = display_config_frame_buffer[i]; } } uint32_t *lfb_addr = (uint32_t *)address; - conf[19].val = (uint32_t)address; + conf[19].value = (uint32_t)address; /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */ - exec_cfg((uint32_t *)DI_BASE, conf, 32); + do_register_writes(DI_BASE, conf, 32); udelay(35000); diff --git a/fusee/fusee-primary/fusee-primary-main/src/di.h b/fusee/fusee-primary/fusee-primary-main/src/di.h index c4ebd538e..6f525fbe2 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/di.h +++ b/fusee/fusee-primary/fusee-primary-main/src/di.h @@ -15,7 +15,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef FUSEE_DI_H_ #define FUSEE_DI_H_ @@ -33,6 +33,12 @@ #define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) #define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) +/* Clock and reset registers. */ +#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 +#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 +#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 +#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC + /* Display registers. */ #define DC_CMD_GENERAL_INCR_SYNCPT 0x00 @@ -238,6 +244,7 @@ #define DC_WIN_LINE_STRIDE 0x70A #define DC_WIN_DV_CONTROL 0x70E +#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716 /* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ #define DC_WINBUF_START_ADDR 0x800 @@ -333,7 +340,7 @@ #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) -#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E #define DSI_PAD_CONTROL_1 0x4F @@ -346,22 +353,46 @@ #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) #define DSI_PAD_CONTROL_4 0x52 +#define DSI_PAD_CONTROL_5_MARIKO 0x53 +#define DSI_PAD_CONTROL_6_MARIKO 0x54 +#define DSI_PAD_CONTROL_7_MARIKO 0x55 +#define DSI_INIT_SEQ_DATA_15 0x5F +#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62 -typedef struct _cfg_op_t -{ - uint32_t off; - uint32_t val; -} cfg_op_t; +/* MIPI calibration registers. */ +#define MIPI_CAL_MIPI_CAL_CTRL 0x0 +#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0 0x4 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS 0x8 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS_2 0xC +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG 0x14 +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG 0x18 +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG 0x1C +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG 0x20 +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG 0x24 +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG 0x28 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG 0x38 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG 0x3C +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG 0x40 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG 0x44 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 0x58 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 0x5C +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 0x64 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 0x68 +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 0x70 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 0x74 -void display_init(); -void display_end(); - -/* Show one single color on the display. */ -void display_color_screen(uint32_t color); +void display_init_erista(void); +void display_init_mariko(void); +void display_end_erista(void); +void display_end_mariko(void); /* Switches screen backlight ON/OFF. */ void display_backlight(bool enable); +/* Show one single color on the display. */ +void display_color_screen(uint32_t color); + /* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ uint32_t *display_init_framebuffer(void *address); diff --git a/fusee/fusee-primary/fusee-primary-main/src/di.inl b/fusee/fusee-primary/fusee-primary-main/src/di.inl index e438ca5cb..2544a8f29 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/di.inl +++ b/fusee/fusee-primary/fusee-primary-main/src/di.inl @@ -1,6 +1,7 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (C) 2018 CTCaer + * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,550 +15,714 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC + +typedef struct { + uint32_t offset; + uint32_t value; +} register_write_t; + +typedef struct { + uint16_t kind; + uint16_t offset; + uint32_t value; +} dsi_sleep_or_register_write_t; + +static const uint32_t display_config_frame_buffer_address = 0xC0000000; + +static const register_write_t display_config_plld_01_erista[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, }; -//Display A config. -static const cfg_op_t _display_config_2[94] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_REG_ACT_CONTROL, 0x54}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, - {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, - {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} +static const register_write_t display_config_plld_01_mariko[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, }; -//DSI Init config. -static const cfg_op_t _display_config_3[60] = { - {DSI_WR_DATA, 0}, - {DSI_INT_ENABLE, 0}, - {DSI_INT_STATUS, 0}, - {DSI_INT_MASK, 0}, - {DSI_INIT_SEQ_DATA_0, 0}, - {DSI_INIT_SEQ_DATA_1, 0}, - {DSI_INIT_SEQ_DATA_2, 0}, - {DSI_INIT_SEQ_DATA_3, 0}, - {DSI_DCS_CMDS, 0}, - {DSI_PKT_SEQ_0_LO, 0}, - {DSI_PKT_SEQ_1_LO, 0}, - {DSI_PKT_SEQ_2_LO, 0}, - {DSI_PKT_SEQ_3_LO, 0}, - {DSI_PKT_SEQ_4_LO, 0}, - {DSI_PKT_SEQ_5_LO, 0}, - {DSI_PKT_SEQ_0_HI, 0}, - {DSI_PKT_SEQ_1_HI, 0}, - {DSI_PKT_SEQ_2_HI, 0}, - {DSI_PKT_SEQ_3_HI, 0}, - {DSI_PKT_SEQ_4_HI, 0}, - {DSI_PKT_SEQ_5_HI, 0}, - {DSI_CONTROL, 0}, - {DSI_PAD_CONTROL_CD, 0}, - {DSI_SOL_DELAY, 0x18}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_TRIGGER, 0}, - {DSI_INIT_SEQ_CONTROL, 0}, - {DSI_PKT_LEN_0_1, 0}, - {DSI_PKT_LEN_2_3, 0}, - {DSI_PKT_LEN_4_5, 0}, - {DSI_PKT_LEN_6_7, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, 0}, - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30118}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dc_01[94] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1939}, - {DSI_WR_DATA, 0xAAAAAAD8}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAAAAAAAA}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAA}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2739}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xF39}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x6D915}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_01_init_01[8] = { + {sizeof(uint32_t) * DSI_WR_DATA, 0x0}, + {sizeof(uint32_t) * DSI_INT_ENABLE, 0x0}, + {sizeof(uint32_t) * DSI_INT_STATUS, 0x0}, + {sizeof(uint32_t) * DSI_INT_MASK, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_5[21] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30172}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PKT_SEQ_0_LO, 0x40000208}, - {DSI_PKT_SEQ_2_LO, 0x40000308}, - {DSI_PKT_SEQ_4_LO, 0x40000308}, - {DSI_PKT_SEQ_1_LO, 0x40000308}, - {DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_3_HI, 0x2CC}, - {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_5_HI, 0x2CC}, - {DSI_PKT_LEN_0_1, 0xCE0000}, - {DSI_PKT_LEN_2_3, 0x87001A2}, - {DSI_PKT_LEN_4_5, 0x190}, - {DSI_PKT_LEN_6_7, 0x190}, - {DSI_HOST_CONTROL, 0}, +static const register_write_t display_config_dsi_01_init_02_erista[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0}, }; -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC +static const register_write_t display_config_dsi_01_init_02_mariko[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_7[10] = { - {DSI_TRIGGER, 0}, - {DSI_CONTROL, 0}, - {DSI_SOL_DELAY, 6}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +static const register_write_t display_config_dsi_01_init_03[13] = { + {sizeof(uint32_t) * DSI_DCS_CMDS, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 1}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} +static const register_write_t display_config_dsi_01_init_04_erista[0] = { + /* No register writes. */ }; -//DSI config. -static const cfg_op_t _display_config_9[4] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PAD_CONTROL_2, 0}, - {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, - {DSI_PAD_CONTROL_4, 0} +static const register_write_t display_config_dsi_01_init_04_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} +static const register_write_t display_config_dsi_01_init_05[11] = { + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -//Display A config. -static const cfg_op_t _display_config_11[113] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - /* Set Display timings */ - {DC_DISP_DISP_TIMING_OPTIONS, 0}, - {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. - {DC_DISP_SYNC_WIDTH, 0x10048}, - {DC_DISP_BACK_PORCH, 0x90048}, - {DC_DISP_ACTIVE, 0x50002D0}, - {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. - /* End of Display timings */ - {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, - {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, - {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_DISP_DISP_CLOCK_CONTROL, 0}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} +static const register_write_t display_config_dsi_01_init_06[12] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -////Display A config. -static const cfg_op_t _display_config_12[17] = { - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_INT_MASK, 0}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_INT_ENABLE, 0}, - {DC_CMD_CONT_SYNCPT_VSYNC, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_POWER_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +static const register_write_t display_config_dsi_01_init_07[14] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30118}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, }; -//DSI config. -static const cfg_op_t _display_config_13[16] = { - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dsi_phy_timing_erista[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2139}, - {DSI_WR_DATA, 0x191919D5}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xB39}, - {DSI_WR_DATA, 0x4F0F41B1}, - {DSI_WR_DATA, 0xF179A433}, - {DSI_WR_DATA, 0x2D81}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_phy_timing_mariko[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603}, }; -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. +static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1939}, + {0, DSI_WR_DATA, 0xAAAAAAD8}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAA}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2739}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xF39}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x6D915}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_POSITION, 0}, //(0,0) - {DC_WIN_H_INITIAL_DDA, 0}, - {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. - {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0}, - {DC_WINBUF_ADDR_V_OFFSET, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x78, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const register_write_t display_config_plld_02_erista[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, +}; + +static const register_write_t display_config_plld_02_mariko[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, +}; + +static const register_write_t display_config_dsi_01_init_08[1] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_init_09[19] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30172}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0x40000208}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0xCE0000}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0x87001A2}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0x190}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0x190}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, 0}, +}; + +static const register_write_t display_config_dsi_01_init_10[10] = { + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 6}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +}; + +static const register_write_t display_config_dsi_01_init_11_erista[4] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0} +}; + +static const register_write_t display_config_dsi_01_init_11_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, +}; + +static const register_write_t display_config_mipi_cal_01[4] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, +}; + +static const register_write_t display_config_mipi_cal_02_erista[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300}, +}; + +static const register_write_t display_config_mipi_cal_02_mariko[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_erista[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_mariko[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_04[10] = { + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}, +}; + +static const register_write_t display_config_dc_02[113] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)}, + {sizeof(uint32_t) * DC_DISP_SYNC_WIDTH, 0x10048}, + {sizeof(uint32_t) * DC_DISP_BACK_PORCH, 0x90048}, + {sizeof(uint32_t) * DC_DISP_ACTIVE, 0x50002D0}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, +}; + +static const register_write_t display_config_frame_buffer[32] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_POSITION, 0}, + {sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00}, + {sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0}, + {sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0}, + {sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}, +}; + +static const register_write_t display_config_solid_color[8] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, +}; + +static const register_write_t display_config_dsi_01_fini_01[2] = { + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_fini_02[13] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0} +}; + +static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2139}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x4F0F41B1}, + {0, DSI_WR_DATA, 0xF179A433}, + {0, DSI_WR_DATA, 0x2D81}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D6}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x115631}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; \ No newline at end of file diff --git a/fusee/fusee-primary/fusee-primary-main/src/main.c b/fusee/fusee-primary/fusee-primary-main/src/main.c index f908a8578..388943b92 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/main.c +++ b/fusee/fusee-primary/fusee-primary-main/src/main.c @@ -99,8 +99,12 @@ static void setup_display(void) { video_init(g_framebuffer); /* Initialize the display. */ - display_init(); - + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } + /* Set the framebuffer. */ display_init_framebuffer(g_framebuffer); @@ -114,7 +118,11 @@ static void cleanup_display(void) { display_backlight(false); /* Terminate the display. */ - display_end(); + if (fuse_get_soc_type() == 1) { + display_end_mariko(); + } else { + display_end_erista(); + } } static void setup_env(void) { diff --git a/fusee/fusee-primary/fusee-primary-main/src/panic.c b/fusee/fusee-primary/fusee-primary-main/src/panic.c index a25ee8521..b51415499 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/panic.c +++ b/fusee/fusee-primary/fusee-primary-main/src/panic.c @@ -125,7 +125,11 @@ static void _check_and_display_atmosphere_fatal_error(void) { video_init((void *)0xC0000000); /* Initialize the display. */ - display_init(); + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } /* Set the framebuffer. */ display_init_framebuffer((void *)0xC0000000); @@ -221,7 +225,11 @@ void check_and_display_panic(void) { } /* Initialize the display. */ - display_init(); + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } /* Fill the screen. */ display_color_screen(color); diff --git a/fusee/fusee-primary/fusee-primary-main/src/utils.c b/fusee/fusee-primary/fusee-primary-main/src/utils.c index 96eb0591b..77f8da91d 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/utils.c +++ b/fusee/fusee-primary/fusee-primary-main/src/utils.c @@ -130,7 +130,11 @@ __attribute__((noreturn)) void fatal_error(const char *fmt, ...) { video_init((void *)0xC0000000); /* Initialize the display. */ - display_init(); + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } /* Set the framebuffer. */ display_init_framebuffer((void *)0xC0000000); diff --git a/fusee/fusee-secondary/src/console.c b/fusee/fusee-secondary/src/console.c index b3d8f0d18..c389cdf22 100644 --- a/fusee/fusee-secondary/src/console.c +++ b/fusee/fusee-secondary/src/console.c @@ -98,7 +98,11 @@ static ssize_t decode_utf8(uint32_t *out, const uint8_t *in) { static void console_init_display(void) { /* Initialize the display. */ - display_init(); + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } /* Set the framebuffer. */ display_init_framebuffer(g_framebuffer); @@ -198,7 +202,11 @@ int console_end(void) { display_backlight(false); /* Terminate the display. */ - display_end(); + if (fuse_get_soc_type() == 1) { + display_end_mariko(); + } else { + display_end_erista(); + } /* Display is terminated. */ g_display_initialized = false; diff --git a/fusee/fusee-secondary/src/di.c b/fusee/fusee-secondary/src/di.c index ddc8ebf47..2463626b6 100644 --- a/fusee/fusee-secondary/src/di.c +++ b/fusee/fusee-secondary/src/di.c @@ -15,7 +15,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #include #include "di.h" @@ -26,28 +26,37 @@ #include "gpio.h" #include "pinmux.h" #include "car.h" +#include "apb_misc.h" #include "di.inl" -static uint32_t _display_ver = 0; +static uint32_t g_lcd_vendor = 0; -static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops) -{ - for (uint32_t i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; +static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + if (writes[i].kind == 1) { + udelay(1000 * writes[i].offset); + } else { + *(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value; + } + } } -static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask) -{ +static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + *(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value; + } +} + +static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) { uint32_t end = get_time_us() + timeout; - while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) { + while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) { /* Wait. */ } - udelay(5); + udelay(delay); } -void display_init() -{ +void display_init_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); @@ -55,8 +64,6 @@ void display_init() /* Power on. */ uint8_t val = 0xD0; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); - val = 0x09; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO7, &val, 1); /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ car->rst_dev_h_clr = 0x1010000; @@ -107,11 +114,19 @@ void display_init() gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); /* Configure display interface and display. */ - MAKE_MIPI_CAL_REG(0x60) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; - exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4); - exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94); - exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60); + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); udelay(10000); @@ -123,57 +138,235 @@ void display_init() MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; MAKE_DSI_REG(DSI_WR_DATA) = 0x337; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_WR_DATA) = 0x406; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); - _display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); - udelay(5000); + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } - _display_ver = MAKE_DSI_REG(DSI_RD_DATA); + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x1105; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - - udelay(180000); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x2905; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - udelay(20000); - - exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21); - exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3); + do_register_writes(CAR_BASE, display_config_plld_02_erista, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; - exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10); + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); udelay(10000); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); +} + +void display_init_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Power on. */ + uint8_t val = 0x3A; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1); + val = 0x71; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1); + val = 0xD0; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); + + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ + car->rst_dev_h_clr = 0x1010000; + car->clk_enb_h_set = 0x1010000; + car->rst_dev_l_clr = 0x18000000; + car->clk_enb_l_set = 0x18000000; + car->clk_enb_x_set = 0x20000; + car->clk_source_uart_fst_mipi_cal = 0xA; + car->clk_enb_w_set = 0x80000; + car->clk_source_dsia_lp = 0xA; + + /* DPD idle. */ + pmc->io_dpd_req = 0x40000000; + pmc->io_dpd2_req = 0x40000000; + + /* Configure pins. */ + pinmux->nfc_en &= ~PINMUX_TRISTATE; + pinmux->nfc_int &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; + pinmux->lcd_rst &= ~PINMUX_TRISTATE; + + /* Configure Backlight +-5V GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); udelay(10000); - exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113); + /* Enable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + + udelay(10000); + + /* Configure Backlight PWM, EN and RST GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight EN. */ + gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); + + /* Configure display interface and display. */ + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0; + MAKE_APB_MISC_REG(0xAC0) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); + + udelay(10000); + + /* Enable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); + + udelay(60000); + + MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; + MAKE_DSI_REG(DSI_WR_DATA) = 0x337; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x406; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); + + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } + + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } + + udelay(20000); + + do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); + MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); + + udelay(10000); + + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); } -void display_backlight(bool enable) -{ - /* Enable Backlight PWM. */ - gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); -} - -void display_end() -{ +void display_end_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); @@ -182,17 +375,42 @@ void display_end() MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; - - exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); - exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16); + + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); udelay(10000); - - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; @@ -230,9 +448,95 @@ void display_end() pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); } -void display_color_screen(uint32_t color) -{ - exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8); +void display_end_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Disable Backlight. */ + display_backlight(false); + + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; + MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } + + MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); + + udelay(10000); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(50000); + + /* Disable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable clocks. */ + car->rst_dev_h_set = 0x1010000; + car->clk_enb_h_clr = 0x1010000; + car->rst_dev_l_set = 0x18000000; + car->clk_enb_l_clr = 0x18000000; + + MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)); + MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; + + /* Backlight PWM. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); + + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); + pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); +} + +void display_backlight(bool enable) { + /* Enable Backlight PWM. */ + gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} + +void display_color_screen(uint32_t color) { + do_register_writes(DI_BASE, display_config_solid_color, 8); /* Configure display to show single color. */ MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; @@ -246,20 +550,19 @@ void display_color_screen(uint32_t color) display_backlight(true); } -uint32_t *display_init_framebuffer(void *address) -{ - static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; - if (conf[0].val == 0) { - for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { - conf[i] = cfg_display_framebuffer[i]; +uint32_t *display_init_framebuffer(void *address) { + static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0}; + if (conf[0].value == 0) { + for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) { + conf[i] = display_config_frame_buffer[i]; } } uint32_t *lfb_addr = (uint32_t *)address; - conf[19].val = (uint32_t)address; + conf[19].value = (uint32_t)address; /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */ - exec_cfg((uint32_t *)DI_BASE, conf, 32); + do_register_writes(DI_BASE, conf, 32); udelay(35000); diff --git a/fusee/fusee-secondary/src/di.h b/fusee/fusee-secondary/src/di.h index c4ebd538e..6f525fbe2 100644 --- a/fusee/fusee-secondary/src/di.h +++ b/fusee/fusee-secondary/src/di.h @@ -15,7 +15,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef FUSEE_DI_H_ #define FUSEE_DI_H_ @@ -33,6 +33,12 @@ #define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) #define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) +/* Clock and reset registers. */ +#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 +#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 +#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 +#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC + /* Display registers. */ #define DC_CMD_GENERAL_INCR_SYNCPT 0x00 @@ -238,6 +244,7 @@ #define DC_WIN_LINE_STRIDE 0x70A #define DC_WIN_DV_CONTROL 0x70E +#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716 /* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ #define DC_WINBUF_START_ADDR 0x800 @@ -333,7 +340,7 @@ #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) -#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E #define DSI_PAD_CONTROL_1 0x4F @@ -346,22 +353,46 @@ #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) #define DSI_PAD_CONTROL_4 0x52 +#define DSI_PAD_CONTROL_5_MARIKO 0x53 +#define DSI_PAD_CONTROL_6_MARIKO 0x54 +#define DSI_PAD_CONTROL_7_MARIKO 0x55 +#define DSI_INIT_SEQ_DATA_15 0x5F +#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62 -typedef struct _cfg_op_t -{ - uint32_t off; - uint32_t val; -} cfg_op_t; +/* MIPI calibration registers. */ +#define MIPI_CAL_MIPI_CAL_CTRL 0x0 +#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0 0x4 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS 0x8 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS_2 0xC +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG 0x14 +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG 0x18 +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG 0x1C +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG 0x20 +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG 0x24 +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG 0x28 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG 0x38 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG 0x3C +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG 0x40 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG 0x44 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 0x58 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 0x5C +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 0x64 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 0x68 +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 0x70 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 0x74 -void display_init(); -void display_end(); - -/* Show one single color on the display. */ -void display_color_screen(uint32_t color); +void display_init_erista(void); +void display_init_mariko(void); +void display_end_erista(void); +void display_end_mariko(void); /* Switches screen backlight ON/OFF. */ void display_backlight(bool enable); +/* Show one single color on the display. */ +void display_color_screen(uint32_t color); + /* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ uint32_t *display_init_framebuffer(void *address); diff --git a/fusee/fusee-secondary/src/di.inl b/fusee/fusee-secondary/src/di.inl index d0e9894ff..2544a8f29 100644 --- a/fusee/fusee-secondary/src/di.inl +++ b/fusee/fusee-secondary/src/di.inl @@ -1,6 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,550 +15,714 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC + +typedef struct { + uint32_t offset; + uint32_t value; +} register_write_t; + +typedef struct { + uint16_t kind; + uint16_t offset; + uint32_t value; +} dsi_sleep_or_register_write_t; + +static const uint32_t display_config_frame_buffer_address = 0xC0000000; + +static const register_write_t display_config_plld_01_erista[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, }; -//Display A config. -static const cfg_op_t _display_config_2[94] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_REG_ACT_CONTROL, 0x54}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, - {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, - {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} +static const register_write_t display_config_plld_01_mariko[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, }; -//DSI Init config. -static const cfg_op_t _display_config_3[60] = { - {DSI_WR_DATA, 0}, - {DSI_INT_ENABLE, 0}, - {DSI_INT_STATUS, 0}, - {DSI_INT_MASK, 0}, - {DSI_INIT_SEQ_DATA_0, 0}, - {DSI_INIT_SEQ_DATA_1, 0}, - {DSI_INIT_SEQ_DATA_2, 0}, - {DSI_INIT_SEQ_DATA_3, 0}, - {DSI_DCS_CMDS, 0}, - {DSI_PKT_SEQ_0_LO, 0}, - {DSI_PKT_SEQ_1_LO, 0}, - {DSI_PKT_SEQ_2_LO, 0}, - {DSI_PKT_SEQ_3_LO, 0}, - {DSI_PKT_SEQ_4_LO, 0}, - {DSI_PKT_SEQ_5_LO, 0}, - {DSI_PKT_SEQ_0_HI, 0}, - {DSI_PKT_SEQ_1_HI, 0}, - {DSI_PKT_SEQ_2_HI, 0}, - {DSI_PKT_SEQ_3_HI, 0}, - {DSI_PKT_SEQ_4_HI, 0}, - {DSI_PKT_SEQ_5_HI, 0}, - {DSI_CONTROL, 0}, - {DSI_PAD_CONTROL_CD, 0}, - {DSI_SOL_DELAY, 0x18}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_TRIGGER, 0}, - {DSI_INIT_SEQ_CONTROL, 0}, - {DSI_PKT_LEN_0_1, 0}, - {DSI_PKT_LEN_2_3, 0}, - {DSI_PKT_LEN_4_5, 0}, - {DSI_PKT_LEN_6_7, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, 0}, - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30118}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dc_01[94] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1939}, - {DSI_WR_DATA, 0xAAAAAAD8}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAAAAAAAA}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAA}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2739}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xF39}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x6D915}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_01_init_01[8] = { + {sizeof(uint32_t) * DSI_WR_DATA, 0x0}, + {sizeof(uint32_t) * DSI_INT_ENABLE, 0x0}, + {sizeof(uint32_t) * DSI_INT_STATUS, 0x0}, + {sizeof(uint32_t) * DSI_INT_MASK, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_5[21] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30172}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PKT_SEQ_0_LO, 0x40000208}, - {DSI_PKT_SEQ_2_LO, 0x40000308}, - {DSI_PKT_SEQ_4_LO, 0x40000308}, - {DSI_PKT_SEQ_1_LO, 0x40000308}, - {DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_3_HI, 0x2CC}, - {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_5_HI, 0x2CC}, - {DSI_PKT_LEN_0_1, 0xCE0000}, - {DSI_PKT_LEN_2_3, 0x87001A2}, - {DSI_PKT_LEN_4_5, 0x190}, - {DSI_PKT_LEN_6_7, 0x190}, - {DSI_HOST_CONTROL, 0}, +static const register_write_t display_config_dsi_01_init_02_erista[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0}, }; -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC +static const register_write_t display_config_dsi_01_init_02_mariko[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_7[10] = { - {DSI_TRIGGER, 0}, - {DSI_CONTROL, 0}, - {DSI_SOL_DELAY, 6}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +static const register_write_t display_config_dsi_01_init_03[13] = { + {sizeof(uint32_t) * DSI_DCS_CMDS, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 1}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} +static const register_write_t display_config_dsi_01_init_04_erista[0] = { + /* No register writes. */ }; -//DSI config. -static const cfg_op_t _display_config_9[4] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PAD_CONTROL_2, 0}, - {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, - {DSI_PAD_CONTROL_4, 0} +static const register_write_t display_config_dsi_01_init_04_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} +static const register_write_t display_config_dsi_01_init_05[11] = { + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -//Display A config. -static const cfg_op_t _display_config_11[113] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - /* Set Display timings */ - {DC_DISP_DISP_TIMING_OPTIONS, 0}, - {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. - {DC_DISP_SYNC_WIDTH, 0x10048}, - {DC_DISP_BACK_PORCH, 0x90048}, - {DC_DISP_ACTIVE, 0x50002D0}, - {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. - /* End of Display timings */ - {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, - {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, - {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_DISP_DISP_CLOCK_CONTROL, 0}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} +static const register_write_t display_config_dsi_01_init_06[12] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -////Display A config. -static const cfg_op_t _display_config_12[17] = { - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_INT_MASK, 0}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_INT_ENABLE, 0}, - {DC_CMD_CONT_SYNCPT_VSYNC, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_POWER_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +static const register_write_t display_config_dsi_01_init_07[14] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30118}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, }; -//DSI config. -static const cfg_op_t _display_config_13[16] = { - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dsi_phy_timing_erista[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2139}, - {DSI_WR_DATA, 0x191919D5}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xB39}, - {DSI_WR_DATA, 0x4F0F41B1}, - {DSI_WR_DATA, 0xF179A433}, - {DSI_WR_DATA, 0x2D81}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_phy_timing_mariko[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603}, }; -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. +static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1939}, + {0, DSI_WR_DATA, 0xAAAAAAD8}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAA}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2739}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xF39}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x6D915}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_POSITION, 0}, //(0,0) - {DC_WIN_H_INITIAL_DDA, 0}, - {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. - {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0}, - {DC_WINBUF_ADDR_V_OFFSET, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x78, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const register_write_t display_config_plld_02_erista[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, +}; + +static const register_write_t display_config_plld_02_mariko[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, +}; + +static const register_write_t display_config_dsi_01_init_08[1] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_init_09[19] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30172}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0x40000208}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0xCE0000}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0x87001A2}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0x190}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0x190}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, 0}, +}; + +static const register_write_t display_config_dsi_01_init_10[10] = { + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 6}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +}; + +static const register_write_t display_config_dsi_01_init_11_erista[4] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0} +}; + +static const register_write_t display_config_dsi_01_init_11_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, +}; + +static const register_write_t display_config_mipi_cal_01[4] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, +}; + +static const register_write_t display_config_mipi_cal_02_erista[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300}, +}; + +static const register_write_t display_config_mipi_cal_02_mariko[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_erista[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_mariko[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_04[10] = { + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}, +}; + +static const register_write_t display_config_dc_02[113] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)}, + {sizeof(uint32_t) * DC_DISP_SYNC_WIDTH, 0x10048}, + {sizeof(uint32_t) * DC_DISP_BACK_PORCH, 0x90048}, + {sizeof(uint32_t) * DC_DISP_ACTIVE, 0x50002D0}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, +}; + +static const register_write_t display_config_frame_buffer[32] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_POSITION, 0}, + {sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00}, + {sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0}, + {sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0}, + {sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}, +}; + +static const register_write_t display_config_solid_color[8] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, +}; + +static const register_write_t display_config_dsi_01_fini_01[2] = { + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_fini_02[13] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0} +}; + +static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2139}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x4F0F41B1}, + {0, DSI_WR_DATA, 0xF179A433}, + {0, DSI_WR_DATA, 0x2D81}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D6}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x115631}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; \ No newline at end of file diff --git a/fusee/fusee-secondary/src/panic.c b/fusee/fusee-secondary/src/panic.c index 37c0a5a8e..d1432f4b9 100644 --- a/fusee/fusee-secondary/src/panic.c +++ b/fusee/fusee-secondary/src/panic.c @@ -70,7 +70,11 @@ void check_and_display_panic(void) { } /* Initialize the display. */ - display_init(); + if (fuse_get_soc_type() == 1) { + display_init_mariko(); + } else { + display_init_erista(); + } /* Fill the screen. */ display_color_screen(color); diff --git a/sept/sept-secondary/src/di.c b/sept/sept-secondary/src/di.c index 01b23ccb3..2463626b6 100644 --- a/sept/sept-secondary/src/di.c +++ b/sept/sept-secondary/src/di.c @@ -26,38 +26,45 @@ #include "gpio.h" #include "pinmux.h" #include "car.h" +#include "apb_misc.h" #include "di.inl" -static uint32_t _display_ver = 0; +static uint32_t g_lcd_vendor = 0; -static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops) -{ - for (uint32_t i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; +static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + if (writes[i].kind == 1) { + udelay(1000 * writes[i].offset); + } else { + *(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value; + } + } } -static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask) -{ +static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) { + for (uint32_t i = 0; i < num_writes; i++) { + *(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value; + } +} + +static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) { uint32_t end = get_time_us() + timeout; - while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) { + while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) { /* Wait. */ } - udelay(5); + udelay(delay); } -void display_init() -{ +void display_init_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - + /* Power on. */ uint8_t val = 0xD0; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); - val = 0x09; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO7, &val, 1); - + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ car->rst_dev_h_clr = 0x1010000; car->clk_enb_h_set = 0x1010000; @@ -78,43 +85,51 @@ void display_init() pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; pinmux->lcd_rst &= ~PINMUX_TRISTATE; - + /* Configure Backlight +-5V GPIOs. */ gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); - + /* Enable Backlight +5V. */ - gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); udelay(10000); /* Enable Backlight -5V. */ - gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); udelay(10000); /* Configure Backlight PWM, EN and RST GPIOs. */ gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); - gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); - + /* Enable Backlight EN. */ gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); /* Configure display interface and display. */ - MAKE_MIPI_CAL_REG(0x60) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; - exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4); - exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94); - exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60); + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); udelay(10000); - + /* Enable Backlight RST. */ gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); @@ -123,94 +138,297 @@ void display_init() MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; MAKE_DSI_REG(DSI_WR_DATA) = 0x337; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_WR_DATA) = 0x406; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); - _display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); - udelay(5000); - - _display_ver = MAKE_DSI_REG(DSI_RD_DATA); - - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x1105; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - - udelay(180000); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x2905; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } + udelay(20000); - - exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21); - exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3); - + + do_register_writes(CAR_BASE, display_config_plld_02_erista, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; - exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10); + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); udelay(10000); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4); - exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); +} + +void display_init_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Power on. */ + uint8_t val = 0x3A; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1); + val = 0x71; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1); + val = 0xD0; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); + + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ + car->rst_dev_h_clr = 0x1010000; + car->clk_enb_h_set = 0x1010000; + car->rst_dev_l_clr = 0x18000000; + car->clk_enb_l_set = 0x18000000; + car->clk_enb_x_set = 0x20000; + car->clk_source_uart_fst_mipi_cal = 0xA; + car->clk_enb_w_set = 0x80000; + car->clk_source_dsia_lp = 0xA; + + /* DPD idle. */ + pmc->io_dpd_req = 0x40000000; + pmc->io_dpd2_req = 0x40000000; + + /* Configure pins. */ + pinmux->nfc_en &= ~PINMUX_TRISTATE; + pinmux->nfc_int &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; + pinmux->lcd_rst &= ~PINMUX_TRISTATE; + + /* Configure Backlight +-5V GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); udelay(10000); - exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113); + /* Enable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + + udelay(10000); + + /* Configure Backlight PWM, EN and RST GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight EN. */ + gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); + + /* Configure display interface and display. */ + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; + MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0; + MAKE_APB_MISC_REG(0xAC0) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DI_BASE, display_config_dc_01, 94); + do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); + do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); + do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); + do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); + + udelay(10000); + + /* Enable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); + + udelay(60000); + + MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; + MAKE_DSI_REG(DSI_WR_DATA) = 0x337; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x406; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); + + MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); + dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); + + /* Parse LCD vendor. */ + uint32_t host_response[3]; + for (uint32_t i = 0; i < 3; i++) { + host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); + } + + /* The last word from host response is: + Bits 0-7: FAB + Bits 8-15: REV + Bits 16-23: Minor REV + */ + if ((host_response[2] & 0xFF) == 0x10) { + g_lcd_vendor = 0; + } else { + g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; + } + g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); + + /* LCD vendor specific configuration. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); + break; + case 0xF20: /* Innolux first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14); + break; + default: + /* Innolux and AUO second revision screens. */ + if ((g_lcd_vendor | 0x10) == 0x1030) { + do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5); + } + break; + } + + udelay(20000); + + do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3); + do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); + MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; + do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); + + udelay(10000); + + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); + do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); + do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); + + udelay(10000); + + do_register_writes(DI_BASE, display_config_dc_02, 113); } -void display_backlight(bool enable) -{ - /* Enable Backlight PWM. */ - gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); -} - -void display_end() -{ +void display_end_erista(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - + /* Disable Backlight. */ display_backlight(false); - + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; - - exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); - exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16); + + do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); udelay(10000); - - if (_display_ver == 0x10) - exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; udelay(50000); - + /* Disable Backlight RST. */ - gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); udelay(10000); - + /* Disable Backlight -5V. */ - gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); udelay(10000); /* Disable Backlight +5V. */ - gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); udelay(10000); @@ -222,17 +440,103 @@ void display_end() MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)); MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; - + /* Backlight PWM. */ gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); - + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); } -void display_color_screen(uint32_t color) -{ - exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8); +void display_end_mariko(void) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Disable Backlight. */ + display_backlight(false); + + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; + MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + /* Wait 5 frames. */ + uint32_t start_val = MAKE_HOST1X_REG(0x30A4); + while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { + /* Wait. */ + } + + MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; + + do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); + do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); + do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); + + udelay(10000); + + /* LCD vendor specific shutdown. */ + switch (g_lcd_vendor) { + case 0x10: /* Japan Display Inc screens. */ + do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); + break; + case 0xF30: /* AUO first revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38); + break; + case 0x1020: /* Innolux second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10); + break; + case 0x1030: /* AUO second revision screens. */ + do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10); + break; + default: + break; + } + + udelay(5000); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(50000); + + /* Disable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable clocks. */ + car->rst_dev_h_set = 0x1010000; + car->clk_enb_h_clr = 0x1010000; + car->rst_dev_l_set = 0x18000000; + car->clk_enb_l_clr = 0x18000000; + + MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)); + MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; + + /* Backlight PWM. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); + + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); + pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); +} + +void display_backlight(bool enable) { + /* Enable Backlight PWM. */ + gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} + +void display_color_screen(uint32_t color) { + do_register_writes(DI_BASE, display_config_solid_color, 8); /* Configure display to show single color. */ MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; @@ -246,20 +550,19 @@ void display_color_screen(uint32_t color) display_backlight(true); } -uint32_t *display_init_framebuffer(void *address) -{ - static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; - if (conf[0].val == 0) { - for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { - conf[i] = cfg_display_framebuffer[i]; +uint32_t *display_init_framebuffer(void *address) { + static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0}; + if (conf[0].value == 0) { + for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) { + conf[i] = display_config_frame_buffer[i]; } } uint32_t *lfb_addr = (uint32_t *)address; - conf[19].val = (uint32_t)address; - + conf[19].value = (uint32_t)address; + /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */ - exec_cfg((uint32_t *)DI_BASE, conf, 32); + do_register_writes(DI_BASE, conf, 32); udelay(35000); diff --git a/sept/sept-secondary/src/di.h b/sept/sept-secondary/src/di.h index c4ebd538e..6f525fbe2 100644 --- a/sept/sept-secondary/src/di.h +++ b/sept/sept-secondary/src/di.h @@ -15,7 +15,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef FUSEE_DI_H_ #define FUSEE_DI_H_ @@ -33,6 +33,12 @@ #define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) #define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) +/* Clock and reset registers. */ +#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 +#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 +#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 +#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC + /* Display registers. */ #define DC_CMD_GENERAL_INCR_SYNCPT 0x00 @@ -238,6 +244,7 @@ #define DC_WIN_LINE_STRIDE 0x70A #define DC_WIN_DV_CONTROL 0x70E +#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716 /* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ #define DC_WINBUF_START_ADDR 0x800 @@ -333,7 +340,7 @@ #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) -#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E #define DSI_PAD_CONTROL_1 0x4F @@ -346,22 +353,46 @@ #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) #define DSI_PAD_CONTROL_4 0x52 +#define DSI_PAD_CONTROL_5_MARIKO 0x53 +#define DSI_PAD_CONTROL_6_MARIKO 0x54 +#define DSI_PAD_CONTROL_7_MARIKO 0x55 +#define DSI_INIT_SEQ_DATA_15 0x5F +#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62 -typedef struct _cfg_op_t -{ - uint32_t off; - uint32_t val; -} cfg_op_t; +/* MIPI calibration registers. */ +#define MIPI_CAL_MIPI_CAL_CTRL 0x0 +#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0 0x4 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS 0x8 +#define MIPI_CAL_CIL_MIPI_CAL_STATUS_2 0xC +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG 0x14 +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG 0x18 +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG 0x1C +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG 0x20 +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG 0x24 +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG 0x28 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG 0x38 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG 0x3C +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG 0x40 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG 0x44 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 0x58 +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 0x5C +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 0x64 +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 0x68 +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 0x70 +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 0x74 -void display_init(); -void display_end(); - -/* Show one single color on the display. */ -void display_color_screen(uint32_t color); +void display_init_erista(void); +void display_init_mariko(void); +void display_end_erista(void); +void display_end_mariko(void); /* Switches screen backlight ON/OFF. */ void display_backlight(bool enable); +/* Show one single color on the display. */ +void display_color_screen(uint32_t color); + /* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ uint32_t *display_init_framebuffer(void *address); diff --git a/sept/sept-secondary/src/di.inl b/sept/sept-secondary/src/di.inl index e438ca5cb..2544a8f29 100644 --- a/sept/sept-secondary/src/di.inl +++ b/sept/sept-secondary/src/di.inl @@ -1,6 +1,7 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (C) 2018 CTCaer + * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,550 +15,714 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC + +typedef struct { + uint32_t offset; + uint32_t value; +} register_write_t; + +typedef struct { + uint16_t kind; + uint16_t offset; + uint32_t value; +} dsi_sleep_or_register_write_t; + +static const uint32_t display_config_frame_buffer_address = 0xC0000000; + +static const register_write_t display_config_plld_01_erista[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, }; -//Display A config. -static const cfg_op_t _display_config_2[94] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_REG_ACT_CONTROL, 0x54}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, - {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, - {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, - {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} +static const register_write_t display_config_plld_01_mariko[4] = { + {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, }; -//DSI Init config. -static const cfg_op_t _display_config_3[60] = { - {DSI_WR_DATA, 0}, - {DSI_INT_ENABLE, 0}, - {DSI_INT_STATUS, 0}, - {DSI_INT_MASK, 0}, - {DSI_INIT_SEQ_DATA_0, 0}, - {DSI_INIT_SEQ_DATA_1, 0}, - {DSI_INIT_SEQ_DATA_2, 0}, - {DSI_INIT_SEQ_DATA_3, 0}, - {DSI_DCS_CMDS, 0}, - {DSI_PKT_SEQ_0_LO, 0}, - {DSI_PKT_SEQ_1_LO, 0}, - {DSI_PKT_SEQ_2_LO, 0}, - {DSI_PKT_SEQ_3_LO, 0}, - {DSI_PKT_SEQ_4_LO, 0}, - {DSI_PKT_SEQ_5_LO, 0}, - {DSI_PKT_SEQ_0_HI, 0}, - {DSI_PKT_SEQ_1_HI, 0}, - {DSI_PKT_SEQ_2_HI, 0}, - {DSI_PKT_SEQ_3_HI, 0}, - {DSI_PKT_SEQ_4_HI, 0}, - {DSI_PKT_SEQ_5_HI, 0}, - {DSI_CONTROL, 0}, - {DSI_PAD_CONTROL_CD, 0}, - {DSI_SOL_DELAY, 0x18}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_TRIGGER, 0}, - {DSI_INIT_SEQ_CONTROL, 0}, - {DSI_PKT_LEN_0_1, 0}, - {DSI_PKT_LEN_2_3, 0}, - {DSI_PKT_LEN_4_5, 0}, - {DSI_PKT_LEN_6_7, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, 0}, - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30118}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dc_01[94] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1939}, - {DSI_WR_DATA, 0xAAAAAAD8}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAAAAAAAA}, - {DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_WR_DATA, 0xAA}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x1BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2739}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2BD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xF39}, - {DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_WR_DATA, 0xFFFFFF}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xBD15}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x6D915}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_01_init_01[8] = { + {sizeof(uint32_t) * DSI_WR_DATA, 0x0}, + {sizeof(uint32_t) * DSI_INT_ENABLE, 0x0}, + {sizeof(uint32_t) * DSI_INT_STATUS, 0x0}, + {sizeof(uint32_t) * DSI_INT_MASK, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_5[21] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30172}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_PKT_SEQ_0_LO, 0x40000208}, - {DSI_PKT_SEQ_2_LO, 0x40000308}, - {DSI_PKT_SEQ_4_LO, 0x40000308}, - {DSI_PKT_SEQ_1_LO, 0x40000308}, - {DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_3_HI, 0x2CC}, - {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, - {DSI_PKT_SEQ_5_HI, 0x2CC}, - {DSI_PKT_LEN_0_1, 0xCE0000}, - {DSI_PKT_LEN_2_3, 0x87001A2}, - {DSI_PKT_LEN_4_5, 0x190}, - {DSI_PKT_LEN_6_7, 0x190}, - {DSI_HOST_CONTROL, 0}, +static const register_write_t display_config_dsi_01_init_02_erista[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0}, }; -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC +static const register_write_t display_config_dsi_01_init_02_mariko[1] = { + {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, }; -//DSI config. -static const cfg_op_t _display_config_7[10] = { - {DSI_TRIGGER, 0}, - {DSI_CONTROL, 0}, - {DSI_SOL_DELAY, 6}, - {DSI_MAX_THRESHOLD, 0x1E0}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +static const register_write_t display_config_dsi_01_init_03[13] = { + {sizeof(uint32_t) * DSI_DCS_CMDS, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 1}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} +static const register_write_t display_config_dsi_01_init_04_erista[0] = { + /* No register writes. */ }; -//DSI config. -static const cfg_op_t _display_config_9[4] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PAD_CONTROL_2, 0}, - {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, - {DSI_PAD_CONTROL_4, 0} +static const register_write_t display_config_dsi_01_init_04_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, }; -//MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} +static const register_write_t display_config_dsi_01_init_05[11] = { + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -//Display A config. -static const cfg_op_t _display_config_11[113] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {0x4E4, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {0x716, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - /* Set Display timings */ - {DC_DISP_DISP_TIMING_OPTIONS, 0}, - {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. - {DC_DISP_SYNC_WIDTH, 0x10048}, - {DC_DISP_BACK_PORCH, 0x90048}, - {DC_DISP_ACTIVE, 0x50002D0}, - {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. - /* End of Display timings */ - {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, - {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, - {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_DISP_DISP_CLOCK_CONTROL, 0}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} +static const register_write_t display_config_dsi_01_init_06[12] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, }; -////Display A config. -static const cfg_op_t _display_config_12[17] = { - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_INT_MASK, 0}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_INT_ENABLE, 0}, - {DC_CMD_CONT_SYNCPT_VSYNC, 0}, - {DC_CMD_DISPLAY_COMMAND, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_POWER_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +static const register_write_t display_config_dsi_01_init_07[14] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30118}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, }; -//DSI config. -static const cfg_op_t _display_config_13[16] = { - {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, - {DSI_PHY_TIMING_1, 0x40A0E05}, - {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {DSI_TO_TALLY, 0}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, - {DSI_TRIGGER, 0}, - {DSI_TX_CRC, 0}, - {DSI_INIT_SEQ_CONTROL, 0} +static const register_write_t display_config_dsi_phy_timing_erista[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601}, }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0x9483FFB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x2139}, - {DSI_WR_DATA, 0x191919D5}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19191919}, - {DSI_WR_DATA, 0x19}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0xB39}, - {DSI_WR_DATA, 0x4F0F41B1}, - {DSI_WR_DATA, 0xF179A433}, - {DSI_WR_DATA, 0x2D81}, - {DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DSI_WR_DATA, 0x439}, - {DSI_WR_DATA, 0xB9}, - {DSI_TRIGGER, DSI_TRIGGER_HOST} +static const register_write_t display_config_dsi_phy_timing_mariko[1] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603}, }; -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. +static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1939}, + {0, DSI_WR_DATA, 0xAAAAAAD8}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAAA}, + {0, DSI_WR_DATA, 0xAAAAAAEB}, + {0, DSI_WR_DATA, 0xAAEBAAAA}, + {0, DSI_WR_DATA, 0xAA}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2739}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2BD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xF39}, + {0, DSI_WR_DATA, 0xFFFFFFD8}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFFFF}, + {0, DSI_WR_DATA, 0xFFFFFF}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xBD15}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x6D915}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_POSITION, 0}, //(0,0) - {DC_WIN_H_INITIAL_DDA, 0}, - {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {DC_WIN_BUFFER_CONTROL, 0}, - {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. - {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0}, - {DC_WINBUF_ADDR_V_OFFSET, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0xB4, 0}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x739}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x143209}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = { + {0, DSI_WR_DATA, 0x1105}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x78, 0}, + {0, DSI_WR_DATA, 0x2905}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const register_write_t display_config_plld_02_erista[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, +}; + +static const register_write_t display_config_plld_02_mariko[3] = { + {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, + {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, + {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, +}; + +static const register_write_t display_config_dsi_01_init_08[1] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_init_09[19] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30172}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0x40000208}, + {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0x40000308}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0x2CC}, + {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0xCE0000}, + {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0x87001A2}, + {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0x190}, + {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0x190}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, 0}, +}; + +static const register_write_t display_config_dsi_01_init_10[10] = { + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_CONTROL, 0}, + {sizeof(uint32_t) * DSI_SOL_DELAY, 6}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +}; + +static const register_write_t display_config_dsi_01_init_11_erista[4] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0} +}; + +static const register_write_t display_config_dsi_01_init_11_mariko[7] = { + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, +}; + +static const register_write_t display_config_mipi_cal_01[4] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, +}; + +static const register_write_t display_config_mipi_cal_02_erista[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300}, +}; + +static const register_write_t display_config_mipi_cal_02_mariko[2] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_erista[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_03_mariko[6] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, +}; + +static const register_write_t display_config_mipi_cal_04[10] = { + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}, +}; + +static const register_write_t display_config_dc_02[113] = { + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, + {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, + {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, + {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, + {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, + {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, + {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, + {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, + {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)}, + {sizeof(uint32_t) * DC_DISP_SYNC_WIDTH, 0x10048}, + {sizeof(uint32_t) * DC_DISP_BACK_PORCH, 0x90048}, + {sizeof(uint32_t) * DC_DISP_ACTIVE, 0x50002D0}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, +}; + +static const register_write_t display_config_frame_buffer[32] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_WIN_POSITION, 0}, + {sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0}, + {sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, + {sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00}, + {sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0}, + {sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0}, + {sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0}, + {sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}, +}; + +static const register_write_t display_config_solid_color[8] = { + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, + {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, +}; + +static const register_write_t display_config_dsi_01_fini_01[2] = { + {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, + {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, +}; + +static const register_write_t display_config_dsi_01_fini_02[13] = { + {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, + {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, + {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, + {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(uint32_t) * DSI_TO_TALLY, 0}, + {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, + {sizeof(uint32_t) * DSI_TRIGGER, 0}, + {sizeof(uint32_t) * DSI_TX_CRC, 0}, + {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0} +}; + +static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2139}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x4F0F41B1}, + {0, DSI_WR_DATA, 0xF179A433}, + {0, DSI_WR_DATA, 0x2D81}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D5}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x2C39}, + {0, DSI_WR_DATA, 0x191919D6}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_WR_DATA, 0x19191919}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0xB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x751548B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x115631}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; + +static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = { + {0, DSI_WR_DATA, 0x439}, + {0, DSI_WR_DATA, 0x9483FFB9}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, + {0, DSI_WR_DATA, 0xB39}, + {0, DSI_WR_DATA, 0x711148B1}, + {0, DSI_WR_DATA, 0x71143209}, + {0, DSI_WR_DATA, 0x114D31}, + {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {1, 0x5, 0}, +}; \ No newline at end of file diff --git a/sept/sept-secondary/src/main.c b/sept/sept-secondary/src/main.c index 80390d560..2381ca541 100644 --- a/sept/sept-secondary/src/main.c +++ b/sept/sept-secondary/src/main.c @@ -114,7 +114,7 @@ static void setup_env(void) { video_init(g_framebuffer); /* Initialize the display. */ - display_init(); + display_init_erista(); /* Set the framebuffer. */ display_init_framebuffer(g_framebuffer); @@ -131,7 +131,7 @@ static void cleanup_env(void) { unmount_sd(); /* Terminate the display. */ - display_end(); + display_end_erista(); } static void exit_callback(int rc) {