mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-24 07:40:26 +01:00
fusee: perform only pmic reboots on mariko
This commit is contained in:
parent
c06f0440fd
commit
557903cfa7
@ -22,9 +22,11 @@
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#include "fuse.h"
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#include "pmc.h"
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#include "timers.h"
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#include "i2c.h"
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#include "panic.h"
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#include "car.h"
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#include "btn.h"
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#include "max77620.h"
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#include "../../../fusee/common/log.h"
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#include "../../../fusee/common/vsprintf.h"
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#include "../../../fusee/common/display/video_fb.h"
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@ -37,6 +39,37 @@
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#undef u8
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#undef u32
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static bool is_soc_mariko(void) {
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return fuse_get_soc_type() == 1;
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}
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__attribute__((noreturn)) static void shutdown_system(bool reboot) {
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/* Ensure that i2c5 is in a coherent state. */
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i2c_config(I2C_5);
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clkrst_reboot(CARDEVICE_I2C5);
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i2c_init(I2C_5);
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/* Get value, set or clear software reset mask. */
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uint8_t on_off_2_val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
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if (reboot) {
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on_off_2_val |= MAX77620_ONOFFCNFG2_SFT_RST_WK;
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} else {
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on_off_2_val &= ~(MAX77620_ONOFFCNFG2_SFT_RST_WK);
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}
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
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/* Set software reset mask. */
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uint8_t on_off_1_val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
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on_off_1_val |= MAX77620_ONOFFCNFG1_SFT_RST;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
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while (true) {
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/* Wait for reboot. */
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}
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}
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extern uint8_t __reboot_start__[], __reboot_end__[];
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void wait(uint32_t microseconds) {
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@ -70,43 +103,47 @@ __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) {
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}
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__attribute__((noreturn)) void reboot_to_self(void) {
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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if (is_soc_mariko()) {
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/* If mariko, we can't reboot to self/payload, so just reboot. */
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shutdown_system(true);
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} else {
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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/* Copy reboot stub into IRAM high. */
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for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
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/* Copy reboot stub into IRAM high. */
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for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
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}
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/* Copy our low part into safe IRAM. */
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for (size_t i = 0; i < 0x8000; i += sizeof(uint32_t)) {
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write32le((void *)0x40030000, i, read32le((void *)0x40008000, i));
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}
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/* Copy our start page into fatal IRAM. */
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for (size_t i = 0; i < 0x1000; i += sizeof(uint32_t)) {
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write32le((void *)0x4003D000, i, read32le((void *)0x40010000, i));
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}
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/* Copy our reboot handler to the rebootstub target. */
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for (size_t i = 0; i < (__reboot_end__ - __reboot_start__); i += sizeof(uint32_t)) {
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write32le((void *)0x40010000, i, read32le(__reboot_start__, i));
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}
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/* Trigger warm reboot. */
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APBDEV_PMC_SCRATCH0_0 = (1 << 0);
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/* Reset the processor. */
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APBDEV_PMC_CONTROL = BIT(4);
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while (true) {
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/* Wait for reboot. */
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}
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}
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/* Copy our low part into safe IRAM. */
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for (size_t i = 0; i < 0x8000; i += sizeof(uint32_t)) {
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write32le((void *)0x40030000, i, read32le((void *)0x40008000, i));
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}
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/* Copy our start page into fatal IRAM. */
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for (size_t i = 0; i < 0x1000; i += sizeof(uint32_t)) {
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write32le((void *)0x4003D000, i, read32le((void *)0x40010000, i));
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}
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/* Copy our reboot handler to the rebootstub target. */
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for (size_t i = 0; i < (__reboot_end__ - __reboot_start__); i += sizeof(uint32_t)) {
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write32le((void *)0x40010000, i, read32le(__reboot_start__, i));
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}
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/* Trigger warm reboot. */
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APBDEV_PMC_SCRATCH0_0 = (1 << 0);
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/* Reset the processor. */
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APBDEV_PMC_CONTROL = BIT(4);
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while (true) {
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/* Wait for reboot. */
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}
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}
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__attribute__((noreturn)) void wait_for_button_and_reboot(void) {
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@ -13,7 +13,7 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdarg.h>
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#include "utils.h"
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@ -23,7 +23,9 @@
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#include "car.h"
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#include "timers.h"
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#include "btn.h"
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#include "i2c.h"
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#include "panic.h"
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#include "max77620.h"
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#include "../../../fusee/common/log.h"
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#include <stdio.h>
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@ -37,6 +39,37 @@
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#undef u8
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#undef u32
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static bool is_soc_mariko(void) {
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return fuse_get_soc_type() == 1;
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}
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__attribute__((noreturn)) static void shutdown_system(bool reboot) {
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/* Ensure that i2c5 is in a coherent state. */
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i2c_config(I2C_5);
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clkrst_reboot(CARDEVICE_I2C5);
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i2c_init(I2C_5);
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/* Get value, set or clear software reset mask. */
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uint8_t on_off_2_val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
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if (reboot) {
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on_off_2_val |= MAX77620_ONOFFCNFG2_SFT_RST_WK;
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} else {
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on_off_2_val &= ~(MAX77620_ONOFFCNFG2_SFT_RST_WK);
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}
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
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/* Set software reset mask. */
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uint8_t on_off_1_val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
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on_off_1_val |= MAX77620_ONOFFCNFG1_SFT_RST;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
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while (true) {
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/* Wait for reboot. */
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}
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}
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void wait(uint32_t microseconds) {
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uint32_t old_time = TIMERUS_CNTR_1US_0;
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while (TIMERUS_CNTR_1US_0 - old_time <= microseconds) {
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@ -67,21 +100,26 @@ __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) {
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}
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__attribute__((noreturn)) static void reboot_to_payload(void) {
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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/* Copy reboot stub into IRAM high. */
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for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
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if (is_soc_mariko()) {
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/* Reboot to payload isn't possible on mariko, so just do normal reboot. */
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shutdown_system(true);
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} else {
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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/* Copy reboot stub into IRAM high. */
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for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
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}
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/* Trigger warm reboot. */
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pmc_reboot(1 << 0);
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while (true) { }
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}
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/* Trigger warm reboot. */
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pmc_reboot(1 << 0);
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while (true) { }
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}
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__attribute__((noreturn)) void reboot_to_fusee_primary(void) {
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@ -89,38 +127,42 @@ __attribute__((noreturn)) void reboot_to_fusee_primary(void) {
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for (size_t i = 0; i < fusee_primary_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x40010000, i, read32le(fusee_primary_bin, i));
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}
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reboot_to_payload();
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}
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__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size) {
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/* Copy tsec firmware. */
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for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) {
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write32le((void *)0x40010F00, i, read32le(tsec_fw, i));
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if (is_soc_mariko()) {
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/* Reboot to sept isn't possible on mariko, so just do normal reboot. */
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shutdown_system(true);
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} else {
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/* Copy tsec firmware. */
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for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) {
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write32le((void *)0x40010F00, i, read32le(tsec_fw, i));
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}
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MAKE_REG32(0x40010EFC) = tsec_fw_length;
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/* Copy stage 2. */
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for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) {
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write32le((void *)0x40016FE0, i, read32le(stage2, i));
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}
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/* Copy sept into IRAM low. */
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for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i));
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}
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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/* Trigger warm reboot. */
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pmc_reboot(1 << 0);
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while (true) { }
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}
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MAKE_REG32(0x40010EFC) = tsec_fw_length;
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/* Copy stage 2. */
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for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) {
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write32le((void *)0x40016FE0, i, read32le(stage2, i));
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}
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/* Copy sept into IRAM low. */
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for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) {
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write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i));
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}
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/* Patch SDRAM init to perform an SVC immediately after second write */
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APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
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APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
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/* Set SVC handler to jump to reboot stub in IRAM. */
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APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
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APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
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/* Trigger warm reboot. */
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pmc_reboot(1 << 0);
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while (true) { }
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}
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__attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size) {
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@ -128,7 +170,7 @@ __attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payl
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for (size_t i = 0; i < payload_size; i += sizeof(uint32_t)) {
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write32le((void *)0x40010000, i, read32le(payload, i));
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}
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reboot_to_payload();
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}
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@ -159,7 +201,7 @@ __attribute__ ((noreturn)) void generic_panic(void) {
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__attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
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/* Override the global logging level. */
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log_set_log_level(SCREEN_LOG_LEVEL_ERROR);
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/* Display fatal error. */
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va_list args;
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print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: ");
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@ -167,7 +209,7 @@ __attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
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vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args);
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va_end(args);
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print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\n Press POWER to reboot.\n");
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/* Wait for button and reboot. */
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wait_for_button_and_reboot();
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}
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