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https://github.com/Atmosphere-NX/Atmosphere.git
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thermosphere: cpu_on hook & skeleton for other PSCI functions
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4a5d05f32b
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6d33ebceef
@ -19,7 +19,7 @@
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typedef struct CoreCtx {
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u64 kernelArgument;
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u64 kernelEntrypoint;
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uintptr_t kernelEntrypoint;
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u32 coreId; // @ 0x0C
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} CoreCtx;
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@ -1,11 +1,15 @@
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#include <string.h>
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#include "smc.h"
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#include "synchronization.h"
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#include "core_ctx.h"
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// Currently in exception_vectors.s:
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extern const u32 doSmcIndirectCallImpl[];
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extern const u32 doSmcIndirectCallImplSmcInstructionOffset, doSmcIndirectCallImplSize;
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// start.s
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void start2(u64 contextId);
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void doSmcIndirectCall(ExceptionStackFrame *frame, u32 smcId)
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{
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u32 codebuf[doSmcIndirectCallImplSize]; // note: potential VLA
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@ -18,11 +22,53 @@ void doSmcIndirectCall(ExceptionStackFrame *frame, u32 smcId)
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((void (*)(ExceptionStackFrame *))codebuf)(frame);
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}
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static void doCpuOnHook(ExceptionStackFrame *frame, u32 smcId)
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{
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// Note: preserve contexId which is passed by EL3, we'll save it later
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u32 cpuId = (u32)frame->x[1]; // note: full affinity mask. Start.s checks that Aff1,2,3 are 0.
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uintptr_t ep = frame->x[2];
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// frame->x[3] is contextId
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if (cpuId < 4) {
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g_coreCtxs[cpuId].kernelEntrypoint = ep;
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frame->x[2] = (uintptr_t)start2;
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}
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}
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void handleSmcTrap(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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// TODO: Arm PSCI 0.2+ stuff
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u32 smcId = esr.iss;
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// Note: don't differenciate PSCI calls by smc immediate since HOS uses #1 for that
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// Note: funcId is actually u32 according to Arm PSCI. Not sure what to do if x0>>32 != 0.
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// NN doesn't truncate, Arm TF does.
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// Note: clear NN ABI-breaking bits
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u32 funcId = frame->x[0] & ~0xFF00;
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switch (funcId) {
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case 0xC4000001:
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// CPU_SUSPEND
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// TODO
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break;
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case 0x84000002:
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// CPU_OFF
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// TODO
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break;
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case 0xC4000003:
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doCpuOnHook(frame, smcId);
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break;
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case 0x84000008:
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// SYSTEM_OFF, not implemented by Nintendo
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// TODO
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break;
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case 0x84000009:
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// SYSTEM_RESET, not implemented by Nintendo
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// TODO
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break;
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default:
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// Other unimportant functions we don't care about
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break;
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}
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doSmcIndirectCall(frame, smcId);
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skipFaultingInstruction(frame, 4);
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}
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@ -29,6 +29,8 @@ _initialKernelEntrypoint:
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start:
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mov x19, #1
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b _startCommon
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.global start2
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.type start2, %function
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start2:
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mov x19, xzr
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_startCommon:
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@ -57,8 +59,12 @@ _startCommon:
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isb
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// Get core ID
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// Ensure Aff0 is 4-1 at most (4 cores), and that Aff1, 2 and 3 are 0 (1 cluster only)
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mrs x10, mpidr_el1
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and x10, x10, #0xFF
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and x10, x10, #0x00FFFFFF // Aff0 to 2
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and x10, x10, #(0xFF << 32) // Aff3
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cmp x10, #4
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bhs .
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// Set tmp stack (__stacks_top__ is aligned)
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adrp x8, __stacks_top__
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