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https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-24 15:50:29 +01:00
Make sdmmc autocalibration follow TRM procedure
Sleep for 1 us, not 1 ms. Timeout after 10 ms, set driver strength code values according to TRM. Fix typo (mS) - time is in milliseconds, not milliSiemens.
This commit is contained in:
Tomasz Moń
parent
0491a21a99
commit
7b9dcd2f1a
@ -11,4 +11,14 @@
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xa98)
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xab4)
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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#endif
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@ -17,6 +17,7 @@
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#include "supplies.h"
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#include "pmc.h"
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#include "pad_control.h"
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#include "apb_misc.h"
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#define TEGRA_SDMMC_BASE (0x700B0000)
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#define TEGRA_SDMMC_SIZE (0x200)
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@ -462,11 +463,12 @@ enum sdmmc_command_magic {
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/* Misc constants */
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MMC_DEFAULT_BLOCK_ORDER = 9,
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MMC_VOLTAGE_SWITCH_TIME = 5000, // 5mS
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MMC_POST_CLOCK_DELAY = 1000, // 1mS
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MMC_VOLTAGE_SWITCH_TIME = 5000, // 5ms
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MMC_POST_CLOCK_DELAY = 1000, // 1ms
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MMC_SPEED_MMC_OFFSET = 10,
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MMC_TUNING_TIMEOUT = 150 * 1000, // 150mS
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MMC_AUTOCAL_TIMEOUT = 10 * 1000, // 10ms
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MMC_TUNING_TIMEOUT = 150 * 1000, // 150ms
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MMC_TUNING_BLOCK_ORDER_4BIT = 6,
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MMC_TUNING_BLOCK_ORDER_8BIT = 7,
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};
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@ -975,6 +977,7 @@ void sdmmc_clock_enable(struct mmc *mmc, bool enabled)
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static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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{
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uint32_t timebase;
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int ret = 0;
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// Stop the SD card's clock, so our autocal sequence doesn't
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// confuse the target card.
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@ -982,16 +985,34 @@ static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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// Start automatic calibration...
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mmc->regs->auto_cal_config |= (MMC_AUTOCAL_START | MMC_AUTOCAL_ENABLE);
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udelay(1000);
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udelay(1);
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// ... and wait until the autocal is complete
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timebase = get_time();
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while ((mmc->regs->auto_cal_status & MMC_AUTOCAL_ACTIVE)) {
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// Ensure we haven't timed out...
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if (get_time_since(timebase) > mmc->timeout) {
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if (get_time_since(timebase) > MMC_AUTOCAL_TIMEOUT) {
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mmc_print(mmc, "ERROR: autocal timed out!");
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return ETIMEDOUT;
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if (mmc->controller == SWITCH_MICROSD) {
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// Fallback driver strengths from Tegra X1 TRM
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uint32_t drvup = (mmc->operating_voltage == MMC_VOLTAGE_3V3) ? 0x12 : 0x11;
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uint32_t drvdn = (mmc->operating_voltage == MMC_VOLTAGE_3V3) ? 0x12 : 0x15;
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uint32_t value = APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0;
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value &= ~(SDMMC1_PAD_CAL_DRVUP_MASK | SDMMC1_PAD_CAL_DRVDN_MASK);
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value |= (drvup << SDMMC1_PAD_CAL_DRVUP_SHIFT);
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value |= (drvdn << SDMMC1_PAD_CAL_DRVDN_SHIFT);
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APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0 = value;
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} else if (mmc->controller == SWITCH_EMMC) {
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uint32_t value = APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0;
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value &= ~(CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK | CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT);
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APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0 = value;
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}
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mmc->regs->auto_cal_config &= ~MMC_AUTOCAL_ENABLE;
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ret = ETIMEDOUT;
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break;
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}
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}
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@ -999,7 +1020,7 @@ static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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if (restart_sd_clock)
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sdmmc_clock_enable(mmc, true);
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return 0;
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return ret;
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}
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@ -11,4 +11,14 @@
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xa98)
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0 MAKE_REG32(MISC_BASE + 0xab4)
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#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
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#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
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#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
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#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
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#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
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#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
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#endif
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@ -17,6 +17,7 @@
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#include "supplies.h"
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#include "pmc.h"
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#include "pad_control.h"
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#include "apb_misc.h"
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#define TEGRA_SDMMC_BASE (0x700B0000)
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#define TEGRA_SDMMC_SIZE (0x200)
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@ -462,11 +463,12 @@ enum sdmmc_command_magic {
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/* Misc constants */
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MMC_DEFAULT_BLOCK_ORDER = 9,
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MMC_VOLTAGE_SWITCH_TIME = 5000, // 5mS
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MMC_POST_CLOCK_DELAY = 1000, // 1mS
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MMC_VOLTAGE_SWITCH_TIME = 5000, // 5ms
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MMC_POST_CLOCK_DELAY = 1000, // 1ms
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MMC_SPEED_MMC_OFFSET = 10,
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MMC_TUNING_TIMEOUT = 150 * 1000, // 150mS
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MMC_AUTOCAL_TIMEOUT = 10 * 1000, // 10ms
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MMC_TUNING_TIMEOUT = 150 * 1000, // 150ms
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MMC_TUNING_BLOCK_ORDER_4BIT = 6,
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MMC_TUNING_BLOCK_ORDER_8BIT = 7,
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};
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@ -975,6 +977,7 @@ void sdmmc_clock_enable(struct mmc *mmc, bool enabled)
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static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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{
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uint32_t timebase;
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int ret = 0;
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// Stop the SD card's clock, so our autocal sequence doesn't
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// confuse the target card.
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@ -982,16 +985,34 @@ static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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// Start automatic calibration...
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mmc->regs->auto_cal_config |= (MMC_AUTOCAL_START | MMC_AUTOCAL_ENABLE);
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udelay(1000);
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udelay(1);
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// ... and wait until the autocal is complete
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timebase = get_time();
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while ((mmc->regs->auto_cal_status & MMC_AUTOCAL_ACTIVE)) {
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// Ensure we haven't timed out...
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if (get_time_since(timebase) > mmc->timeout) {
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if (get_time_since(timebase) > MMC_AUTOCAL_TIMEOUT) {
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mmc_print(mmc, "ERROR: autocal timed out!");
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return ETIMEDOUT;
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if (mmc->controller == SWITCH_MICROSD) {
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// Fallback driver strengths from Tegra X1 TRM
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uint32_t drvup = (mmc->operating_voltage == MMC_VOLTAGE_3V3) ? 0x12 : 0x11;
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uint32_t drvdn = (mmc->operating_voltage == MMC_VOLTAGE_3V3) ? 0x12 : 0x15;
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uint32_t value = APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0;
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value &= ~(SDMMC1_PAD_CAL_DRVUP_MASK | SDMMC1_PAD_CAL_DRVDN_MASK);
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value |= (drvup << SDMMC1_PAD_CAL_DRVUP_SHIFT);
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value |= (drvdn << SDMMC1_PAD_CAL_DRVDN_SHIFT);
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APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0 = value;
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} else if (mmc->controller == SWITCH_EMMC) {
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uint32_t value = APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0;
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value &= ~(CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK | CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT);
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value |= (0x10 << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT);
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APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0 = value;
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}
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mmc->regs->auto_cal_config &= ~MMC_AUTOCAL_ENABLE;
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ret = ETIMEDOUT;
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break;
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}
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}
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@ -999,7 +1020,7 @@ static int sdmmc_run_autocal(struct mmc *mmc, bool restart_sd_clock)
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if (restart_sd_clock)
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sdmmc_clock_enable(mmc, true);
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return 0;
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return ret;
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}
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