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kern: KSupervisorPageTable now checks wxn instead of setting it
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85b5f20395
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@ -372,6 +372,10 @@ namespace ams::kern::arch::arm64::cpu {
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this->SetBit(19, en);
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return *this;
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}
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constexpr ALWAYS_INLINE bool GetWxn() const {
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return this->GetBits(19, 1) != 0;
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}
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};
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/* Accessors for timer registers. */
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@ -23,9 +23,8 @@ namespace ams::kern::arch::arm64 {
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class KSupervisorPageTable {
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private:
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KPageTable m_page_table;
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u64 m_ttbr0_identity[cpu::NumCores];
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public:
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constexpr KSupervisorPageTable() : m_page_table(util::ConstantInitialize), m_ttbr0_identity() { /* ... */ }
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constexpr KSupervisorPageTable() : m_page_table(util::ConstantInitialize) { /* ... */ }
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NOINLINE void Initialize(s32 core_id);
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@ -61,8 +60,6 @@ namespace ams::kern::arch::arm64 {
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return m_page_table.GetPhysicalAddress(out, address);
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}
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constexpr u64 GetIdentityMapTtbr0(s32 core_id) const { return m_ttbr0_identity[core_id]; }
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void DumpMemoryBlocks() const {
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return m_page_table.DumpMemoryBlocks();
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}
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@ -18,12 +18,8 @@
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namespace ams::kern::arch::arm64 {
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void KSupervisorPageTable::Initialize(s32 core_id) {
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/* Get the identity mapping ttbr0. */
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m_ttbr0_identity[core_id] = cpu::GetTtbr0El1();
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/* Set sctlr_el1 */
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cpu::SystemControlRegisterAccessor().SetWxn(true).Store();
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cpu::EnsureInstructionConsistency();
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/* Verify that sctlr_el1 has the wxn bit set. */
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MESOSPHERE_ABORT_UNLESS(cpu::SystemControlRegisterAccessor().GetWxn());
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/* Invalidate the entire TLB. */
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cpu::InvalidateEntireTlb();
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