mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-28 01:20:58 +01:00
fusee: 11.0.0 support
This commit is contained in:
hexkyz
SciresM
parent
53c684a17a
commit
b918d4b2aa
@ -25,6 +25,7 @@
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#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
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#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
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#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
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@ -176,16 +176,16 @@ static void display_init_erista(void) {
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case 0x10: /* Japan Display Inc screens. */
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do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
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break;
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case 0xF20: /* Innolux first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
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case 0xF20: /* Innolux nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
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break;
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case 0xF30: /* AUO first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
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case 0xF30: /* AUO nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
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break;
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default:
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/* Innolux and AUO second revision screens. */
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/* Innolux and AUO nx-abcc screens. */
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if ((g_lcd_vendor | 0x10) == 0x1030) {
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do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
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do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
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}
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break;
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}
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@ -216,6 +216,7 @@ static void display_init_mariko(void) {
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volatile tegra_car_t *car = car_get_regs();
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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uint32_t hardware_type = fuse_get_hardware_type();
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/* Power on. */
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uint8_t val = 0x3A;
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@ -246,37 +247,43 @@ static void display_init_mariko(void) {
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pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
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pinmux->lcd_rst &= ~PINMUX_TRISTATE;
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/* Configure Backlight +-5V GPIOs. */
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gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
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if (hardware_type == 5) {
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/* HardwareType_Five only configures GPIO_LCD_BL_RST. */
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gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
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} else {
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/* Configure Backlight +-5V GPIOs. */
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gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
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/* Enable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
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udelay(10000);
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/* Enable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
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udelay(10000);
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/* Configure Backlight PWM, EN and RST GPIOs. */
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gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
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/* Enable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
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udelay(10000);
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/* Enable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
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udelay(10000);
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/* Configure Backlight PWM, EN and RST GPIOs. */
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gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
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gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
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gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
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/* Enable Backlight EN. */
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gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
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/* Enable Backlight EN. */
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gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
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}
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/* Configure display interface and display. */
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MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
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MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0;
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MAKE_APB_MISC_REG(0xAC0) = 0;
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APB_MISC_GP_DSI_PAD_CONTROL_0 = 0;
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do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
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do_register_writes(DI_BASE, display_config_dc_01, 94);
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@ -296,8 +303,12 @@ static void display_init_mariko(void) {
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gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
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udelay(60000);
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MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
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if (hardware_type == 5) {
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MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103;
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} else {
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MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
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}
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MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
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MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
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dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
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@ -332,17 +343,20 @@ static void display_init_mariko(void) {
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case 0x10: /* Japan Display Inc screens. */
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do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
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break;
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case 0xF20: /* Innolux first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
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case 0xF20: /* Innolux nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
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break;
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case 0xF30: /* AUO first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
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case 0xF30: /* AUO nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
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break;
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case 0x2050: /* Unknown nx-abcd screens. */
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do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13);
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break;
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case 0x1020: /* Innolux nx-abcc screens. */
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case 0x1030: /* AUO nx-abcc screens. */
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case 0x1040: /* Unknown nx-abcc screens. */
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default:
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/* Innolux and AUO second revision screens. */
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if ((g_lcd_vendor | 0x10) == 0x1030) {
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do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
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}
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do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
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break;
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}
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@ -391,6 +405,9 @@ static void display_end_erista(void) {
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
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do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
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udelay(40000);
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do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
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do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
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do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
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@ -403,14 +420,14 @@ static void display_end_erista(void) {
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case 0x10: /* Japan Display Inc screens. */
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do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
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break;
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case 0xF30: /* AUO first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
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case 0xF30: /* AUO nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
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break;
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case 0x1020: /* Innolux second revision screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
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case 0x1020: /* Innolux nx-abcc screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
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break;
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case 0x1030: /* AUO second revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
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case 0x1030: /* AUO nx-abcc screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
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break;
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default:
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break;
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@ -456,7 +473,6 @@ static void display_end_erista(void) {
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static void display_end_mariko(void) {
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volatile tegra_car_t *car = car_get_regs();
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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/* Disable Backlight. */
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display_backlight(false);
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@ -473,52 +489,61 @@ static void display_end_mariko(void) {
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MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
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do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
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udelay(40000);
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do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
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do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
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do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
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do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13);
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udelay(10000);
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if (g_lcd_vendor != 0x2050) {
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udelay(10000);
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}
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/* LCD vendor specific shutdown. */
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switch (g_lcd_vendor) {
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case 0x10: /* Japan Display Inc screens. */
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do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
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break;
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case 0xF30: /* AUO first revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
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case 0xF30: /* AUO nx-abca2 screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
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break;
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case 0x1020: /* Innolux second revision screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
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case 0x1020: /* Innolux nx-abcc screens. */
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do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
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break;
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case 0x1030: /* AUO second revision screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
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case 0x1030: /* AUO nx-abcc screens. */
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do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
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break;
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case 0x1040: /* Unknown nx-abcc screens. */
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do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10);
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break;
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default:
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break;
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}
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udelay(5000);
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MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
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MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
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udelay(50000);
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udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000);
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/* Disable Backlight RST. */
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gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
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udelay(10000);
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gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
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/* Disable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
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if (g_lcd_vendor == 0x2050) {
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udelay(30000);
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} else {
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udelay(10000);
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/* Disable Backlight -5V. */
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gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
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udelay(10000);
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udelay(10000);
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/* Disable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
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/* Disable Backlight +5V. */
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gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
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udelay(10000);
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udelay(10000);
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}
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/* Disable clocks. */
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car->rst_dev_h_set = 0x1010000;
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@ -528,12 +553,6 @@ static void display_end_mariko(void) {
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MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
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MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
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/* Backlight PWM. */
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gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
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pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
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pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
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}
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void display_init(void) {
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@ -553,8 +572,51 @@ void display_end(void) {
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}
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void display_backlight(bool enable) {
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/* Enable Backlight PWM. */
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gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
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if (g_lcd_vendor == 0x2050) {
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int brightness = enable ? 100 : 0;
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/* Enable FRAME_END_INT */
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MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2;
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/* Configure DSI_LINE_TYPE as FOUR */
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9;
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/* Set and wait for FRAME_END_INT */
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MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
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while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
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/* Wait */
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}
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/* Configure display brightness. */
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const uint32_t brightness_val = ((0x7FF * brightness) / 100);
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MAKE_DSI_REG(DSI_WR_DATA) = 0x339;
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MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51;
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/* Set and wait for FRAME_END_INT */
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MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
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while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
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/* Wait */
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}
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/* Set client sync point block reset. */
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MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1;
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udelay(300000);
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/* Clear client sync point block resest. */
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MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0;
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udelay(300000);
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/* Clear DSI_LINE_TYPE config. */
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MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
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/* Disable FRAME_END_INT */
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MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0;
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MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
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} else {
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/* Enable Backlight PWM. */
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gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
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}
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}
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void display_color_screen(uint32_t color) {
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@ -66,6 +66,7 @@
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#define PM0_ENABLE (1 << 16)
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#define PM1_ENABLE (1 << 18)
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_ENABLE 0x39
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@ -253,6 +254,8 @@
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#define DC_WINBUF_SURFACE_KIND 0x80B
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/* Display serial interface registers. */
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#define DSI_INCR_SYNCPT_CNTRL 0x1
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#define DSI_RD_DATA 0x9
|
||||
#define DSI_WR_DATA 0xA
|
||||
|
||||
|
||||
@ -294,7 +294,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[4
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -311,7 +311,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -328,7 +328,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x78, 0},
|
||||
@ -336,6 +336,22 @@ static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_speci
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
{0, DSI_WR_DATA, 0xA015},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x205315},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x339},
|
||||
{0, DSI_WR_DATA, 0xFF0751},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0x2905},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_plld_02_erista[3] = {
|
||||
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
|
||||
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
|
||||
@ -614,6 +630,22 @@ static const register_write_t display_config_solid_color[8] = {
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dc_01_fini_01[13] = {
|
||||
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_MASK, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_ENABLE, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dsi_01_fini_01[2] = {
|
||||
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
|
||||
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
|
||||
@ -660,7 +692,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[2
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -701,7 +733,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -714,7 +746,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -725,4 +757,17 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini
|
||||
{0, DSI_WR_DATA, 0x114D31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0xB39},
|
||||
{0, DSI_WR_DATA, 0x731348B1},
|
||||
{0, DSI_WR_DATA, 0x71243209},
|
||||
{0, DSI_WR_DATA, 0x4C31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
@ -3290,7 +3290,186 @@ static const uint8_t sdram_params_mariko_11[2104] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
static const uint8_t sdram_params_mariko_12[2104] = {
|
||||
0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00,
|
||||
0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05,
|
||||
0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00,
|
||||
0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xAF, 0xC9, 0x3C, 0x9E, 0x00, 0x00,
|
||||
0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
|
||||
0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
|
||||
0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00,
|
||||
0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00,
|
||||
0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00,
|
||||
0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00,
|
||||
0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00,
|
||||
0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x0E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
|
||||
0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
|
||||
0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91,
|
||||
0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06,
|
||||
0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A,
|
||||
0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23,
|
||||
0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D,
|
||||
0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A,
|
||||
0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x01, 0x88, 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88,
|
||||
0x00, 0x00, 0x00, 0xC0, 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88,
|
||||
0x5D, 0x5D, 0x0E, 0x8C, 0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C,
|
||||
0x00, 0x00, 0x0D, 0x8C, 0x14, 0x14, 0x16, 0x88, 0x04, 0x00, 0x01, 0x88,
|
||||
0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xCC, 0x00,
|
||||
0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x25, 0x08, 0x11, 0x00,
|
||||
0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00,
|
||||
0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80,
|
||||
0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00,
|
||||
0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29,
|
||||
0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29,
|
||||
0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00,
|
||||
0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00,
|
||||
0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00,
|
||||
0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00,
|
||||
0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x16, 0x00, 0x16, 0x00,
|
||||
0x0D, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x0B, 0x00, 0x17, 0x00, 0x17, 0x00,
|
||||
0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00,
|
||||
0x4F, 0x00, 0x51, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0xAB, 0x00, 0x0A, 0x04, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F,
|
||||
0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9F, 0xFF, 0x37, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65,
|
||||
0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32,
|
||||
0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67,
|
||||
0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00,
|
||||
0xFF, 0x9F, 0xAF, 0x4F, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x40,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x34, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x05, 0x00, 0x00, 0x00, 0x05,
|
||||
0x10, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x21, 0x04, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x00, 0x20, 0x00, 0x00, 0x00,
|
||||
0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x10, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x1C,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x08, 0x00, 0x02, 0x03, 0x08, 0x00,
|
||||
0x00, 0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39,
|
||||
0x00, 0x10, 0x9C, 0x4B, 0x00, 0x10, 0x00, 0x00, 0x01, 0x00, 0x00, 0x08,
|
||||
0x4C, 0x00, 0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
|
||||
0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x01, 0x02, 0x03, 0x00,
|
||||
0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xFF, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0xCB, 0xFA, 0xE4,
|
||||
0xD3, 0xFE, 0x00, 0x06, 0x00, 0x00, 0x80, 0x2A, 0x02, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x16, 0x40, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[29] = {
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
@ -3319,6 +3498,7 @@ static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static const uint32_t *sdram_params_erista[7] = {
|
||||
@ -3331,11 +3511,11 @@ static const uint32_t *sdram_params_erista[7] = {
|
||||
(const uint32_t *)sdram_params_erista_6,
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xFFFFFFFF,
|
||||
static const uint32_t sdram_params_index_table_mariko[29] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xC,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
@ -3360,6 +3540,7 @@ static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xB,
|
||||
0xB,
|
||||
0xB,
|
||||
7,
|
||||
};
|
||||
|
||||
static const uint32_t *sdram_params_mariko[12] = {
|
||||
@ -3375,4 +3556,5 @@ static const uint32_t *sdram_params_mariko[12] = {
|
||||
(const uint32_t *)sdram_params_mariko_9,
|
||||
(const uint32_t *)sdram_params_mariko_10,
|
||||
(const uint32_t *)sdram_params_mariko_11,
|
||||
(const uint32_t *)sdram_params_mariko_12,
|
||||
};
|
||||
|
||||
@ -124,7 +124,7 @@ static const uint8_t sdram_params_erista_lz[1262] = {
|
||||
0x8E, 0x68
|
||||
};
|
||||
|
||||
static const uint8_t sdram_params_mariko_lz[1727] = {
|
||||
static const uint8_t sdram_params_mariko_lz[1741] = {
|
||||
0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
|
||||
0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08,
|
||||
0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A,
|
||||
@ -268,10 +268,12 @@ static const uint8_t sdram_params_mariko_lz[1727] = {
|
||||
0x38, 0x08, 0x29, 0x32, 0x93, 0xA5, 0x54, 0x4A, 0x6B, 0x76, 0x87, 0x19,
|
||||
0x82, 0x29, 0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A,
|
||||
0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1,
|
||||
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28
|
||||
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x85, 0x7C, 0xB1, 0x28, 0x19,
|
||||
0x8B, 0x21, 0x90, 0x38, 0x19, 0x82, 0x3F, 0xA0, 0x70, 0x19, 0x24, 0x90,
|
||||
0x38
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
static const uint32_t sdram_params_index_table_erista[29] = {
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
@ -300,13 +302,14 @@ static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xFFFFFFFF,
|
||||
static const uint32_t sdram_params_index_table_mariko[29] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xC,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
@ -331,4 +334,5 @@ static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xB,
|
||||
0xB,
|
||||
0xB,
|
||||
7,
|
||||
};
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
|
||||
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
|
||||
#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
|
||||
|
||||
|
||||
@ -176,16 +176,16 @@ static void display_init_erista(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
|
||||
break;
|
||||
case 0xF20: /* Innolux first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
|
||||
case 0xF20: /* Innolux nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
default:
|
||||
/* Innolux and AUO second revision screens. */
|
||||
/* Innolux and AUO nx-abcc screens. */
|
||||
if ((g_lcd_vendor | 0x10) == 0x1030) {
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -216,6 +216,7 @@ static void display_init_mariko(void) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
uint32_t hardware_type = fuse_get_hardware_type();
|
||||
|
||||
/* Power on. */
|
||||
uint8_t val = 0x3A;
|
||||
@ -246,37 +247,43 @@ static void display_init_mariko(void) {
|
||||
pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
|
||||
pinmux->lcd_rst &= ~PINMUX_TRISTATE;
|
||||
|
||||
/* Configure Backlight +-5V GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
|
||||
if (hardware_type == 5) {
|
||||
/* HardwareType_Five only configures GPIO_LCD_BL_RST. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
} else {
|
||||
/* Configure Backlight +-5V GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Configure Backlight PWM, EN and RST GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Configure Backlight PWM, EN and RST GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight EN. */
|
||||
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
|
||||
/* Enable Backlight EN. */
|
||||
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
|
||||
}
|
||||
|
||||
/* Configure display interface and display. */
|
||||
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
|
||||
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0;
|
||||
MAKE_APB_MISC_REG(0xAC0) = 0;
|
||||
APB_MISC_GP_DSI_PAD_CONTROL_0 = 0;
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
|
||||
do_register_writes(DI_BASE, display_config_dc_01, 94);
|
||||
@ -296,8 +303,12 @@ static void display_init_mariko(void) {
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(60000);
|
||||
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
|
||||
|
||||
if (hardware_type == 5) {
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103;
|
||||
} else {
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
|
||||
}
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
|
||||
@ -332,17 +343,20 @@ static void display_init_mariko(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
|
||||
break;
|
||||
case 0xF20: /* Innolux first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
|
||||
case 0xF20: /* Innolux nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0x2050: /* Unknown nx-abcd screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13);
|
||||
break;
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
case 0x1040: /* Unknown nx-abcc screens. */
|
||||
default:
|
||||
/* Innolux and AUO second revision screens. */
|
||||
if ((g_lcd_vendor | 0x10) == 0x1030) {
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
|
||||
}
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -391,6 +405,9 @@ static void display_end_erista(void) {
|
||||
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
|
||||
udelay(40000);
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
|
||||
@ -403,14 +420,14 @@ static void display_end_erista(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
|
||||
break;
|
||||
case 0x1020: /* Innolux second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1030: /* AUO second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@ -456,7 +473,6 @@ static void display_end_erista(void) {
|
||||
|
||||
static void display_end_mariko(void) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
|
||||
/* Disable Backlight. */
|
||||
display_backlight(false);
|
||||
@ -473,52 +489,61 @@ static void display_end_mariko(void) {
|
||||
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
|
||||
udelay(40000);
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13);
|
||||
|
||||
udelay(10000);
|
||||
if (g_lcd_vendor != 0x2050) {
|
||||
udelay(10000);
|
||||
}
|
||||
|
||||
/* LCD vendor specific shutdown. */
|
||||
switch (g_lcd_vendor) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
|
||||
break;
|
||||
case 0x1020: /* Innolux second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1030: /* AUO second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1040: /* Unknown nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
udelay(5000);
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
|
||||
udelay(50000);
|
||||
udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000);
|
||||
|
||||
/* Disable Backlight RST. */
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
|
||||
|
||||
/* Disable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
|
||||
if (g_lcd_vendor == 0x2050) {
|
||||
udelay(30000);
|
||||
} else {
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
|
||||
/* Disable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
udelay(10000);
|
||||
}
|
||||
|
||||
/* Disable clocks. */
|
||||
car->rst_dev_h_set = 0x1010000;
|
||||
@ -528,12 +553,6 @@ static void display_end_mariko(void) {
|
||||
|
||||
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
|
||||
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
|
||||
|
||||
/* Backlight PWM. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
|
||||
|
||||
pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
|
||||
pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
|
||||
}
|
||||
|
||||
void display_init(void) {
|
||||
@ -553,8 +572,51 @@ void display_end(void) {
|
||||
}
|
||||
|
||||
void display_backlight(bool enable) {
|
||||
/* Enable Backlight PWM. */
|
||||
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
|
||||
if (g_lcd_vendor == 0x2050) {
|
||||
int brightness = enable ? 100 : 0;
|
||||
|
||||
/* Enable FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2;
|
||||
|
||||
/* Configure DSI_LINE_TYPE as FOUR */
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9;
|
||||
|
||||
/* Set and wait for FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Configure display brightness. */
|
||||
const uint32_t brightness_val = ((0x7FF * brightness) / 100);
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x339;
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51;
|
||||
|
||||
/* Set and wait for FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Set client sync point block reset. */
|
||||
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1;
|
||||
udelay(300000);
|
||||
|
||||
/* Clear client sync point block resest. */
|
||||
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0;
|
||||
udelay(300000);
|
||||
|
||||
/* Clear DSI_LINE_TYPE config. */
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
/* Disable FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0;
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
} else {
|
||||
/* Enable Backlight PWM. */
|
||||
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
|
||||
}
|
||||
}
|
||||
|
||||
void display_color_screen(uint32_t color) {
|
||||
|
||||
@ -66,6 +66,7 @@
|
||||
#define PM0_ENABLE (1 << 16)
|
||||
#define PM1_ENABLE (1 << 18)
|
||||
|
||||
#define DC_CMD_INT_STATUS 0x37
|
||||
#define DC_CMD_INT_MASK 0x38
|
||||
#define DC_CMD_INT_ENABLE 0x39
|
||||
|
||||
@ -253,6 +254,8 @@
|
||||
#define DC_WINBUF_SURFACE_KIND 0x80B
|
||||
|
||||
/* Display serial interface registers. */
|
||||
#define DSI_INCR_SYNCPT_CNTRL 0x1
|
||||
|
||||
#define DSI_RD_DATA 0x9
|
||||
#define DSI_WR_DATA 0xA
|
||||
|
||||
|
||||
@ -294,7 +294,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[4
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -311,7 +311,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -328,7 +328,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x78, 0},
|
||||
@ -336,6 +336,22 @@ static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_speci
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
{0, DSI_WR_DATA, 0xA015},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x205315},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x339},
|
||||
{0, DSI_WR_DATA, 0xFF0751},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0x2905},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_plld_02_erista[3] = {
|
||||
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
|
||||
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
|
||||
@ -614,6 +630,22 @@ static const register_write_t display_config_solid_color[8] = {
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dc_01_fini_01[13] = {
|
||||
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_MASK, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_ENABLE, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dsi_01_fini_01[2] = {
|
||||
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
|
||||
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
|
||||
@ -660,7 +692,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[2
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -701,7 +733,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -714,7 +746,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -725,4 +757,17 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini
|
||||
{0, DSI_WR_DATA, 0x114D31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0xB39},
|
||||
{0, DSI_WR_DATA, 0x731348B1},
|
||||
{0, DSI_WR_DATA, 0x71243209},
|
||||
{0, DSI_WR_DATA, 0x4C31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
@ -25,6 +25,7 @@
|
||||
#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
|
||||
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
|
||||
#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
|
||||
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
|
||||
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
|
||||
#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
|
||||
|
||||
|
||||
@ -176,16 +176,16 @@ static void display_init_erista(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
|
||||
break;
|
||||
case 0xF20: /* Innolux first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
|
||||
case 0xF20: /* Innolux nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
default:
|
||||
/* Innolux and AUO second revision screens. */
|
||||
/* Innolux and AUO nx-abcc screens. */
|
||||
if ((g_lcd_vendor | 0x10) == 0x1030) {
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -216,6 +216,7 @@ static void display_init_mariko(void) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
uint32_t hardware_type = fuse_get_hardware_type();
|
||||
|
||||
/* Power on. */
|
||||
uint8_t val = 0x3A;
|
||||
@ -246,37 +247,43 @@ static void display_init_mariko(void) {
|
||||
pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
|
||||
pinmux->lcd_rst &= ~PINMUX_TRISTATE;
|
||||
|
||||
/* Configure Backlight +-5V GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
|
||||
if (hardware_type == 5) {
|
||||
/* HardwareType_Five only configures GPIO_LCD_BL_RST. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
} else {
|
||||
/* Configure Backlight +-5V GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Configure Backlight PWM, EN and RST GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Configure Backlight PWM, EN and RST GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight EN. */
|
||||
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
|
||||
/* Enable Backlight EN. */
|
||||
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
|
||||
}
|
||||
|
||||
/* Configure display interface and display. */
|
||||
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
|
||||
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0;
|
||||
MAKE_APB_MISC_REG(0xAC0) = 0;
|
||||
APB_MISC_GP_DSI_PAD_CONTROL_0 = 0;
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
|
||||
do_register_writes(DI_BASE, display_config_dc_01, 94);
|
||||
@ -296,8 +303,12 @@ static void display_init_mariko(void) {
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(60000);
|
||||
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
|
||||
|
||||
if (hardware_type == 5) {
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103;
|
||||
} else {
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
|
||||
}
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
|
||||
@ -332,17 +343,20 @@ static void display_init_mariko(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
|
||||
break;
|
||||
case 0xF20: /* Innolux first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev1_specific_init_01, 14);
|
||||
case 0xF20: /* Innolux nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_init_01, 14);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
|
||||
break;
|
||||
case 0x2050: /* Unknown nx-abcd screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13);
|
||||
break;
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
case 0x1040: /* Unknown nx-abcc screens. */
|
||||
default:
|
||||
/* Innolux and AUO second revision screens. */
|
||||
if ((g_lcd_vendor | 0x10) == 0x1030) {
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_rev2_specific_init_01, 5);
|
||||
}
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -391,6 +405,9 @@ static void display_end_erista(void) {
|
||||
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
|
||||
udelay(40000);
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
|
||||
@ -403,14 +420,14 @@ static void display_end_erista(void) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
|
||||
break;
|
||||
case 0x1020: /* Innolux second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1030: /* AUO second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@ -456,7 +473,6 @@ static void display_end_erista(void) {
|
||||
|
||||
static void display_end_mariko(void) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
|
||||
/* Disable Backlight. */
|
||||
display_backlight(false);
|
||||
@ -473,52 +489,61 @@ static void display_end_mariko(void) {
|
||||
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
|
||||
udelay(40000);
|
||||
|
||||
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
|
||||
do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13);
|
||||
|
||||
udelay(10000);
|
||||
if (g_lcd_vendor != 0x2050) {
|
||||
udelay(10000);
|
||||
}
|
||||
|
||||
/* LCD vendor specific shutdown. */
|
||||
switch (g_lcd_vendor) {
|
||||
case 0x10: /* Japan Display Inc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
|
||||
break;
|
||||
case 0xF30: /* AUO first revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev1_specific_fini_01, 38);
|
||||
case 0xF30: /* AUO nx-abca2 screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
|
||||
break;
|
||||
case 0x1020: /* Innolux second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_rev2_specific_fini_01, 10);
|
||||
case 0x1020: /* Innolux nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1030: /* AUO second revision screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_rev2_specific_fini_01, 10);
|
||||
case 0x1030: /* AUO nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
case 0x1040: /* Unknown nx-abcc screens. */
|
||||
do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
udelay(5000);
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
|
||||
udelay(50000);
|
||||
udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000);
|
||||
|
||||
/* Disable Backlight RST. */
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
|
||||
|
||||
/* Disable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
|
||||
if (g_lcd_vendor == 0x2050) {
|
||||
udelay(30000);
|
||||
} else {
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
|
||||
/* Disable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
udelay(10000);
|
||||
}
|
||||
|
||||
/* Disable clocks. */
|
||||
car->rst_dev_h_set = 0x1010000;
|
||||
@ -528,12 +553,6 @@ static void display_end_mariko(void) {
|
||||
|
||||
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
|
||||
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
|
||||
|
||||
/* Backlight PWM. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
|
||||
|
||||
pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
|
||||
pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
|
||||
}
|
||||
|
||||
void display_init(void) {
|
||||
@ -553,8 +572,51 @@ void display_end(void) {
|
||||
}
|
||||
|
||||
void display_backlight(bool enable) {
|
||||
/* Enable Backlight PWM. */
|
||||
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
|
||||
if (g_lcd_vendor == 0x2050) {
|
||||
int brightness = enable ? 100 : 0;
|
||||
|
||||
/* Enable FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2;
|
||||
|
||||
/* Configure DSI_LINE_TYPE as FOUR */
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9;
|
||||
|
||||
/* Set and wait for FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Configure display brightness. */
|
||||
const uint32_t brightness_val = ((0x7FF * brightness) / 100);
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x339;
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51;
|
||||
|
||||
/* Set and wait for FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Set client sync point block reset. */
|
||||
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1;
|
||||
udelay(300000);
|
||||
|
||||
/* Clear client sync point block resest. */
|
||||
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0;
|
||||
udelay(300000);
|
||||
|
||||
/* Clear DSI_LINE_TYPE config. */
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
/* Disable FRAME_END_INT */
|
||||
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0;
|
||||
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
|
||||
} else {
|
||||
/* Enable Backlight PWM. */
|
||||
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
|
||||
}
|
||||
}
|
||||
|
||||
void display_color_screen(uint32_t color) {
|
||||
|
||||
@ -66,6 +66,7 @@
|
||||
#define PM0_ENABLE (1 << 16)
|
||||
#define PM1_ENABLE (1 << 18)
|
||||
|
||||
#define DC_CMD_INT_STATUS 0x37
|
||||
#define DC_CMD_INT_MASK 0x38
|
||||
#define DC_CMD_INT_ENABLE 0x39
|
||||
|
||||
@ -253,6 +254,8 @@
|
||||
#define DC_WINBUF_SURFACE_KIND 0x80B
|
||||
|
||||
/* Display serial interface registers. */
|
||||
#define DSI_INCR_SYNCPT_CNTRL 0x1
|
||||
|
||||
#define DSI_RD_DATA 0x9
|
||||
#define DSI_WR_DATA 0xA
|
||||
|
||||
|
||||
@ -294,7 +294,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[4
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -311,7 +311,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev1_specific_
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init_01[14] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
@ -328,7 +328,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_init
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_specific_init_01[5] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x78, 0},
|
||||
@ -336,6 +336,22 @@ static const dsi_sleep_or_register_write_t display_config_innolux_auo_rev2_speci
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = {
|
||||
{0, DSI_WR_DATA, 0x1105},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0xB4, 0},
|
||||
{0, DSI_WR_DATA, 0xA015},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x205315},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{0, DSI_WR_DATA, 0x339},
|
||||
{0, DSI_WR_DATA, 0xFF0751},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0x2905},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_plld_02_erista[3] = {
|
||||
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
|
||||
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
|
||||
@ -614,6 +630,22 @@ static const register_write_t display_config_solid_color[8] = {
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dc_01_fini_01[13] = {
|
||||
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_MASK, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_INT_ENABLE, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, 0},
|
||||
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
};
|
||||
|
||||
static const register_write_t display_config_dsi_01_fini_01[2] = {
|
||||
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
|
||||
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
|
||||
@ -660,7 +692,7 @@ static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[2
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini_01[38] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -701,7 +733,7 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev1_specific_fini
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -714,7 +746,7 @@ static const dsi_sleep_or_register_write_t display_config_innolux_rev2_specific_
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini_01[10] = {
|
||||
static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
@ -725,4 +757,17 @@ static const dsi_sleep_or_register_write_t display_config_auo_rev2_specific_fini
|
||||
{0, DSI_WR_DATA, 0x114D31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
|
||||
static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = {
|
||||
{0, DSI_WR_DATA, 0x439},
|
||||
{0, DSI_WR_DATA, 0x9483FFB9},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
{0, DSI_WR_DATA, 0xB39},
|
||||
{0, DSI_WR_DATA, 0x731348B1},
|
||||
{0, DSI_WR_DATA, 0x71243209},
|
||||
{0, DSI_WR_DATA, 0x4C31},
|
||||
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{1, 0x5, 0},
|
||||
};
|
||||
@ -3290,7 +3290,186 @@ static const uint8_t sdram_params_mariko_11[2104] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
static const uint8_t sdram_params_mariko_12[2104] = {
|
||||
0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00,
|
||||
0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05,
|
||||
0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00,
|
||||
0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xAF, 0xC9, 0x3C, 0x9E, 0x00, 0x00,
|
||||
0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
|
||||
0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
|
||||
0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00,
|
||||
0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00,
|
||||
0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00,
|
||||
0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00,
|
||||
0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00,
|
||||
0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x0E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
|
||||
0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
|
||||
0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91,
|
||||
0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06,
|
||||
0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A,
|
||||
0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23,
|
||||
0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D,
|
||||
0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A,
|
||||
0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x01, 0x88, 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88,
|
||||
0x00, 0x00, 0x00, 0xC0, 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88,
|
||||
0x5D, 0x5D, 0x0E, 0x8C, 0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C,
|
||||
0x00, 0x00, 0x0D, 0x8C, 0x14, 0x14, 0x16, 0x88, 0x04, 0x00, 0x01, 0x88,
|
||||
0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xCC, 0x00,
|
||||
0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x25, 0x08, 0x11, 0x00,
|
||||
0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00,
|
||||
0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80,
|
||||
0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00,
|
||||
0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29,
|
||||
0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29,
|
||||
0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00,
|
||||
0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00,
|
||||
0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00,
|
||||
0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00,
|
||||
0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00,
|
||||
0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x16, 0x00, 0x16, 0x00,
|
||||
0x0D, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x0B, 0x00, 0x17, 0x00, 0x17, 0x00,
|
||||
0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00,
|
||||
0x4F, 0x00, 0x51, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0xAB, 0x00, 0x0A, 0x04, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F,
|
||||
0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9F, 0xFF, 0x37, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65,
|
||||
0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32,
|
||||
0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67,
|
||||
0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00,
|
||||
0xFF, 0x9F, 0xAF, 0x4F, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x40,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x34, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x05, 0x00, 0x00, 0x00, 0x05,
|
||||
0x10, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x21, 0x04, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x00, 0x20, 0x00, 0x00, 0x00,
|
||||
0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x10, 0x10, 0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x1C,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x08, 0x00, 0x02, 0x03, 0x08, 0x00,
|
||||
0x00, 0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39,
|
||||
0x00, 0x10, 0x9C, 0x4B, 0x00, 0x10, 0x00, 0x00, 0x01, 0x00, 0x00, 0x08,
|
||||
0x4C, 0x00, 0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
|
||||
0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x01, 0x02, 0x03, 0x00,
|
||||
0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xFF, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0xCB, 0xFA, 0xE4,
|
||||
0xD3, 0xFE, 0x00, 0x06, 0x00, 0x00, 0x80, 0x2A, 0x02, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x16, 0x40, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[29] = {
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
@ -3319,6 +3498,7 @@ static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static const uint32_t *sdram_params_erista[7] = {
|
||||
@ -3331,11 +3511,11 @@ static const uint32_t *sdram_params_erista[7] = {
|
||||
(const uint32_t *)sdram_params_erista_6,
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xFFFFFFFF,
|
||||
static const uint32_t sdram_params_index_table_mariko[29] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xC,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
@ -3360,6 +3540,7 @@ static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xB,
|
||||
0xB,
|
||||
0xB,
|
||||
7,
|
||||
};
|
||||
|
||||
static const uint32_t *sdram_params_mariko[12] = {
|
||||
@ -3375,4 +3556,5 @@ static const uint32_t *sdram_params_mariko[12] = {
|
||||
(const uint32_t *)sdram_params_mariko_9,
|
||||
(const uint32_t *)sdram_params_mariko_10,
|
||||
(const uint32_t *)sdram_params_mariko_11,
|
||||
(const uint32_t *)sdram_params_mariko_12,
|
||||
};
|
||||
|
||||
@ -124,7 +124,7 @@ static const uint8_t sdram_params_erista_lz[1262] = {
|
||||
0x8E, 0x68
|
||||
};
|
||||
|
||||
static const uint8_t sdram_params_mariko_lz[1727] = {
|
||||
static const uint8_t sdram_params_mariko_lz[1741] = {
|
||||
0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
|
||||
0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08,
|
||||
0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A,
|
||||
@ -268,10 +268,12 @@ static const uint8_t sdram_params_mariko_lz[1727] = {
|
||||
0x38, 0x08, 0x29, 0x32, 0x93, 0xA5, 0x54, 0x4A, 0x6B, 0x76, 0x87, 0x19,
|
||||
0x82, 0x29, 0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A,
|
||||
0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1,
|
||||
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28
|
||||
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x85, 0x7C, 0xB1, 0x28, 0x19,
|
||||
0x8B, 0x21, 0x90, 0x38, 0x19, 0x82, 0x3F, 0xA0, 0x70, 0x19, 0x24, 0x90,
|
||||
0x38
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
static const uint32_t sdram_params_index_table_erista[29] = {
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
@ -300,13 +302,14 @@ static const uint32_t sdram_params_index_table_erista[28] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xFFFFFFFF,
|
||||
static const uint32_t sdram_params_index_table_mariko[29] = {
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xC,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
0xFFFFFFFF,
|
||||
@ -331,4 +334,5 @@ static const uint32_t sdram_params_index_table_mariko[28] = {
|
||||
0xB,
|
||||
0xB,
|
||||
0xB,
|
||||
7,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user