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boot: implement ShowSplashScreen/Display

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This commit is contained in:
Michael Scire 2019-05-03 05:00:03 -07:00
parent 93fb060fac
commit d9da531b41
14 changed files with 1979 additions and 1 deletions
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539
stratosphere/boot/source/boot_display.cpp Normal file
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/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "boot_functions.hpp"
#include "boot_display_config.hpp"
#include "i2c_driver/i2c_api.hpp"
/* Helpful defines. */
constexpr size_t DeviceAddressSpaceAlignSize = 0x400000;
constexpr size_t DeviceAddressSpaceAlignMask = DeviceAddressSpaceAlignSize - 1;
constexpr uintptr_t FrameBufferPaddr = DisplayConfigFrameBufferAddress;
constexpr size_t FrameBufferWidth = 768;
constexpr size_t FrameBufferHeight = 1280;
constexpr size_t FrameBufferSize = FrameBufferHeight * FrameBufferWidth * sizeof(u32);
constexpr uintptr_t Disp1Base = 0x54200000ul;
constexpr uintptr_t DsiBase = 0x54300000ul;
constexpr uintptr_t ClkRstBase = 0x60006000ul;
constexpr uintptr_t GpioBase = 0x6000D000ul;
constexpr uintptr_t ApbMiscBase = 0x70000000ul;
constexpr uintptr_t MipiCalBase = 0x700E3000ul;
constexpr size_t Disp1Size = 0x3000;
constexpr size_t DsiSize = 0x1000;
constexpr size_t ClkRstSize = 0x1000;
constexpr size_t GpioSize = 0x1000;
constexpr size_t ApbMiscSize = 0x1000;
constexpr size_t MipiCalSize = 0x1000;
/* Types. */
/* Globals. */
static bool g_is_display_intialized = false;
static u32 *g_frame_buffer = nullptr;
static bool g_is_mariko = false;
static u32 g_lcd_vendor = 0;
static Handle g_dc_das_hnd = INVALID_HANDLE;
static u8 g_frame_buffer_storage[DeviceAddressSpaceAlignSize + FrameBufferSize];
static uintptr_t g_disp1_regs = 0;
static uintptr_t g_dsi_regs = 0;
static uintptr_t g_clk_rst_regs = 0;
static uintptr_t g_gpio_regs = 0;
static uintptr_t g_apb_misc_regs = 0;
static uintptr_t g_mipi_cal_regs = 0;
static inline uintptr_t QueryVirtualAddress(uintptr_t phys, size_t size) {
uintptr_t aligned_phys = phys & ~0xFFFul;
size_t aligned_size = size + (phys - aligned_phys);
uintptr_t aligned_virt;
if (R_FAILED(svcQueryIoMapping(&aligned_virt, aligned_phys, aligned_size))) {
std::abort();
}
return aligned_virt + (phys - aligned_phys);
}
static inline void WriteRegister(volatile u32 *reg, u32 val) {
*reg = val;
}
static inline void WriteRegister(uintptr_t reg, u32 val) {
WriteRegister(reinterpret_cast<volatile u32 *>(reg), val);
}
static inline u32 ReadRegister(volatile u32 *reg) {
u32 val = *reg;
return val;
}
static inline u32 ReadRegister(uintptr_t reg) {
return ReadRegister(reinterpret_cast<volatile u32 *>(reg));
}
static inline void SetRegisterBits(volatile u32 *reg, u32 mask) {
*reg |= mask;
}
static inline void SetRegisterBits(uintptr_t reg, u32 mask) {
SetRegisterBits(reinterpret_cast<volatile u32 *>(reg), mask);
}
static inline void ClearRegisterBits(volatile u32 *reg, u32 mask) {
*reg &= mask;
}
static inline void ClearRegisterBits(uintptr_t reg, u32 mask) {
ClearRegisterBits(reinterpret_cast<volatile u32 *>(reg), mask);
}
static inline void ReadWriteRegisterBits(volatile u32 *reg, u32 val, u32 mask) {
*reg = (*reg & (~mask)) | (val & mask);
}
static inline void ReadWriteRegisterBits(uintptr_t reg, u32 val, u32 mask) {
ReadWriteRegisterBits(reinterpret_cast<volatile u32 *>(reg), val, mask);
}
static void InitializeRegisterBaseAddresses() {
g_disp1_regs = QueryVirtualAddress(Disp1Base, Disp1Size);
g_dsi_regs = QueryVirtualAddress(DsiBase, DsiSize);
g_clk_rst_regs = QueryVirtualAddress(ClkRstBase, ClkRstSize);
g_gpio_regs = QueryVirtualAddress(GpioBase, GpioSize);
g_apb_misc_regs = QueryVirtualAddress(ApbMiscBase, ApbMiscSize);
g_mipi_cal_regs = QueryVirtualAddress(MipiCalBase, MipiCalSize);
}
static inline void DoRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes, size_t num_writes) {
for (size_t i = 0; i < num_writes; i++) {
*(reinterpret_cast<volatile u32 *>(base_address + reg_writes[i].offset)) = reg_writes[i].value;
}
}
static inline void DoSocDependentRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes_erista, size_t num_writes_erista, const RegisterWrite *reg_writes_mariko, size_t num_writes_mariko) {
if (g_is_mariko) {
DoRegisterWrites(base_address, reg_writes_mariko, num_writes_mariko);
} else {
DoRegisterWrites(base_address, reg_writes_erista, num_writes_erista);
}
}
static inline void DoDsiSleepOrRegisterWrites(const DsiSleepOrRegisterWrite *reg_writes, size_t num_writes) {
for (size_t i = 0; i < num_writes; i++) {
if (reg_writes[i].kind == DsiSleepOrRegisterWriteKind_Write) {
*(reinterpret_cast<volatile u32 *>(g_dsi_regs + sizeof(u32) * reg_writes[i].offset)) = reg_writes[i].value;
} else if (reg_writes[i].kind == DsiSleepOrRegisterWriteKind_Sleep) {
svcSleepThread(1'000'000ul * reg_writes[i].offset);
} else {
std::abort();
}
}
}
#define DO_REGISTER_WRITES(base_address, writes) DoRegisterWrites(base_address, writes, sizeof(writes) / sizeof(writes[0]))
#define DO_SOC_DEPENDENT_REGISTER_WRITES(base_address, writes) DoSocDependentRegisterWrites(base_address, writes##Erista, sizeof(writes##Erista) / sizeof(writes##Erista[0]), writes##Mariko, sizeof(writes##Mariko) / sizeof(writes##Mariko[0]))
#define DO_DSI_SLEEP_OR_REGISTER_WRITES(writes) DoDsiSleepOrRegisterWrites(writes, sizeof(writes) / sizeof(writes[0]))
static void InitializeFrameBuffer() {
if (g_frame_buffer != nullptr) {
std::memset(g_frame_buffer, 0x00, FrameBufferSize);
armDCacheFlush(g_frame_buffer, FrameBufferSize);
} else {
const uintptr_t frame_buffer_aligned = ((reinterpret_cast<uintptr_t>(g_frame_buffer_storage) + DeviceAddressSpaceAlignMask) & ~uintptr_t(DeviceAddressSpaceAlignMask));
g_frame_buffer = reinterpret_cast<u32 *>(frame_buffer_aligned);
for (size_t i = 0; i < FrameBufferSize / sizeof(u32); i++) {
g_frame_buffer[i] = 0xFF0000FF;
}
//std::memset(g_frame_buffer, 0xCC, FrameBufferSize);
armDCacheFlush(g_frame_buffer, FrameBufferSize);
constexpr u64 DeviceName_DC = 2;
/* Create Address Space. */
if (R_FAILED(svcCreateDeviceAddressSpace(&g_dc_das_hnd, 0, (1ul << 32)))) {
std::abort();
}
/* Attach it to the DC. */
if (R_FAILED(svcAttachDeviceAddressSpace(DeviceName_DC, g_dc_das_hnd))) {
std::abort();
}
/* Map the framebuffer for the DC as read-only. */
if (R_FAILED(svcMapDeviceAddressSpaceAligned(g_dc_das_hnd, CUR_PROCESS_HANDLE, frame_buffer_aligned, FrameBufferSize, FrameBufferPaddr, 1))) {
std::abort();
}
}
}
static void FinalizeFrameBuffer() {
if (g_frame_buffer != nullptr) {
const uintptr_t frame_buffer_aligned = reinterpret_cast<uintptr_t>(g_frame_buffer);
constexpr u64 DeviceName_DC = 2;
/* Unmap the framebuffer from the DC. */
if (R_FAILED(svcUnmapDeviceAddressSpace(g_dc_das_hnd, CUR_PROCESS_HANDLE, frame_buffer_aligned, FrameBufferSize, FrameBufferPaddr))) {
std::abort();
}
/* Detach address space from the DC. */
if (R_FAILED(svcDetachDeviceAddressSpace(DeviceName_DC, g_dc_das_hnd))) {
std::abort();
}
/* Close the address space. */
if (R_FAILED(svcCloseHandle(g_dc_das_hnd))) {
std::abort();
}
g_dc_das_hnd = INVALID_HANDLE;
g_frame_buffer = nullptr;
}
}
static void WaitDsiTrigger() {
TimeoutHelper timeout_helper(250'000'000ul);
while (true) {
if (timeout_helper.TimedOut()) {
break;
}
if (ReadRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER) == 0) {
break;
}
}
svcSleepThread(5'000ul);
}
static void WaitDsiHostControl() {
TimeoutHelper timeout_helper(150'000'000ul);
while (true) {
if (timeout_helper.TimedOut()) {
break;
}
if ((ReadRegister(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL) & DSI_HOST_CONTROL_IMM_BTA) == 0) {
break;
}
}
}
void Boot::InitializeDisplay() {
/* Setup globals. */
InitializeRegisterBaseAddresses();
g_is_mariko = Boot::IsMariko();
InitializeFrameBuffer();
/* Turn on DSI/voltage rail. */
{
I2cSessionImpl i2c_session;
I2cDriver::Initialize();
I2cDriver::OpenSession(&i2c_session, I2cDevice_Max77620Pmic);
if (g_is_mariko) {
Boot::WriteI2cRegister(i2c_session, 0x18, 0x3A);
Boot::WriteI2cRegister(i2c_session, 0x1F, 0x71);
}
Boot::WriteI2cRegister(i2c_session, 0x23, 0xD0);
I2cDriver::Finalize();
}
/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_CLR, 0x1010000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_SET, 0x1010000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_CLR, 0x18000000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_SET, 0x18000000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_X_SET, 0x20000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL, 0xA);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_W_SET, 0x80000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP, 0xA);
/* DPD idle. */
WritePmcRegister(PmcBase + APBDEV_PMC_IO_DPD_REQ, 0x40000000);
WritePmcRegister(PmcBase + APBDEV_PMC_IO_DPD2_REQ, 0x40000000);
/* Configure LCD pinmux tristate + passthrough. */
ClearRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_NFC_EN, ~PINMUX_TRISTATE);
ClearRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_NFC_INT, ~PINMUX_TRISTATE);
ClearRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, ~PINMUX_TRISTATE);
ClearRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_EN, ~PINMUX_TRISTATE);
ClearRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_RST, ~PINMUX_TRISTATE);
/* Configure LCD power, VDD. */
SetRegisterBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3);
SetRegisterBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3);
SetRegisterBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
svcSleepThread(10'000'000ul);
SetRegisterBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
svcSleepThread(10'000'000ul);
/* Configure LCD backlight. */
SetRegisterBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x7);
SetRegisterBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x7);
SetRegisterBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2);
/* Configure display interface and display. */
WriteRegister(g_mipi_cal_regs + 0x060, 0);
if (g_is_mariko) {
WriteRegister(g_mipi_cal_regs + 0x058, 0);
WriteRegister(g_apb_misc_regs + 0xAC0, 0);
}
/* Execute configs. */
DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01);
DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init01);
/* NOTE: Nintendo bug here. */
/* As of 8.0.0, Nintendo writes this list to CAR instead of DSI */
/* This results in them zeroing CLK_SOURCE_UARTA... */
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init02);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init03);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init04);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init05);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init06);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init07);
svcSleepThread(10'000'000ul);
/* Enable backlight reset. */
SetRegisterBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
svcSleepThread(60'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x337);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
WaitDsiTrigger();
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x406);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
WaitDsiTrigger();
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
WaitDsiHostControl();
svcSleepThread(5'000'000ul);
/* Parse LCD vendor. */
{
u32 host_response[3];
for (size_t i = 0; i < sizeof(host_response) / sizeof(host_response[0]); i++) {
host_response[i] = ReadRegister(g_dsi_regs + sizeof(u32) * DSI_RD_DATA);
}
if ((host_response[2] & 0xFF) == 0x10) {
g_lcd_vendor = 0;
} else {
g_lcd_vendor = (host_response[2] >> 8) & 0xFF00;
}
g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF);
}
/* LCD vendor specific configuration. */
switch (g_lcd_vendor) {
case 0xF30: /* TODO: What's this? */
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(180'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
break;
case 0xF20: /* TODO: What's this? */
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(180'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
break;
case 0x10: /* Japan Display Inc screens. */
DO_DSI_SLEEP_OR_REGISTER_WRITES(DisplayConfigJdiSpecificInit01);
break;
default:
if ((g_lcd_vendor | 0x10) == 0x1030) {
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(120'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
}
break;
}
svcSleepThread(20'000'000ul);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld02);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init08);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init09);
WriteRegister(g_disp1_regs + sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, SHIFT_CLK_DIVIDER(4));
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init10);
svcSleepThread(10'000'000ul);
/* Configure MIPI CAL. */
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal01);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
if (g_is_mariko) {
/* On Mariko the above configurations are executed twice, for some reason. */
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
}
svcSleepThread(10'000'000ul);
/* Write DISP1, FrameBuffer config. */
DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc02);
DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigFrameBuffer);
svcSleepThread(35'000'000ul);
g_is_display_intialized = true;
}
void Boot::ShowDisplay(size_t x, size_t y, size_t width, size_t height, const u32 *img) {
if (!g_is_display_intialized) {
return;
}
/* Draw the image to the screen. */
std::memset(g_frame_buffer, 0, FrameBufferSize);
{
for (size_t cur_y = 0; cur_y < height; cur_y++) {
for (size_t cur_x = 0; cur_x < width; cur_x++) {
g_frame_buffer[(FrameBufferHeight - (x + cur_x)) * FrameBufferWidth + y + cur_y] = img[cur_y * width + cur_x];
}
}
}
armDCacheFlush(g_frame_buffer, FrameBufferSize);
/* Enable backlight. */
SetRegisterBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
}
void Boot::FinalizeDisplay() {
if (!g_is_display_intialized) {
return;
}
/* Disable backlight. */
ClearRegisterBits(g_gpio_regs + GPIO_PORT6_OUT_1, ~0x1);
WriteRegister(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 1);
WriteRegister(g_disp1_regs + sizeof(u32) * DSI_WR_DATA, 0x2805);
/* Nintendo waits 5 frames before continuing. */
{
const uintptr_t host1x_vaddr = QueryVirtualAddress(0x500030a4, 4);
const u32 start_val = ReadRegister(host1x_vaddr);
while (ReadRegister(host1x_vaddr) < start_val + 5) {
/* spinlock here. */
}
}
WriteRegister(g_disp1_regs + sizeof(u32) * DC_CMD_STATE_ACCESS, (READ_MUX | WRITE_MUX));
WriteRegister(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 0);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini01);
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini02);
svcSleepThread(10'000'000ul);
/* Vendor specific shutdown. */
switch (g_lcd_vendor) {
case 0x10: /* Japan Display Inc screens. */
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificFini01);
break;
case 0xF30: /* TODO: What's this? */
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigF30SpecificFini01);
svcSleepThread(5'000'000ul);
break;
case 0x1020: /* TODO: What's this? */
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x115631);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
break;
case 0x1030: /* TODO: What's this? */
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x114D31);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(5'000'000ul);
break;
default:
break;
}
svcSleepThread(5'000'000ul);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1005);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
svcSleepThread(50'000'000ul);
/* Disable backlight RST/Voltage. */
ClearRegisterBits(g_gpio_regs + GPIO_PORT6_OUT_1, ~0x4);
svcSleepThread(10'000'000ul);
ClearRegisterBits(g_gpio_regs + GPIO_PORT3_OUT_0, ~0x2);
svcSleepThread(10'000'000ul);
ClearRegisterBits(g_gpio_regs + GPIO_PORT3_OUT_0, ~0x1);
svcSleepThread(10'000'000ul);
/* Cut clock to DSI. */
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_SET, 0x1010000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, 0x1010000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_SET, 0x18000000);
WriteRegister(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, 0x18000000);
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_PAD_CONTROL_0, (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)));
WriteRegister(g_dsi_regs + sizeof(u32) * DSI_POWER_CONTROL, 0);
/* Final LCD config for PWM */
ClearRegisterBits(g_gpio_regs + GPIO_PORT6_CNF_1, ~0x1);
SetRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, PINMUX_TRISTATE);
ReadWriteRegisterBits(g_apb_misc_regs + 0x3000 + PINMUX_AUX_LCD_BL_PWM, 1, 0x3);
/* Unmap framebuffer from DC virtual address space. */
FinalizeFrameBuffer();
g_is_display_intialized = false;
}

676
stratosphere/boot/source/boot_display_config.hpp Normal file
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@ -0,0 +1,676 @@
/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
#include "boot_registers_clkrst.hpp"
#include "boot_registers_di.hpp"
#include "boot_registers_gpio.hpp"
#include "boot_registers_pinmux.hpp"
#include "boot_registers_pmc.hpp"
struct RegisterWrite {
u32 offset;
u32 value;
};
enum DsiSleepOrRegisterWriteKind : u16 {
DsiSleepOrRegisterWriteKind_Write = 0,
DsiSleepOrRegisterWriteKind_Sleep = 1,
};
struct DsiSleepOrRegisterWrite {
DsiSleepOrRegisterWriteKind kind;
u16 offset;
u32 value;
};
static constexpr RegisterWrite DisplayConfigPlld01Erista[] = {
{CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA},
};
static constexpr RegisterWrite DisplayConfigPlld01Mariko[] = {
{CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00},
};
static constexpr RegisterWrite DisplayConfigDc01[] = {
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(u32) * DC_CMD_REG_ACT_CONTROL, 0x54},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_DISP_DC_MCCIF_FIFOCTRL, 0},
{sizeof(u32) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
{sizeof(u32) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
{sizeof(u32) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
{sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
{sizeof(u32) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{sizeof(u32) * 0x4E4, 0},
{sizeof(u32) * DC_COM_CRC_CONTROL, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
};
static constexpr RegisterWrite DisplayConfigDsi01Init01[] = {
{sizeof(u32) * DSI_WR_DATA, 0x0},
{sizeof(u32) * DSI_INT_ENABLE, 0x0},
{sizeof(u32) * DSI_INT_STATUS, 0x0},
{sizeof(u32) * DSI_INT_MASK, 0x0},
{sizeof(u32) * DSI_INIT_SEQ_DATA_0, 0x0},
{sizeof(u32) * DSI_INIT_SEQ_DATA_1, 0x0},
{sizeof(u32) * DSI_INIT_SEQ_DATA_2, 0x0},
{sizeof(u32) * DSI_INIT_SEQ_DATA_3, 0x0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init02Erista[] = {
{sizeof(u32) * DSI_INIT_SEQ_DATA_15, 0x0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init02Mariko[] = {
{sizeof(u32) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init03[] = {
{sizeof(u32) * DSI_DCS_CMDS, 0},
{sizeof(u32) * DSI_PKT_SEQ_0_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_1_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_2_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_3_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_4_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_5_LO, 0},
{sizeof(u32) * DSI_PKT_SEQ_0_HI, 0},
{sizeof(u32) * DSI_PKT_SEQ_1_HI, 0},
{sizeof(u32) * DSI_PKT_SEQ_2_HI, 0},
{sizeof(u32) * DSI_PKT_SEQ_3_HI, 0},
{sizeof(u32) * DSI_PKT_SEQ_4_HI, 0},
{sizeof(u32) * DSI_PKT_SEQ_5_HI, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init04Erista[] = {
/* No register writes. */
};
static constexpr RegisterWrite DisplayConfigDsi01Init04Mariko[] = {
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
{sizeof(u32) * DSI_PAD_CONTROL_2, 0},
{sizeof(u32) * DSI_PAD_CONTROL_3, 0},
{sizeof(u32) * DSI_PAD_CONTROL_4, 0},
{sizeof(u32) * DSI_PAD_CONTROL_5_MARIKO, 0},
{sizeof(u32) * DSI_PAD_CONTROL_6_MARIKO, 0},
{sizeof(u32) * DSI_PAD_CONTROL_7_MARIKO, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init05[] = {
{sizeof(u32) * DSI_PAD_CONTROL_CD, 0},
{sizeof(u32) * DSI_SOL_DELAY, 0x18},
{sizeof(u32) * DSI_MAX_THRESHOLD, 0x1E0},
{sizeof(u32) * DSI_TRIGGER, 0},
{sizeof(u32) * DSI_INIT_SEQ_CONTROL, 0},
{sizeof(u32) * DSI_PKT_LEN_0_1, 0},
{sizeof(u32) * DSI_PKT_LEN_2_3, 0},
{sizeof(u32) * DSI_PKT_LEN_4_5, 0},
{sizeof(u32) * DSI_PKT_LEN_6_7, 0},
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init06[] = {
{sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(u32) * DSI_PHY_TIMING_2, 0x30109},
{sizeof(u32) * DSI_BTA_TIMING, 0x190A14},
{sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(u32) * DSI_TO_TALLY, 0},
{sizeof(u32) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_POWER_CONTROL, 0},
{sizeof(u32) * DSI_POWER_CONTROL, 0},
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init07[] = {
{sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(u32) * DSI_PHY_TIMING_2, 0x30118},
{sizeof(u32) * DSI_BTA_TIMING, 0x190A14},
{sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(u32) * DSI_TO_TALLY, 0},
{sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(u32) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_MAX_THRESHOLD, 0x40},
{sizeof(u32) * DSI_TRIGGER, 0},
{sizeof(u32) * DSI_TX_CRC, 0},
{sizeof(u32) * DSI_INIT_SEQ_CONTROL, 0}
};
static constexpr RegisterWrite DisplayConfigDsiPhyTimingErista[] = {
{sizeof(u32) * DSI_PHY_TIMING_0, 0x6070601},
};
static constexpr RegisterWrite DisplayConfigDsiPhyTimingMariko[] = {
{sizeof(u32) * DSI_PHY_TIMING_0, 0x6070603},
};
static constexpr DsiSleepOrRegisterWrite DisplayConfigJdiSpecificInit01[] = {
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x9483FFB9},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1939},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAD8},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAAA},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAA},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1BD15},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2739},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2BD15},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xF39},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x6D915},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB9},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1105},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
{DsiSleepOrRegisterWriteKind_Sleep, 0xB4, 0},
{DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2905},
{DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static constexpr RegisterWrite DisplayConfigPlld02Erista[] = {
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA},
};
static constexpr RegisterWrite DisplayConfigPlld02Mariko[] = {
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00},
};
static constexpr RegisterWrite DisplayConfigDsi01Init08[] = {
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init09[] = {
{sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(u32) * DSI_PHY_TIMING_2, 0x30172},
{sizeof(u32) * DSI_BTA_TIMING, 0x190A14},
{sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
{sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(u32) * DSI_TO_TALLY, 0},
{sizeof(u32) * DSI_PKT_SEQ_0_LO, 0x40000208},
{sizeof(u32) * DSI_PKT_SEQ_2_LO, 0x40000308},
{sizeof(u32) * DSI_PKT_SEQ_4_LO, 0x40000308},
{sizeof(u32) * DSI_PKT_SEQ_1_LO, 0x40000308},
{sizeof(u32) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
{sizeof(u32) * DSI_PKT_SEQ_3_HI, 0x2CC},
{sizeof(u32) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
{sizeof(u32) * DSI_PKT_SEQ_5_HI, 0x2CC},
{sizeof(u32) * DSI_PKT_LEN_0_1, 0xCE0000},
{sizeof(u32) * DSI_PKT_LEN_2_3, 0x87001A2},
{sizeof(u32) * DSI_PKT_LEN_4_5, 0x190},
{sizeof(u32) * DSI_PKT_LEN_6_7, 0x190},
{sizeof(u32) * DSI_HOST_CONTROL, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Init10[] = {
{sizeof(u32) * DSI_TRIGGER, 0},
{sizeof(u32) * DSI_CONTROL, 0},
{sizeof(u32) * DSI_SOL_DELAY, 6},
{sizeof(u32) * DSI_MAX_THRESHOLD, 0x1E0},
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(u32) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
};
static constexpr RegisterWrite DisplayConfigDsi01Init11Erista[] = {
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
{sizeof(u32) * DSI_PAD_CONTROL_2, 0},
{sizeof(u32) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
{sizeof(u32) * DSI_PAD_CONTROL_4, 0}
};
static constexpr RegisterWrite DisplayConfigDsi01Init11Mariko[] = {
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
{sizeof(u32) * DSI_PAD_CONTROL_2, 0},
{sizeof(u32) * DSI_PAD_CONTROL_3, 0},
{sizeof(u32) * DSI_PAD_CONTROL_4, 0x77777},
{sizeof(u32) * DSI_PAD_CONTROL_5_MARIKO, 0x77777},
{sizeof(u32) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)},
{sizeof(u32) * DSI_PAD_CONTROL_7_MARIKO, 0},
};
static constexpr RegisterWrite DisplayConfigMipiCal01[] = {
{0x60, 0},
{0x08, 0xF3F10000},
{0x58, 1},
{0x60, 0},
};
static constexpr RegisterWrite DisplayConfigMipiCal02Erista[] = {
{0x60, 0x10010},
{0x5C, 0x300},
};
static constexpr RegisterWrite DisplayConfigMipiCal02Mariko[] = {
{0x60, 0x10010},
{0x5C, 0},
};
static constexpr RegisterWrite DisplayConfigMipiCal03Erista[] = {
{0x38, 0x200200},
{0x3C, 0x200200},
{0x64, 0x200002},
{0x68, 0x200002},
{0x14, 0},
{0x14, 0},
};
static constexpr RegisterWrite DisplayConfigMipiCal03Mariko[] = {
{0x38, 0x200006},
{0x3C, 0x200006},
{0x64, 0x260000},
{0x68, 0x260000},
{0x14, 0x200000},
{0x14, 0x200000},
};
static constexpr RegisterWrite DisplayConfigMipiCal04[] = {
{0x1C, 0},
{0x20, 0},
{0x24, 0},
{0x28, 0},
{0x40, 0},
{0x44, 0},
{0x68, 0},
{0x70, 0},
{0x74, 0},
{0x00, 0x2A000001},
};
static constexpr RegisterWrite DisplayConfigDc02[] = {
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_DV_CONTROL, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
/* Setup default YUV colorspace conversion coefficients */
{sizeof(u32) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(u32) * DC_WIN_CSC_KUR, 0},
{sizeof(u32) * DC_WIN_CSC_KVR, 0x198},
{sizeof(u32) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(u32) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(u32) * DC_WIN_CSC_KUB, 0x204},
{sizeof(u32) * DC_WIN_CSC_KVB, 0},
/* End of color coefficients */
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{sizeof(u32) * 0x4E4, 0},
{sizeof(u32) * DC_COM_CRC_CONTROL, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * 0x716, 0x10000FF},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
/* Set Display timings */
{sizeof(u32) * DC_DISP_DISP_TIMING_OPTIONS, 0},
{sizeof(u32) * DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
{sizeof(u32) * DC_DISP_SYNC_WIDTH, 0x10048},
{sizeof(u32) * DC_DISP_BACK_PORCH, 0x90048},
{sizeof(u32) * DC_DISP_ACTIVE, 0x50002D0},
{sizeof(u32) * DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd.
/* End of Display timings */
{sizeof(u32) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
{sizeof(u32) * DC_COM_PIN_OUTPUT_ENABLE(1), 0},
{sizeof(u32) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
{sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, 0},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(u32) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
{sizeof(u32) * DC_DISP_FRONT_PORCH, 0xA0088},
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(u32) * DC_CMD_STATE_ACCESS, 0},
{sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
{sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
};
static constexpr u32 DisplayConfigFrameBufferAddress = 0xC0000000;
static constexpr RegisterWrite DisplayConfigFrameBuffer[] = {
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{sizeof(u32) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_WIN_POSITION, 0}, //(0,0)
{sizeof(u32) * DC_WIN_H_INITIAL_DDA, 0},
{sizeof(u32) * DC_WIN_V_INITIAL_DDA, 0},
{sizeof(u32) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
{sizeof(u32) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
{sizeof(u32) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
{sizeof(u32) * DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
{sizeof(u32) * DC_WIN_BUFFER_CONTROL, 0},
{sizeof(u32) * DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
{sizeof(u32) * DC_WINBUF_START_ADDR, DisplayConfigFrameBufferAddress}, //Framebuffer address.
{sizeof(u32) * DC_WINBUF_ADDR_H_OFFSET, 0},
{sizeof(u32) * DC_WINBUF_ADDR_V_OFFSET, 0},
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{sizeof(u32) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
{sizeof(u32) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD.
{sizeof(u32) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
{sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
};
static constexpr RegisterWrite DisplayConfigDsi01Fini01[] = {
{sizeof(u32) * DSI_POWER_CONTROL, 0},
{sizeof(u32) * DSI_PAD_CONTROL_1, 0},
};
static constexpr RegisterWrite DisplayConfigDsi01Fini02[] = {
{sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(u32) * DSI_PHY_TIMING_2, 0x30109},
{sizeof(u32) * DSI_BTA_TIMING, 0x190A14},
{sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
{sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(u32) * DSI_TO_TALLY, 0},
{sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(u32) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(u32) * DSI_MAX_THRESHOLD, 0x40},
{sizeof(u32) * DSI_TRIGGER, 0},
{sizeof(u32) * DSI_TX_CRC, 0},
{sizeof(u32) * DSI_INIT_SEQ_CONTROL, 0}
};
static constexpr RegisterWrite DisplayConfigJdiSpecificFini01[] = {
{sizeof(u32) * DSI_WR_DATA, 0x439},
{sizeof(u32) * DSI_WR_DATA, 0x9483FFB9},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0x2139},
{sizeof(u32) * DSI_WR_DATA, 0x191919D5},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0xB39},
{sizeof(u32) * DSI_WR_DATA, 0x4F0F41B1},
{sizeof(u32) * DSI_WR_DATA, 0xF179A433},
{sizeof(u32) * DSI_WR_DATA, 0x2D81},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0x439},
{sizeof(u32) * DSI_WR_DATA, 0xB9},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static constexpr RegisterWrite DisplayConfigF30SpecificFini01[] = {
{sizeof(u32) * DSI_WR_DATA, 0x439},
{sizeof(u32) * DSI_WR_DATA, 0x9483FFB9},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0x2C39},
{sizeof(u32) * DSI_WR_DATA, 0x191919D5},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0x2C39},
{sizeof(u32) * DSI_WR_DATA, 0x191919D6},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_WR_DATA, 0x19191919},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0xB39},
{sizeof(u32) * DSI_WR_DATA, 0x711148B1},
{sizeof(u32) * DSI_WR_DATA, 0x71143209},
{sizeof(u32) * DSI_WR_DATA, 0x114D31},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
{sizeof(u32) * DSI_WR_DATA, 0x439},
{sizeof(u32) * DSI_WR_DATA, 0xB9},
{sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST},
};

8
stratosphere/boot/source/boot_functions.hpp
View File

@ -30,6 +30,7 @@ class Boot {
static void SetInitialGpioConfiguration();
static void CheckClock();
static void DetectBootReason();
static void ShowSplashScreen();
/* Power utilities. */
static void RebootSystem();
@ -48,8 +49,15 @@ class Boot {
static HardwareType GetHardwareType();
static u32 GetBootReason();
static bool IsRecoveryBoot();
static bool IsMariko();
/* I2C Utilities. */
static Result ReadI2cRegister(I2cSessionImpl &session, u8 *dst, size_t dst_size, const u8 *cmd, size_t cmd_size);
static Result WriteI2cRegister(I2cSessionImpl &session, const u8 *src, size_t src_size, const u8 *cmd, size_t cmd_size);
static Result WriteI2cRegister(I2cSessionImpl &session, const u8 address, const u8 value);
/* Splash Screen/Display utilities. */
static void InitializeDisplay();
static void ShowDisplay(size_t x, size_t y, size_t width, size_t height, const u32 *img);
static void FinalizeDisplay();
};

4
stratosphere/boot/source/boot_i2c_utils.cpp
View File

@ -69,3 +69,7 @@ Result Boot::WriteI2cRegister(I2cSessionImpl &session, const u8 *src, size_t src
return RetryUntilSuccess([&]() { return I2cDriver::Send(session, cmd_list, src_size + cmd_size, static_cast<I2cTransactionOption>(I2cTransactionOption_Start | I2cTransactionOption_Stop)); });
}
Result Boot::WriteI2cRegister(I2cSessionImpl &session, const u8 address, const u8 value) {
return Boot::WriteI2cRegister(session, &value, sizeof(value), &address, sizeof(address));
}

3
stratosphere/boot/source/boot_main.cpp
View File

@ -122,7 +122,8 @@ int main(int argc, char **argv)
/* Talk to PMIC/RTC, set boot reason with SPL. */
Boot::DetectBootReason();
/* TODO: ShowSplashScreen(); */
/* Display splash screen for two seconds. */
Boot::ShowSplashScreen();
/* TODO: ConfigurePinmux(); */

119
stratosphere/boot/source/boot_registers_clkrst.hpp Normal file
View File

@ -0,0 +1,119 @@
/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
static constexpr size_t CLK_RST_CONTROLLER_RST_SOURCE = 0x0;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_L = 0x4;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_H = 0x8;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_U = 0xC;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_L = 0x10;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_H = 0x14;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_U = 0x18;
static constexpr size_t CLK_RST_CONTROLLER_CCLK_BURST_POLICY = 0x20;
static constexpr size_t CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER = 0x24;
static constexpr size_t CLK_RST_CONTROLLER_SCLK_BURST_POLICY = 0x28;
static constexpr size_t CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER = 0x2C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SYSTEM_RATE = 0x30;
static constexpr size_t CLK_RST_CONTROLLER_MISC_CLK_ENB = 0x48;
static constexpr size_t CLK_RST_CONTROLLER_OSC_CTRL = 0x50;
static constexpr size_t CLK_RST_CONTROLLER_PLLC_BASE = 0x80;
static constexpr size_t CLK_RST_CONTROLLER_PLLC_MISC = 0x88;
static constexpr size_t CLK_RST_CONTROLLER_PLLM_BASE = 0x90;
static constexpr size_t CLK_RST_CONTROLLER_PLLM_MISC1 = 0x98;
static constexpr size_t CLK_RST_CONTROLLER_PLLM_MISC2 = 0x9C;
static constexpr size_t CLK_RST_CONTROLLER_PLLP_BASE = 0xA0;
static constexpr size_t CLK_RST_CONTROLLER_PLLD_BASE = 0xD0;
static constexpr size_t CLK_RST_CONTROLLER_PLLD_MISC1 = 0xD8;
static constexpr size_t CLK_RST_CONTROLLER_PLLD_MISC = 0xDC;
static constexpr size_t CLK_RST_CONTROLLER_PLLX_BASE = 0xE0;
static constexpr size_t CLK_RST_CONTROLLER_PLLX_MISC = 0xE4;
static constexpr size_t CLK_RST_CONTROLLER_PLLE_BASE = 0xE8;
static constexpr size_t CLK_RST_CONTROLLER_PLLE_MISC = 0xEC;
static constexpr size_t CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA = 0xF8;
static constexpr size_t CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB = 0xFC;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_PWM = 0x110;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 = 0x124;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 = 0x128;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 = 0x138;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_VI = 0x148;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 = 0x150;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 = 0x154;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 = 0x164;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_UARTA = 0x178;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_UARTB = 0x17C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X = 0x180;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_UARTC = 0x1A0;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 = 0x1B8;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 = 0x1BC;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_CSITE = 0x1D4;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_EMC = 0x19C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_TSEC = 0x1F4;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_X = 0x280;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_X_SET = 0x284;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_X_CLR = 0x288;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_X = 0x28C;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_X_SET = 0x290;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_X_CLR = 0x294;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_Y = 0x298;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_Y_SET = 0x29C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_Y_CLR = 0x2A0;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_Y = 0x2A4;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_Y_SET = 0x2A8;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_Y_CLR = 0x2AC;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_L_SET = 0x300;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_L_CLR = 0x304;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_H_SET = 0x308;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_H_CLR = 0x30C;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_U_SET = 0x310;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEV_U_CLR = 0x314;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_L_SET = 0x320;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_L_CLR = 0x324;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_H_SET = 0x328;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_H_CLR = 0x32C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_U_SET = 0x330;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_U_CLR = 0x334;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_V = 0x358;
static constexpr size_t CLK_RST_CONTROLLER_RST_DEVICES_W = 0x35C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_V = 0x360;
static constexpr size_t CLK_RST_CONTROLLER_CLK_OUT_ENB_W = 0x364;
static constexpr size_t CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 = 0x388;
static constexpr size_t CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC = 0x3A0;
static constexpr size_t CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD = 0x3A4;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT = 0x3B4;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 = 0x410;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SE = 0x42C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_V_SET = 0x440;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_W_SET = 0x448;
static constexpr size_t CLK_RST_CONTROLLER_CLK_ENB_W_CLR = 0x44C;
static constexpr size_t CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET = 0x450;
static constexpr size_t CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR = 0x454;
static constexpr size_t CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 = 0x488;
static constexpr size_t CLK_RST_CONTROLLER_PLLE_AUX = 0x48C;
static constexpr size_t CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 = 0x4A0;
static constexpr size_t CLK_RST_CONTROLLER_PLLX_MISC_3 = 0x518;
static constexpr size_t CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE = 0x554;
static constexpr size_t CLK_RST_CONTROLLER_SPARE_REG0 = 0x55C;
static constexpr size_t CLK_RST_CONTROLLER_PLLMB_BASE = 0x5E8;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP = 0x620;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL = 0x664;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL = 0x66C;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM = 0x694;
static constexpr size_t CLK_RST_CONTROLLER_CLK_SOURCE_NVENC = 0x6A0;
static constexpr size_t CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER = 0x704;

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/*
* Copyright (c) 2018 naehrwert
* Copyright (C) 2018 CTCaer
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
#define SYNCPT_CNTRL_NO_STALL (1 << 8)
#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
#define SYNCPT_VSYNC_ENABLE (1 << 8)
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
#define DC_CMD_DISPLAY_COMMAND 0x32
#define DISP_CTRL_MODE_STOP (0 << 5)
#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
#define DISP_CTRL_MODE_MASK (3 << 5)
#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
#define PW0_ENABLE (1 << 0)
#define PW1_ENABLE (1 << 2)
#define PW2_ENABLE (1 << 4)
#define PW3_ENABLE (1 << 6)
#define PW4_ENABLE (1 << 8)
#define PM0_ENABLE (1 << 16)
#define PM1_ENABLE (1 << 18)
#define DC_CMD_INT_MASK 0x38
#define DC_CMD_INT_ENABLE 0x39
#define DC_CMD_STATE_ACCESS 0x40
#define READ_MUX (1 << 0)
#define WRITE_MUX (1 << 2)
#define DC_CMD_STATE_CONTROL 0x41
#define GENERAL_ACT_REQ (1 << 0)
#define WIN_A_ACT_REQ (1 << 1)
#define WIN_B_ACT_REQ (1 << 2)
#define WIN_C_ACT_REQ (1 << 3)
#define CURSOR_ACT_REQ (1 << 7)
#define GENERAL_UPDATE (1 << 8)
#define WIN_A_UPDATE (1 << 9)
#define WIN_B_UPDATE (1 << 10)
#define WIN_C_UPDATE (1 << 11)
#define CURSOR_UPDATE (1 << 15)
#define NC_HOST_TRIG (1 << 24)
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
#define WINDOW_A_SELECT (1 << 4)
#define WINDOW_B_SELECT (1 << 5)
#define WINDOW_C_SELECT (1 << 6)
#define DC_CMD_REG_ACT_CONTROL 0x043
#define DC_COM_CRC_CONTROL 0x300
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
#define DC_COM_DSC_TOP_CTL 0x33E
#define DC_DISP_DISP_WIN_OPTIONS 0x402
#define HDMI_ENABLE (1 << 30)
#define DSI_ENABLE (1 << 29)
#define SOR1_TIMING_CYA (1 << 27)
#define SOR1_ENABLE (1 << 26)
#define SOR_ENABLE (1 << 25)
#define CURSOR_ENABLE (1 << 16)
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
#define DC_DISP_REF_TO_SYNC 0x406
#define DC_DISP_SYNC_WIDTH 0x407
#define DC_DISP_BACK_PORCH 0x408
#define DC_DISP_ACTIVE 0x409
#define DC_DISP_FRONT_PORCH 0x40A
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
#define DISP_DATA_FORMAT_DF2S (4 << 0)
#define DISP_DATA_FORMAT_DF3S (5 << 0)
#define DISP_DATA_FORMAT_DFSPI (6 << 0)
#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
#define DISP_ALIGNMENT_MSB (0 << 8)
#define DISP_ALIGNMENT_LSB (1 << 8)
#define DISP_ORDER_RED_BLUE (0 << 9)
#define DISP_ORDER_BLUE_RED (1 << 9)
#define DC_DISP_DISP_COLOR_CONTROL 0x430
#define DITHER_CONTROL_MASK (3 << 8)
#define DITHER_CONTROL_DISABLE (0 << 8)
#define DITHER_CONTROL_ORDERED (2 << 8)
#define DITHER_CONTROL_ERRDIFF (3 << 8)
#define BASE_COLOR_SIZE_MASK (0xf << 0)
#define BASE_COLOR_SIZE_666 (0 << 0)
#define BASE_COLOR_SIZE_111 (1 << 0)
#define BASE_COLOR_SIZE_222 (2 << 0)
#define BASE_COLOR_SIZE_333 (3 << 0)
#define BASE_COLOR_SIZE_444 (4 << 0)
#define BASE_COLOR_SIZE_555 (5 << 0)
#define BASE_COLOR_SIZE_565 (6 << 0)
#define BASE_COLOR_SIZE_332 (7 << 0)
#define BASE_COLOR_SIZE_888 (8 << 0)
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
#define SC1_H_QUALIFIER_NONE (1 << 16)
#define SC0_H_QUALIFIER_NONE (1 << 0)
#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
#define DE_SELECT_ACTIVE_BLANK (0 << 0)
#define DE_SELECT_ACTIVE (1 << 0)
#define DE_SELECT_ACTIVE_IS (2 << 0)
#define DE_CONTROL_ONECLK (0 << 2)
#define DE_CONTROL_NORMAL (1 << 2)
#define DE_CONTROL_EARLY_EXT (2 << 2)
#define DE_CONTROL_EARLY (3 << 2)
#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
#define DC_DISP_SD_BL_PARAMETERS 0x4D7
#define DC_DISP_SD_BL_CONTROL 0x4DC
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
#define DC_WIN_CSC_YOF 0x611
#define DC_WIN_CSC_KYRGB 0x612
#define DC_WIN_CSC_KUR 0x613
#define DC_WIN_CSC_KVR 0x614
#define DC_WIN_CSC_KUG 0x615
#define DC_WIN_CSC_KVG 0x616
#define DC_WIN_CSC_KUB 0x617
#define DC_WIN_CSC_KVB 0x618
#define DC_WIN_AD_WIN_OPTIONS 0xB80
#define DC_WIN_BD_WIN_OPTIONS 0xD80
#define DC_WIN_CD_WIN_OPTIONS 0xF80
// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
#define DC_WIN_WIN_OPTIONS 0x700
#define H_DIRECTION (1 << 0)
#define V_DIRECTION (1 << 2)
#define SCAN_COLUMN (1 << 4)
#define COLOR_EXPAND (1 << 6)
#define CSC_ENABLE (1 << 18)
#define WIN_ENABLE (1 << 30)
#define DC_WIN_COLOR_DEPTH 0x703
#define WIN_COLOR_DEPTH_P1 0x0
#define WIN_COLOR_DEPTH_P2 0x1
#define WIN_COLOR_DEPTH_P4 0x2
#define WIN_COLOR_DEPTH_P8 0x3
#define WIN_COLOR_DEPTH_B4G4R4A4 0x4
#define WIN_COLOR_DEPTH_B5G5R5A 0x5
#define WIN_COLOR_DEPTH_B5G6R5 0x6
#define WIN_COLOR_DEPTH_AB5G5R5 0x7
#define WIN_COLOR_DEPTH_B8G8R8A8 0xC
#define WIN_COLOR_DEPTH_R8G8B8A8 0xD
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
#define WIN_COLOR_DEPTH_YCbCr422 0x10
#define WIN_COLOR_DEPTH_YUV422 0x11
#define WIN_COLOR_DEPTH_YCbCr420P 0x12
#define WIN_COLOR_DEPTH_YUV420P 0x13
#define WIN_COLOR_DEPTH_YCbCr422P 0x14
#define WIN_COLOR_DEPTH_YUV422P 0x15
#define WIN_COLOR_DEPTH_YCbCr422R 0x16
#define WIN_COLOR_DEPTH_YUV422R 0x17
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
#define WIN_COLOR_DEPTH_YUV422RA 0x19
#define DC_WIN_BUFFER_CONTROL 0x702
#define DC_WIN_POSITION 0x704
#define DC_WIN_SIZE 0x705
#define H_SIZE(x) (((x) & 0x1fff) << 0)
#define V_SIZE(x) (((x) & 0x1fff) << 16)
#define DC_WIN_PRESCALED_SIZE 0x706
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
#define DC_WIN_H_INITIAL_DDA 0x707
#define DC_WIN_V_INITIAL_DDA 0x708
#define DC_WIN_DDA_INC 0x709
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
#define DC_WIN_LINE_STRIDE 0x70A
#define LINE_STRIDE(x) (x)
#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
#define DC_WIN_DV_CONTROL 0x70E
// The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER).
#define DC_WINBUF_START_ADDR 0x800
#define DC_WINBUF_ADDR_H_OFFSET 0x806
#define DC_WINBUF_ADDR_V_OFFSET 0x808
#define DC_WINBUF_SURFACE_KIND 0x80B
#define PITCH (0 << 0)
#define TILED (1 << 0)
#define BLOCK (2 << 0)
#define BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
/*! Display serial interface registers. */
#define _DSIREG(reg) ((reg) * 4)
#define DSI_RD_DATA 0x9
#define DSI_WR_DATA 0xA
#define DSI_POWER_CONTROL 0xB
#define DSI_POWER_CONTROL_ENABLE 1
#define DSI_INT_ENABLE 0xC
#define DSI_INT_STATUS 0xD
#define DSI_INT_MASK 0xE
#define DSI_HOST_CONTROL 0xF
#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
#define DSI_HOST_CONTROL_RAW (1 << 6)
#define DSI_HOST_CONTROL_HS (1 << 5)
#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
#define DSI_HOST_CONTROL_CS (1 << 1)
#define DSI_HOST_CONTROL_ECC (1 << 0)
#define DSI_CONTROL 0x10
#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
#define DSI_CONTROL_DCS_ENABLE (1 << 3)
#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
#define DSI_CONTROL_HOST_ENABLE (1 << 0)
#define DSI_SOL_DELAY 0x11
#define DSI_MAX_THRESHOLD 0x12
#define DSI_TRIGGER 0x13
#define DSI_TRIGGER_HOST (1 << 1)
#define DSI_TRIGGER_VIDEO (1 << 0)
#define DSI_TX_CRC 0x14
#define DSI_STATUS 0x15
#define DSI_INIT_SEQ_CONTROL 0x1A
#define DSI_INIT_SEQ_DATA_0 0x1B
#define DSI_INIT_SEQ_DATA_1 0x1C
#define DSI_INIT_SEQ_DATA_2 0x1D
#define DSI_INIT_SEQ_DATA_3 0x1E
#define DSI_PKT_SEQ_0_LO 0x23
#define DSI_PKT_SEQ_0_HI 0x24
#define DSI_PKT_SEQ_1_LO 0x25
#define DSI_PKT_SEQ_1_HI 0x26
#define DSI_PKT_SEQ_2_LO 0x27
#define DSI_PKT_SEQ_2_HI 0x28
#define DSI_PKT_SEQ_3_LO 0x29
#define DSI_PKT_SEQ_3_HI 0x2A
#define DSI_PKT_SEQ_4_LO 0x2B
#define DSI_PKT_SEQ_4_HI 0x2C
#define DSI_PKT_SEQ_5_LO 0x2D
#define DSI_PKT_SEQ_5_HI 0x2E
#define DSI_DCS_CMDS 0x33
#define DSI_PKT_LEN_0_1 0x34
#define DSI_PKT_LEN_2_3 0x35
#define DSI_PKT_LEN_4_5 0x36
#define DSI_PKT_LEN_6_7 0x37
#define DSI_PHY_TIMING_0 0x3C
#define DSI_PHY_TIMING_1 0x3D
#define DSI_PHY_TIMING_2 0x3E
#define DSI_BTA_TIMING 0x3F
#define DSI_TIMEOUT_0 0x44
#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
#define DSI_TIMEOUT_1 0x45
#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
#define DSI_TO_TALLY 0x46
#define DSI_PAD_CONTROL_0 0x4B
#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
#define DSI_PAD_CONTROL_CD 0x4c
#define DSI_VIDEO_MODE_CONTROL 0x4E
#define DSI_PAD_CONTROL_1 0x4F
#define DSI_PAD_CONTROL_2 0x50
#define DSI_PAD_CONTROL_3 0x51
#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
#define DSI_PAD_CONTROL_4 0x52
#define DSI_PAD_CONTROL_5_MARIKO 0x53
#define DSI_PAD_CONTROL_6_MARIKO 0x54
#define DSI_PAD_CONTROL_7_MARIKO 0x55
#define DSI_INIT_SEQ_DATA_15 0x5F
#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62

28
stratosphere/boot/source/boot_registers_gpio.hpp Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
static constexpr size_t GPIO_PORT3_CNF_0 = 0x200;
static constexpr size_t GPIO_PORT3_OE_0 = 0x210;
static constexpr size_t GPIO_PORT3_OUT_0 = 0x220;
static constexpr size_t GPIO_PORT6_CNF_1 = 0x504;
static constexpr size_t GPIO_PORT6_OE_1 = 0x514;
static constexpr size_t GPIO_PORT6_OUT_1 = 0x524;

75
stratosphere/boot/source/boot_registers_pinmux.hpp Normal file
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/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
static constexpr size_t APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL = 0x8D4;
static constexpr size_t APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL = 0x8D8;
static constexpr size_t APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL = 0xA98;
static constexpr size_t APB_MISC_GP_VGPIO_GPIO_MUX_SEL = 0xB74;
static constexpr size_t PINMUX_AUX_SDMMC1_CLK = 0x00;
static constexpr size_t PINMUX_AUX_SDMMC1_CMD = 0x04;
static constexpr size_t PINMUX_AUX_SDMMC1_DAT3 = 0x08;
static constexpr size_t PINMUX_AUX_SDMMC1_DAT2 = 0x0C;
static constexpr size_t PINMUX_AUX_SDMMC1_DAT1 = 0x10;
static constexpr size_t PINMUX_AUX_SDMMC1_DAT0 = 0x14;
static constexpr size_t PINMUX_AUX_SDMMC3_CLK = 0x1C;
static constexpr size_t PINMUX_AUX_SDMMC3_CMD = 0x20;
static constexpr size_t PINMUX_AUX_SDMMC3_DAT0 = 0x24;
static constexpr size_t PINMUX_AUX_SDMMC3_DAT1 = 0x28;
static constexpr size_t PINMUX_AUX_SDMMC3_DAT2 = 0x2C;
static constexpr size_t PINMUX_AUX_SDMMC3_DAT3 = 0x30;
static constexpr size_t PINMUX_AUX_DMIC3_CLK = 0xB4;
static constexpr size_t PINMUX_AUX_UART2_TX = 0xF4;
static constexpr size_t PINMUX_AUX_UART3_TX = 0x104;
static constexpr size_t PINMUX_AUX_WIFI_EN = 0x1B4;
static constexpr size_t PINMUX_AUX_WIFI_RST = 0x1B8;
static constexpr size_t PINMUX_AUX_NFC_EN = 0x1D0;
static constexpr size_t PINMUX_AUX_NFC_INT = 0x1D4;
static constexpr size_t PINMUX_AUX_LCD_BL_PWM = 0x1FC;
static constexpr size_t PINMUX_AUX_LCD_BL_EN = 0x200;
static constexpr size_t PINMUX_AUX_LCD_RST = 0x204;
static constexpr size_t PINMUX_AUX_GPIO_PE6 = 0x248;
static constexpr size_t PINMUX_AUX_GPIO_PH6 = 0x250;
static constexpr size_t PINMUX_AUX_GPIO_PZ1 = 0x280;
static constexpr u32 PINMUX_FUNC_MASK = (3 << 0);
static constexpr u32 PINMUX_PULL_MASK = (3 << 2);
static constexpr u32 PINMUX_PULL_NONE = (0 << 2);
static constexpr u32 PINMUX_PULL_DOWN = (1 << 2);
static constexpr u32 PINMUX_PULL_UP = (2 << 2);
static constexpr u32 PINMUX_TRISTATE = (1 << 4);
static constexpr u32 PINMUX_PARKED = (1 << 5);
static constexpr u32 PINMUX_INPUT_ENABLE = (1 << 6);
static constexpr u32 PINMUX_LOCK = (1 << 7);
static constexpr u32 PINMUX_LPDR = (1 << 8);
static constexpr u32 PINMUX_HSM = (1 << 9);
static constexpr u32 PINMUX_IO_HV = (1 << 10);
static constexpr u32 PINMUX_OPEN_DRAIN = (1 << 11);
static constexpr u32 PINMUX_SCHMT = (1 << 12);
static constexpr u32 PINMUX_DRIVE_1X = (0 << 13) ;
static constexpr u32 PINMUX_DRIVE_2X = (1 << 13);
static constexpr u32 PINMUX_DRIVE_3X = (2 << 13);
static constexpr u32 PINMUX_DRIVE_4X = (3 << 13);

71
stratosphere/boot/source/boot_registers_pmc.hpp Normal file
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@ -0,0 +1,71 @@
/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <switch.h>
#include "boot_types.hpp"
static constexpr uintptr_t PmcBase = 0x7000E400ul;
static constexpr size_t APBDEV_PMC_CNTRL = 0x0;
static constexpr u32 PMC_CNTRL_MAIN_RST = (1 << 4);
static constexpr size_t APBDEV_PMC_SEC_DISABLE = 0x4;
static constexpr size_t APBDEV_PMC_PWRGATE_TOGGLE = 0x30;
static constexpr size_t APBDEV_PMC_PWRGATE_STATUS = 0x38;
static constexpr size_t APBDEV_PMC_NO_IOPOWER = 0x44;
static constexpr size_t APBDEV_PMC_SCRATCH0 = 0x50;
static constexpr size_t APBDEV_PMC_SCRATCH1 = 0x54;
static constexpr size_t APBDEV_PMC_SCRATCH20 = 0xA0;
static constexpr size_t APBDEV_PMC_PWR_DET_VAL = 0xE4;
static constexpr u32 PMC_PWR_DET_SDMMC1_IO_EN = (1 << 12);
static constexpr size_t APBDEV_PMC_DDR_PWR = 0xE8;
static constexpr size_t APBDEV_PMC_CRYPTO_OP = 0xF4;
static constexpr u32 PMC_CRYPTO_OP_SE_ENABLE = 0;
static constexpr u32 PMC_CRYPTO_OP_SE_DISABLE = 1;
static constexpr size_t APBDEV_PMC_SCRATCH33 = 0x120;
static constexpr size_t APBDEV_PMC_SCRATCH40 = 0x13C;
static constexpr size_t APBDEV_PMC_OSC_EDPD_OVER = 0x1A4;
static constexpr size_t APBDEV_PMC_RST_STATUS = 0x1B4;
static constexpr size_t APBDEV_PMC_IO_DPD_REQ = 0x1B8;
static constexpr size_t APBDEV_PMC_IO_DPD2_REQ = 0x1C0;
static constexpr size_t APBDEV_PMC_VDDP_SEL = 0x1CC;
static constexpr size_t APBDEV_PMC_DDR_CFG = 0x1D0;
static constexpr size_t APBDEV_PMC_SCRATCH45 = 0x234;
static constexpr size_t APBDEV_PMC_SCRATCH46 = 0x238;
static constexpr size_t APBDEV_PMC_SCRATCH49 = 0x244;
static constexpr size_t APBDEV_PMC_TSC_MULT = 0x2B4;
static constexpr size_t APBDEV_PMC_SEC_DISABLE2 = 0x2C4;
static constexpr size_t APBDEV_PMC_WEAK_BIAS = 0x2C8;
static constexpr size_t APBDEV_PMC_REG_SHORT = 0x2CC;
static constexpr size_t APBDEV_PMC_SEC_DISABLE3 = 0x2D8;
static constexpr size_t APBDEV_PMC_SECURE_SCRATCH21 = 0x334;
static constexpr size_t APBDEV_PMC_SECURE_SCRATCH32 = 0x360;
static constexpr size_t APBDEV_PMC_SECURE_SCRATCH49 = 0x3A4;
static constexpr size_t APBDEV_PMC_CNTRL2 = 0x440;
static constexpr size_t APBDEV_PMC_IO_DPD3_REQ = 0x45C;
static constexpr size_t APBDEV_PMC_IO_DPD4_REQ = 0x464;
static constexpr size_t APBDEV_PMC_UTMIP_PAD_CFG1 = 0x4C4;
static constexpr size_t APBDEV_PMC_UTMIP_PAD_CFG3 = 0x4CC;
static constexpr size_t APBDEV_PMC_DDR_CNTRL = 0x4E4;
static constexpr size_t APBDEV_PMC_SEC_DISABLE4 = 0x5B0;
static constexpr size_t APBDEV_PMC_SEC_DISABLE5 = 0x5B4;
static constexpr size_t APBDEV_PMC_SEC_DISABLE6 = 0x5B8;
static constexpr size_t APBDEV_PMC_SEC_DISABLE7 = 0x5BC;
static constexpr size_t APBDEV_PMC_SEC_DISABLE8 = 0x5C0;
static constexpr size_t APBDEV_PMC_SCRATCH188 = 0x810;
static constexpr size_t APBDEV_PMC_SCRATCH190 = 0x818;
static constexpr size_t APBDEV_PMC_SCRATCH200 = 0x840;

14
stratosphere/boot/source/boot_spl_utils.cpp
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@ -30,4 +30,18 @@ bool Boot::IsRecoveryBoot() {
std::abort();
}
return val != 0;
}
bool Boot::IsMariko() {
HardwareType hw_type = GetHardwareType();
switch (hw_type) {
case HardwareType_Icosa:
case HardwareType_Copper:
return false;
case HardwareType_Hoag:
case HardwareType_Iowa:
return true;
default:
std::abort();
}
}

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/*
* Copyright (c) 2018-2019 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "boot_functions.hpp"
#include "boot_splash_screen_notext.hpp"
/* TODO: Compile-time switch for splash_screen_text.hpp? */
void Boot::ShowSplashScreen() {
const u32 boot_reason = Boot::GetBootReason();
if (boot_reason == 1 || boot_reason == 4) {
return;
}
Boot::InitializeDisplay();
{
/* Splash screen is shown for 2 seconds. */
Boot::ShowDisplay(SplashScreenX, SplashScreenY, SplashScreenW, SplashScreenH, SplashScreen);
svcSleepThread(2'000'000'000ul);
}
Boot::FinalizeDisplay();
}

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stratosphere/boot/source/boot_splash_screen_text.hpp Normal file
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