From e0f1e637f79a6eae88178a6576a3a74a953d1929 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Mon, 17 Dec 2018 12:39:35 -0800 Subject: [PATCH] Add single source of truth for target firmwares. --- .gitignore | 8 + common/include/atmosphere.h | 1 + common/include/atmosphere/target_fw.h | 36 ++ exosphere/lp0fw/Makefile | 2 +- exosphere/lp0fw/src/lp0.c | 8 +- exosphere/lp0fw/src/lp0.h | 2 +- exosphere/lp0fw/src/mc.c | 40 ++ exosphere/lp0fw/src/mc.h | 614 +++++++++++++++++++++ exosphere/lp0fw/src/start.s | 5 +- exosphere/lp0fw/src/utils.h | 1 + exosphere/src/bootup.c | 26 +- exosphere/src/coldboot_init.c | 8 +- exosphere/src/configitem.c | 10 +- exosphere/src/cpu_context.c | 4 +- exosphere/src/exocfg.c | 4 +- exosphere/src/exocfg.h | 15 +- exosphere/src/fuse.c | 2 +- exosphere/src/mc.c | 10 +- exosphere/src/package2.c | 50 +- exosphere/src/sc7.c | 14 +- exosphere/src/sealedkeys.c | 2 +- exosphere/src/smc_api.c | 20 +- exosphere/src/smc_user.c | 48 +- exosphere/src/titlekey.c | 2 +- exosphere/src/warmboot_init.c | 6 +- exosphere/src/warmboot_main.c | 4 +- fusee/fusee-secondary/src/exocfg.h | 12 +- fusee/fusee-secondary/src/key_derivation.c | 24 +- fusee/fusee-secondary/src/nxboot.c | 40 +- fusee/fusee-secondary/src/nxboot_iram.c | 6 +- fusee/fusee-secondary/src/stratosphere.c | 2 +- 31 files changed, 855 insertions(+), 171 deletions(-) create mode 100644 common/include/atmosphere/target_fw.h create mode 100644 exosphere/lp0fw/src/mc.c create mode 100644 exosphere/lp0fw/src/mc.h diff --git a/.gitignore b/.gitignore index f55c55a62..d759ff7f0 100644 --- a/.gitignore +++ b/.gitignore @@ -65,6 +65,14 @@ dkms.conf *.tgz *.zip +# IDA binaries +*.id0 +*.id1 +*.id2 +*.idb +*.nam +*.til + .**/ # NOTE: make sure to make exceptions to this pattern when needed! diff --git a/common/include/atmosphere.h b/common/include/atmosphere.h index 86f2f0427..09f2faccf 100644 --- a/common/include/atmosphere.h +++ b/common/include/atmosphere.h @@ -22,6 +22,7 @@ extern "C" { #endif #include "atmosphere/version.h" +#include "atmosphere/target_fw.h" #ifdef __cplusplus } diff --git a/common/include/atmosphere/target_fw.h b/common/include/atmosphere/target_fw.h new file mode 100644 index 000000000..03f689e94 --- /dev/null +++ b/common/include/atmosphere/target_fw.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ATMOSPHERE_TARGET_FIRMWARE_H +#define ATMOSPHERE_TARGET_FIRMWARE_H + +#define ATMOSPHERE_TARGET_FIRMWARE_100 1 +#define ATMOSPHERE_TARGET_FIRMWARE_200 2 +#define ATMOSPHERE_TARGET_FIRMWARE_300 3 +#define ATMOSPHERE_TARGET_FIRMWARE_400 4 +#define ATMOSPHERE_TARGET_FIRMWARE_500 5 +#define ATMOSPHERE_TARGET_FIRMWARE_600 6 +#define ATMOSPHERE_TARGET_FIRMWARE_620 7 + +#define ATMOSPHERE_TARGET_FIRMWARE_CURRENT ATMOSPHERE_TARGET_FIRMWARE_620 + +#define ATMOSPHERE_TARGET_FIRMWARE_MIN ATMOSPHERE_TARGET_FIRMWARE_100 +#define ATMOSPHERE_TARGET_FIRMWARE_MAX ATMOSPHERE_TARGET_FIRMWARE_620 + +/* TODO: What should this be, for release? */ +#define ATMOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG ATMOSPHERE_TARGET_FIRMWARE_CURRENT + +#endif \ No newline at end of file diff --git a/exosphere/lp0fw/Makefile b/exosphere/lp0fw/Makefile index 0eadd1314..e8afccfd1 100644 --- a/exosphere/lp0fw/Makefile +++ b/exosphere/lp0fw/Makefile @@ -20,7 +20,7 @@ TARGET := $(notdir $(CURDIR)) BUILD := build SOURCES := src DATA := data -INCLUDES := include +INCLUDES := include ../../common/include #--------------------------------------------------------------------------------- # options for code generation diff --git a/exosphere/lp0fw/src/lp0.c b/exosphere/lp0fw/src/lp0.c index b363748e8..7f1c77ec4 100644 --- a/exosphere/lp0fw/src/lp0.c +++ b/exosphere/lp0fw/src/lp0.c @@ -16,6 +16,7 @@ #include "utils.h" #include "lp0.h" +#include "mc.h" #include "pmc.h" #include "timer.h" @@ -29,10 +30,15 @@ void reboot(void) { void lp0_entry_main(warmboot_metadata_t *meta) { /* Before doing anything else, ensure some sanity. */ - if (meta->magic != WARMBOOT_MAGIC || meta->tz_relative_offset > 0x2000) { + if (meta->magic != WARMBOOT_MAGIC || meta->target_firmware > ATMOSPHERE_TARGET_FIRMWARE_MAX) { reboot(); } + /* [4.0.0+] First thing warmboot does is disable BPMP access to memory. */ + if (meta->target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400) { + disable_bpmp_access_to_dram(); + } + /* TODO: stuff */ while (true) { /* TODO: Halt BPMP */ } diff --git a/exosphere/lp0fw/src/lp0.h b/exosphere/lp0fw/src/lp0.h index 189813d9b..90cdb6850 100644 --- a/exosphere/lp0fw/src/lp0.h +++ b/exosphere/lp0fw/src/lp0.h @@ -24,7 +24,7 @@ typedef struct { uint32_t magic; - uint32_t tz_relative_offset; + uint32_t target_firmware; uint32_t padding[2]; } warmboot_metadata_t; diff --git a/exosphere/lp0fw/src/mc.c b/exosphere/lp0fw/src/mc.c new file mode 100644 index 000000000..a26ef285b --- /dev/null +++ b/exosphere/lp0fw/src/mc.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include "mc.h" +#include "utils.h" + +void disable_bpmp_access_to_dram(void) { + /* Modify carveout 4 to prevent BPMP access to dram (TZ will fix it). */ + volatile security_carveout_t *carveout = (volatile security_carveout_t *)(MC_BASE + 0xC08 + 0x50 * (4 - CARVEOUT_ID_MIN)); + carveout->paddr_low = 0; + carveout->paddr_high = 0; + carveout->size_big_pages = 1; /* 128 KiB */ + carveout->client_access_0 = 0; + carveout->client_access_1 = 0; + carveout->client_access_2 = 0; + carveout->client_access_3 = 0; + carveout->client_access_4 = 0; + carveout->client_force_internal_access_0 = BIT(CSR_AVPCARM7R); + carveout->client_force_internal_access_1 = BIT(CSW_AVPCARM7W); + carveout->client_force_internal_access_2 = 0; + carveout->client_force_internal_access_3 = 0; + carveout->client_force_internal_access_4 = 0; + /* Set config to LOCKED, TZ-SECURE, untranslated addresses only. */ + carveout->config = 0x8F; +} diff --git a/exosphere/lp0fw/src/mc.h b/exosphere/lp0fw/src/mc.h new file mode 100644 index 000000000..647a826c4 --- /dev/null +++ b/exosphere/lp0fw/src/mc.h @@ -0,0 +1,614 @@ +/* + * Copyright (c) 2018 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef EXOSPHERE_WARMBOOT_BIN_MC_H +#define EXOSPHERE_WARMBOOT_BIN_MC_H + +#include + +#define MC_BASE_PHYS 0x70019000 + +#define MC_BASE (MC_BASE_PHYS) +#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n) + +#define MC_INTSTATUS 0x0 +#define MC_INTMASK 0x4 +#define MC_ERR_STATUS 0x8 +#define MC_ERR_ADR 0xc +#define MC_SMMU_CONFIG 0x10 +#define MC_SMMU_TLB_CONFIG 0x14 +#define MC_SMMU_PTC_CONFIG 0x18 +#define MC_SMMU_PTB_ASID 0x1c +#define MC_SMMU_PTB_DATA 0x20 +#define MC_SMMU_TLB_FLUSH 0x30 +#define MC_SMMU_PTC_FLUSH 0x34 +#define MC_SMMU_AFI_ASID 0x238 +#define MC_SMMU_AVPC_ASID 0x23c +#define MC_SMMU_PPCS1_ASID 0x298 +#define MC_SMMU_TRANSLATION_ENABLE_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98 +#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0 +#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 +#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 +#define MC_PCFIFO_CLIENT_CONFIG3 0xddc +#define MC_PCFIFO_CLIENT_CONFIG4 0xde0 +#define MC_EMEM_CFG 0x50 +#define MC_EMEM_ADR_CFG 0x54 +#define MC_EMEM_ADR_CFG_DEV0 0x58 +#define MC_EMEM_ADR_CFG_DEV1 0x5c +#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60 +#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 +#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 +#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c +#define MC_SECURITY_CFG0 0x70 +#define MC_SECURITY_CFG1 0x74 +#define MC_SECURITY_CFG3 0x9bc +#define MC_SECURITY_RSV 0x7c +#define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_TIMING_RCD 0x98 +#define MC_EMEM_ARB_TIMING_RP 0x9c +#define MC_EMEM_ARB_TIMING_RC 0xa0 +#define MC_EMEM_ARB_TIMING_RAS 0xa4 +#define MC_EMEM_ARB_TIMING_FAW 0xa8 +#define MC_EMEM_ARB_TIMING_RRD 0xac +#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 +#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 +#define MC_EMEM_ARB_TIMING_R2R 0xb8 +#define MC_EMEM_ARB_TIMING_W2W 0xbc +#define MC_EMEM_ARB_TIMING_R2W 0xc0 +#define MC_EMEM_ARB_TIMING_W2R 0xc4 +#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 +#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 +#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 +#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 +#define MC_EMEM_ARB_DA_TURNS 0xd0 +#define MC_EMEM_ARB_DA_COVERS 0xd4 +#define MC_EMEM_ARB_MISC0 0xd8 +#define MC_EMEM_ARB_MISC1 0xdc +#define MC_EMEM_ARB_MISC2 0xc8 +#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 +#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 +#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0 +#define MC_EMEM_ARB_OVERRIDE 0xe8 +#define MC_EMEM_ARB_RSV 0xec +#define MC_CLKEN_OVERRIDE 0xf4 +#define MC_TIMING_CONTROL_DBG 0xf8 +#define MC_TIMING_CONTROL 0xfc +#define MC_STAT_CONTROL 0x100 +#define MC_STAT_STATUS 0x104 +#define MC_STAT_EMC_CLOCK_LIMIT 0x108 +#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c +#define MC_STAT_EMC_CLOCKS 0x110 +#define MC_STAT_EMC_CLOCKS_MSBS 0x114 +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118 +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158 +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20 +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24 +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198 +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8 +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28 +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c +#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0 +#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0 +#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120 +#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c +#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c +#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c +#define MC_STAT_EMC_SET0_COUNT 0x138 +#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c +#define MC_STAT_EMC_SET1_COUNT 0x178 +#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c +#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140 +#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144 +#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180 +#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184 +#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148 +#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c +#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188 +#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c +#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150 +#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190 +#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8 +#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc +#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8 +#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc +#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0 +#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0 +#define MC_CLIENT_HOTRESET_CTRL 0x200 +#define MC_CLIENT_HOTRESET_CTRL_1 0x970 +#define MC_CLIENT_HOTRESET_STATUS 0x204 +#define MC_CLIENT_HOTRESET_STATUS_1 0x974 +#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208 +#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c +#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 +#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214 +#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94 +#define MC_EMEM_ARB_HYSTERESIS_0 0x218 +#define MC_EMEM_ARB_HYSTERESIS_1 0x21c +#define MC_EMEM_ARB_HYSTERESIS_2 0x220 +#define MC_EMEM_ARB_HYSTERESIS_3 0x224 +#define MC_EMEM_ARB_HYSTERESIS_4 0xb84 +#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0 +#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4 +#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8 +#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc +#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0 +#define MC_EMEM_ARB_DHYST_CTRL 0xbcc +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec +#define MC_RESERVED_RSV 0x3fc +#define MC_DISB_EXTRA_SNAP_LEVELS 0x408 +#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4 +#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0 +#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18 +#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08 +#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10 +#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c +#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40 +#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414 +#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc +#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c +#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14 +#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0 +#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac +#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c +#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48 +#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8 +#define MC_USBX_EXTRA_SNAP_LEVELS 0x404 +#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8 +#define MC_SD_EXTRA_SNAP_LEVELS 0xa04 +#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c +#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8 +#define MC_GK_EXTRA_SNAP_LEVELS 0xa00 +#define MC_VE2_EXTRA_SNAP_LEVELS 0x410 +#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44 +#define MC_VIDEO_PROTECT_BOM 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978 +#define MC_VIDEO_PROTECT_REG_CTRL 0x650 +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 +#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590 +#define MC_IRAM_BOM 0x65c +#define MC_IRAM_TOM 0x660 +#define MC_IRAM_ADR_HI 0x980 +#define MC_IRAM_REG_CTRL 0x964 +#define MC_EMEM_CFG_ACCESS_CTRL 0x664 +#define MC_TZ_SECURITY_CTRL 0x668 +#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c +#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4 +#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc +#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8 +#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80 +#define MC_SEC_CARVEOUT_BOM 0x670 +#define MC_SEC_CARVEOUT_SIZE_MB 0x674 +#define MC_SEC_CARVEOUT_ADR_HI 0x9d4 +#define MC_SEC_CARVEOUT_REG_CTRL 0x678 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684 +#define MC_STUTTER_CONTROL 0x688 +#define MC_RESERVED_RSV_1 0x958 +#define MC_DVFS_PIPE_SELECT 0x95c +#define MC_AHB_PTSA_MIN 0x4e0 +#define MC_AUD_PTSA_MIN 0x54c +#define MC_MLL_MPCORER_PTSA_RATE 0x44c +#define MC_RING2_PTSA_RATE 0x440 +#define MC_USBD_PTSA_RATE 0x530 +#define MC_USBX_PTSA_MIN 0x528 +#define MC_USBD_PTSA_MIN 0x534 +#define MC_APB_PTSA_MAX 0x4f0 +#define MC_JPG_PTSA_RATE 0x584 +#define MC_DIS_PTSA_MIN 0x420 +#define MC_AVP_PTSA_MAX 0x4fc +#define MC_AVP_PTSA_RATE 0x4f4 +#define MC_RING1_PTSA_MIN 0x480 +#define MC_DIS_PTSA_MAX 0x424 +#define MC_SD_PTSA_MAX 0x4d8 +#define MC_MSE_PTSA_RATE 0x4c4 +#define MC_VICPC_PTSA_MIN 0x558 +#define MC_PCX_PTSA_MAX 0x4b4 +#define MC_ISP_PTSA_RATE 0x4a0 +#define MC_A9AVPPC_PTSA_MIN 0x48c +#define MC_RING2_PTSA_MAX 0x448 +#define MC_AUD_PTSA_RATE 0x548 +#define MC_HOST_PTSA_MIN 0x51c +#define MC_MLL_MPCORER_PTSA_MAX 0x454 +#define MC_SD_PTSA_MIN 0x4d4 +#define MC_RING1_PTSA_RATE 0x47c +#define MC_JPG_PTSA_MIN 0x588 +#define MC_HDAPC_PTSA_MIN 0x62c +#define MC_AVP_PTSA_MIN 0x4f8 +#define MC_JPG_PTSA_MAX 0x58c +#define MC_VE_PTSA_MAX 0x43c +#define MC_DFD_PTSA_MAX 0x63c +#define MC_VICPC_PTSA_RATE 0x554 +#define MC_GK_PTSA_MAX 0x544 +#define MC_VICPC_PTSA_MAX 0x55c +#define MC_SDM_PTSA_MAX 0x624 +#define MC_SAX_PTSA_RATE 0x4b8 +#define MC_PCX_PTSA_MIN 0x4b0 +#define MC_APB_PTSA_MIN 0x4ec +#define MC_GK2_PTSA_MIN 0x614 +#define MC_PCX_PTSA_RATE 0x4ac +#define MC_RING1_PTSA_MAX 0x484 +#define MC_HDAPC_PTSA_RATE 0x628 +#define MC_MLL_MPCORER_PTSA_MIN 0x450 +#define MC_GK2_PTSA_MAX 0x618 +#define MC_AUD_PTSA_MAX 0x550 +#define MC_GK2_PTSA_RATE 0x610 +#define MC_ISP_PTSA_MAX 0x4a8 +#define MC_DISB_PTSA_RATE 0x428 +#define MC_VE2_PTSA_MAX 0x49c +#define MC_DFD_PTSA_MIN 0x638 +#define MC_FTOP_PTSA_RATE 0x50c +#define MC_A9AVPPC_PTSA_RATE 0x488 +#define MC_VE2_PTSA_MIN 0x498 +#define MC_USBX_PTSA_MAX 0x52c +#define MC_DIS_PTSA_RATE 0x41c +#define MC_USBD_PTSA_MAX 0x538 +#define MC_A9AVPPC_PTSA_MAX 0x490 +#define MC_USBX_PTSA_RATE 0x524 +#define MC_FTOP_PTSA_MAX 0x514 +#define MC_HDAPC_PTSA_MAX 0x630 +#define MC_SD_PTSA_RATE 0x4d0 +#define MC_DFD_PTSA_RATE 0x634 +#define MC_FTOP_PTSA_MIN 0x510 +#define MC_SDM_PTSA_RATE 0x61c +#define MC_AHB_PTSA_RATE 0x4dc +#define MC_SMMU_SMMU_PTSA_MAX 0x460 +#define MC_RING2_PTSA_MIN 0x444 +#define MC_SDM_PTSA_MIN 0x620 +#define MC_APB_PTSA_RATE 0x4e8 +#define MC_MSE_PTSA_MIN 0x4c8 +#define MC_HOST_PTSA_RATE 0x518 +#define MC_VE_PTSA_RATE 0x434 +#define MC_AHB_PTSA_MAX 0x4e4 +#define MC_SAX_PTSA_MIN 0x4bc +#define MC_SMMU_SMMU_PTSA_MIN 0x45c +#define MC_ISP_PTSA_MIN 0x4a4 +#define MC_HOST_PTSA_MAX 0x520 +#define MC_SAX_PTSA_MAX 0x4c0 +#define MC_VE_PTSA_MIN 0x438 +#define MC_GK_PTSA_MIN 0x540 +#define MC_MSE_PTSA_MAX 0x4cc +#define MC_DISB_PTSA_MAX 0x430 +#define MC_DISB_PTSA_MIN 0x42c +#define MC_SMMU_SMMU_PTSA_RATE 0x458 +#define MC_VE2_PTSA_RATE 0x494 +#define MC_GK_PTSA_RATE 0x53c +#define MC_PTSA_GRANT_DECREMENT 0x960 +#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 +#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 +#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 +#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384 +#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc +#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 +#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 +#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 +#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 +#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 +#define MC_LATENCY_ALLOWANCE_VIC_0 0x394 +#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 +#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 +#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc +#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 +#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694 +#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 +#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c +#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 +#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 +#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698 +#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec +#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0 +#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4 +#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 +#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 +#define MC_LATENCY_ALLOWANCE_HC_1 0x314 +#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 +#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 +#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c +#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec +#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 +#define MC_LATENCY_ALLOWANCE_VI2_0 0x398 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4 +#define MC_LATENCY_ALLOWANCE_SATA_0 0x350 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690 +#define MC_LATENCY_ALLOWANCE_HC_0 0x310 +#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8 +#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac +#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 +#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388 +#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 +#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 +#define MC_MIN_LENGTH_APE_0 0xb34 +#define MC_MIN_LENGTH_DCB_2 0x8a8 +#define MC_MIN_LENGTH_A9AVP_0 0x950 +#define MC_MIN_LENGTH_TSEC_0 0x93c +#define MC_MIN_LENGTH_DC_1 0x898 +#define MC_MIN_LENGTH_AXIAP_0 0x94c +#define MC_MIN_LENGTH_ISP2B_0 0x930 +#define MC_MIN_LENGTH_VI2_0 0x944 +#define MC_MIN_LENGTH_DCB_0 0x8a0 +#define MC_MIN_LENGTH_DCB_1 0x8a4 +#define MC_MIN_LENGTH_PPCS_1 0x8f4 +#define MC_MIN_LENGTH_NVJPG_0 0xb3c +#define MC_MIN_LENGTH_HDA_0 0x8c4 +#define MC_MIN_LENGTH_NVENC_0 0x8d4 +#define MC_MIN_LENGTH_SDMMC_0 0xb18 +#define MC_MIN_LENGTH_ISP2B_1 0x934 +#define MC_MIN_LENGTH_HC_1 0x8c0 +#define MC_MIN_LENGTH_DC_3 0xb20 +#define MC_MIN_LENGTH_AVPC_0 0x890 +#define MC_MIN_LENGTH_VIC_0 0x940 +#define MC_MIN_LENGTH_ISP2_0 0x91c +#define MC_MIN_LENGTH_HC_0 0x8bc +#define MC_MIN_LENGTH_SE_0 0xb38 +#define MC_MIN_LENGTH_NVDEC_0 0xb30 +#define MC_MIN_LENGTH_SATA_0 0x8fc +#define MC_MIN_LENGTH_DC_0 0x894 +#define MC_MIN_LENGTH_XUSB_1 0x92c +#define MC_MIN_LENGTH_DC_2 0x89c +#define MC_MIN_LENGTH_SDMMCAA_0 0xb14 +#define MC_MIN_LENGTH_GPU_0 0xb04 +#define MC_MIN_LENGTH_ETR_0 0xb44 +#define MC_MIN_LENGTH_AFI_0 0x88c +#define MC_MIN_LENGTH_PPCS_0 0x8f0 +#define MC_MIN_LENGTH_ISP2_1 0x920 +#define MC_MIN_LENGTH_XUSB_0 0x928 +#define MC_MIN_LENGTH_MPCORE_0 0x8cc +#define MC_MIN_LENGTH_TSECB_0 0xb48 +#define MC_MIN_LENGTH_SDMMCA_0 0xb10 +#define MC_MIN_LENGTH_GPU2_0 0xb40 +#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c +#define MC_MIN_LENGTH_PTC_0 0x8f8 +#define MC_EMEM_ARB_OVERRIDE_1 0x968 +#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984 +#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988 +#define MC_EMEM_ARB_STATS_0 0x990 +#define MC_EMEM_ARB_STATS_1 0x994 +#define MC_MTS_CARVEOUT_BOM 0x9a0 +#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4 +#define MC_MTS_CARVEOUT_ADR_HI 0x9a8 +#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74 +#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10 +#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c +#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4 +#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 +#define MC_SECURITY_CARVEOUT1_CFG0 0xc08 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68 +#define MC_SECURITY_CARVEOUT3_BOM 0xcac +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60 +#define MC_SECURITY_CARVEOUT3_CFG0 0xca8 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88 +#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64 +#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50 +#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14 +#define MC_SECURITY_CARVEOUT1_BOM 0xc0c +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c +#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8 +#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60 +#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80 +#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc +#define MC_SECURITY_CARVEOUT4_BOM 0xcfc +#define MC_SECURITY_CARVEOUT5_CFG0 0xd48 +#define MC_SECURITY_CARVEOUT2_BOM 0xc5c +#define MC_SECURITY_CARVEOUT5_BOM 0xd4c +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0 +#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 +#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 +#define MC_DA_CONFIG0 0x9dc + +/* Virtual aliases */ +#define VIRT_MC_SECURITY_CFG3 MAKE_MC_REG(MC_SECURITY_CFG3) + +/* Memory Controller clients */ +#define CLIENT_ACCESS_NUM_CLIENTS 32 +typedef enum { + /* _ACCESS0 */ + CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), + + /* _ACCESS1 */ + CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), + + /* _ACCESS2 */ + CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), + + /* _ACCESS3 */ + CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), + + /* _ACCESS4 */ + CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), + CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4)) +} McClient; + +/* Memory Controller carveouts */ +#define CARVEOUT_ID_MIN 1 +#define CARVEOUT_ID_MAX 5 +typedef struct { + uint32_t config; + uint32_t paddr_low; + uint32_t paddr_high; + uint32_t size_big_pages; + uint32_t client_access_0; + uint32_t client_access_1; + uint32_t client_access_2; + uint32_t client_access_3; + uint32_t client_access_4; + uint32_t client_force_internal_access_0; + uint32_t client_force_internal_access_1; + uint32_t client_force_internal_access_2; + uint32_t client_force_internal_access_3; + uint32_t client_force_internal_access_4; + uint8_t padding[0x18]; +} security_carveout_t; + +void disable_bpmp_access_to_dram(void); + +#endif \ No newline at end of file diff --git a/exosphere/lp0fw/src/start.s b/exosphere/lp0fw/src/start.s index 9abe6a391..17aab0bfc 100644 --- a/exosphere/lp0fw/src/start.s +++ b/exosphere/lp0fw/src/start.s @@ -47,14 +47,11 @@ .global _start _start: b crt0 -.rept 0x7C - .word 0x00000000 /* Padding */ -.endr .global _metadata _metadata: .ascii "WBT0" /* Magic number */ - .word 0x00000000 /* TrustZone relative base. */ + .word 0x00000000 /* Target firmware. */ .word 0x00000000 /* Reserved */ .word 0x00000000 /* Reserved */ diff --git a/exosphere/lp0fw/src/utils.h b/exosphere/lp0fw/src/utils.h index 60a48d6b6..f1e43cec6 100644 --- a/exosphere/lp0fw/src/utils.h +++ b/exosphere/lp0fw/src/utils.h @@ -20,6 +20,7 @@ #include #include #include +#include #define BIT(n) (1u << (n)) #define BITL(n) (1ull << (n)) diff --git a/exosphere/src/bootup.c b/exosphere/src/bootup.c index 9d01ae08a..fbaf2bb27 100644 --- a/exosphere/src/bootup.c +++ b/exosphere/src/bootup.c @@ -52,7 +52,7 @@ void setup_dram_magic_numbers(void) { unsigned int target_fw = exosphere_get_target_firmware(); (*(volatile uint32_t *)(0x8005FFFC)) = 0xC0EDBBCC; /* Access test value. */ flush_dcache_range((void *)0x8005FFFC, (void *)0x80060000); - if (EXOSPHERE_TARGET_FIRMWARE_600 <= target_fw) { + if (ATMOSPHERE_TARGET_FIRMWARE_600 <= target_fw) { (*(volatile uint32_t *)(0x8005FF00)) = 0x00000083; /* SKU code. */ (*(volatile uint32_t *)(0x8005FF04)) = 0x00000002; (*(volatile uint32_t *)(0x8005FF08)) = 0x00000210; /* Tegra210 code. */ @@ -81,7 +81,7 @@ void bootup_misc_mmio(void) { se_generate_random_key(KEYSLOT_SWITCH_SRKGENKEY, KEYSLOT_SWITCH_RNGKEY); se_generate_srk(KEYSLOT_SWITCH_SRKGENKEY); - if (!g_has_booted_up && (EXOSPHERE_TARGET_FIRMWARE_600 > exosphere_get_target_firmware())) { + if (!g_has_booted_up && (ATMOSPHERE_TARGET_FIRMWARE_600 > exosphere_get_target_firmware())) { setup_dram_magic_numbers(); } @@ -113,7 +113,7 @@ void bootup_misc_mmio(void) { configure_default_carveouts(); /* Mark registers secure world only. */ - if (exosphere_get_target_firmware() == EXOSPHERE_TARGET_FIRMWARE_100) { + if (exosphere_get_target_firmware() == ATMOSPHERE_TARGET_FIRMWARE_100) { APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = APB_SSER0_SATA_AUX | APB_SSER0_DTV | APB_SSER0_QSPI | APB_SSER0_SATA | APB_SSER0_LA; APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = APB_SSER1_SPI1 | APB_SSER1_SPI2 | APB_SSER1_SPI3 | APB_SSER1_SPI5 | APB_SSER1_SPI6 | APB_SSER1_I2C4 | APB_SSER1_I2C6; APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = 1 << 4 | 1 << 5 | APB_SSER2_DDS; /* bits 4 and 5 are not labeled in 21.1.7.3 */ @@ -130,7 +130,7 @@ void bootup_misc_mmio(void) { /* Also mark I2C4 secure only, */ sec_disable_1 |= APB_SSER1_I2C4; } - if (hardware_type != 0 && exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (hardware_type != 0 && exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { /* Starting on 4.x on non-dev units, mark UARTB, UARTC, SPI4, I2C3 secure only. */ sec_disable_1 |= APB_SSER1_UART_B | APB_SSER1_UART_C | APB_SSER1_SPI4 | APB_SSER1_I2C3; /* Starting on 4.x on non-dev units, mark SDMMC1 secure only. */ @@ -148,7 +148,7 @@ void bootup_misc_mmio(void) { MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF; /* TODO: What are these MC reg writes? */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { MAKE_MC_REG(0x038) = 0xE; } else { MAKE_MC_REG(0x038) = 0x0; @@ -163,7 +163,7 @@ void bootup_misc_mmio(void) { MAKE_MC_REG(0x9F0) = 0; MAKE_MC_REG(0x9F4) = 0; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0; } MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0; @@ -179,7 +179,7 @@ void bootup_misc_mmio(void) { /* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */ uint32_t reset_vec; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { reset_vec = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); } else { reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); @@ -205,7 +205,7 @@ void bootup_misc_mmio(void) { intr_set_cpu_mask(INTERRUPT_ID_SECURITY_ENGINE, 8); intr_set_edge_level(INTERRUPT_ID_SECURITY_ENGINE, 0); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { intr_set_priority(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0); intr_set_group(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 0); intr_set_enabled(INTERRUPT_ID_ACTIVITY_MONITOR_4X, 1); @@ -220,14 +220,14 @@ void bootup_misc_mmio(void) { uart_init(UART_A, 115200); intr_register_handler(INTERRUPT_ID_SECURITY_ENGINE, se_operation_completed); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { intr_register_handler(INTERRUPT_ID_ACTIVITY_MONITOR_4X, actmon_interrupt_handler); } for (unsigned int core = 1; core < NUM_CPU_CORES; core++) { set_core_is_active(core, false); } g_has_booted_up = true; - } else if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) { + } else if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400) { /* Disable AHB redirect. */ MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000; MAKE_MC_REG(MC_IRAM_TOM) = 0; @@ -237,7 +237,7 @@ void bootup_misc_mmio(void) { } void setup_4x_mmio(void) { - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) { configure_gpu_ucode_carveout(); } @@ -360,9 +360,9 @@ void identity_unmap_iram_cd_tzram(void) { } void secure_additional_devices(void) { - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_200) { APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 |= APB_SSER0_PMC; /* make PMC secure-only (2.x+) */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 |= APB_SSER1_MC0 | APB_SSER1_MC1 | APB_SSER1_MCB; /* make MC0, MC1, MCB secure-only (4.x+) */ } } diff --git a/exosphere/src/coldboot_init.c b/exosphere/src/coldboot_init.c index aedc28277..1ea3ebb9c 100644 --- a/exosphere/src/coldboot_init.c +++ b/exosphere/src/coldboot_init.c @@ -91,7 +91,7 @@ static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl, unsigned int target_fi static const uintptr_t offs_5x[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZ5XS, COMMA) }; for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) { - uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i]; + uintptr_t off = (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i]; tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + off, sizes[i], is_executable[i]); offset += increments[i]; } @@ -101,7 +101,7 @@ static void configure_ttbls(unsigned int target_firmware) { uintptr_t *mmu_l1_tbl; uintptr_t *mmu_l2_tbl; uintptr_t *mmu_l3_tbl; - if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) { + if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_500) { mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); @@ -151,7 +151,7 @@ uintptr_t get_coldboot_crt0_temp_stack_address(void) { } uintptr_t get_coldboot_crt0_stack_address(void) { - if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware_for_init() < ATMOSPHERE_TARGET_FIRMWARE_500) { return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; } else { return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; @@ -193,7 +193,7 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold) init_dma_controllers(g_exosphere_target_firmware_for_init); configure_ttbls(g_exosphere_target_firmware_for_init); - if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { + if (g_exosphere_target_firmware_for_init < ATMOSPHERE_TARGET_FIRMWARE_500) { set_memory_registers_enable_mmu_1x_ttbr0(); } else { set_memory_registers_enable_mmu_5x_ttbr0(); diff --git a/exosphere/src/configitem.c b/exosphere/src/configitem.c index cac02b835..66a98730a 100644 --- a/exosphere/src/configitem.c +++ b/exosphere/src/configitem.c @@ -125,7 +125,7 @@ uint32_t configitem_get(bool privileged, ConfigItem item, uint64_t *p_outvalue) break; case CONFIGITEM_BOOTREASON: /* For some reason, Nintendo removed it on 4.0 */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400) { *p_outvalue = bootconfig_get_boot_reason(); } else { result = 2; @@ -149,7 +149,7 @@ uint32_t configitem_get(bool privileged, ConfigItem item, uint64_t *p_outvalue) break; case CONFIGITEM_ISQUESTUNIT: /* Added on 3.0, used to determine whether console is a kiosk unit. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_300) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_300) { *p_outvalue = (fuse_get_reserved_odm(4) >> 10) & 1; } else { result = 2; @@ -157,7 +157,7 @@ uint32_t configitem_get(bool privileged, ConfigItem item, uint64_t *p_outvalue) break; case CONFIGITEM_NEWHARDWARETYPE_5X: /* Added in 5.x, currently hardcoded to 0. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { *p_outvalue = 0; } else { result = 2; @@ -165,7 +165,7 @@ uint32_t configitem_get(bool privileged, ConfigItem item, uint64_t *p_outvalue) break; case CONFIGITEM_NEWKEYGENERATION_5X: /* Added in 5.x. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { *p_outvalue = fuse_get_5x_key_generation(); } else { result = 2; @@ -173,7 +173,7 @@ uint32_t configitem_get(bool privileged, ConfigItem item, uint64_t *p_outvalue) break; case CONFIGITEM_PACKAGE2HASH_5X: /* Added in 5.x. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500 && bootconfig_is_recovery_boot()) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500 && bootconfig_is_recovery_boot()) { bootconfig_get_package2_hash_for_recovery(p_outvalue); } else { result = 2; diff --git a/exosphere/src/cpu_context.c b/exosphere/src/cpu_context.c index ed307dc46..13fb03aab 100644 --- a/exosphere/src/cpu_context.c +++ b/exosphere/src/cpu_context.c @@ -100,7 +100,7 @@ uint32_t cpu_on(uint32_t core, uintptr_t entrypoint_addr, uint64_t argument) { static const uint32_t status_masks[NUM_CPU_CORES] = {0x4000, 0x200, 0x400, 0x800}; static const uint32_t toggle_vals[NUM_CPU_CORES] = {0xE, 0x9, 0xA, 0xB}; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { /* Reset the core */ CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET_0 = (1 << (core + 0x10)) | (1 << core); } @@ -133,7 +133,7 @@ uint32_t cpu_on(uint32_t core, uintptr_t entrypoint_addr, uint64_t argument) { } CPU_ON_SUCCESS: - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { /* Start the core */ CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0 = (1 << (core + 0x10)) | (1 << core); } diff --git a/exosphere/src/exocfg.c b/exosphere/src/exocfg.c index 77d655dd2..08a929d7f 100644 --- a/exosphere/src/exocfg.c +++ b/exosphere/src/exocfg.c @@ -27,7 +27,7 @@ /* TODO: Should this be at a non-static location? */ #define MAILBOX_EXOSPHERE_CONFIG (*((volatile exosphere_config_t *)(MAILBOX_BASE + 0xE40ULL))) -static exosphere_config_t g_exosphere_cfg = {MAGIC_EXOSPHERE_BOOTCONFIG, EXOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG, EXOSPHERE_FLAGS_DEFAULT}; +static exosphere_config_t g_exosphere_cfg = {MAGIC_EXOSPHERE_BOOTCONFIG, ATMOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG, EXOSPHERE_FLAGS_DEFAULT}; static bool g_has_loaded_config = false; #define EXOSPHERE_CHECK_FLAG(flag) ((g_exosphere_cfg.flags & flag) != 0) @@ -65,7 +65,7 @@ unsigned int exosphere_should_perform_620_keygen(void) { generic_panic(); } - return g_exosphere_cfg.target_firmware >= EXOSPHERE_TARGET_FIRMWARE_620 && EXOSPHERE_CHECK_FLAG(EXOSPHERE_FLAG_PERFORM_620_KEYGEN); + return g_exosphere_cfg.target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_620 && EXOSPHERE_CHECK_FLAG(EXOSPHERE_FLAG_PERFORM_620_KEYGEN); } unsigned int exosphere_should_override_debugmode_priv(void) { diff --git a/exosphere/src/exocfg.h b/exosphere/src/exocfg.h index 56ff82fdf..2f41c6cf1 100644 --- a/exosphere/src/exocfg.h +++ b/exosphere/src/exocfg.h @@ -18,6 +18,7 @@ #define EXOSPHERE_EXOSPHERE_CONFIG_H #include +#include #include "utils.h" #include "memory_map.h" @@ -29,18 +30,6 @@ /* "XBC1" */ #define MAGIC_EXOSPHERE_BOOTCONFIG (0x31434258) -#define EXOSPHERE_TARGET_FIRMWARE_100 1 -#define EXOSPHERE_TARGET_FIRMWARE_200 2 -#define EXOSPHERE_TARGET_FIRMWARE_300 3 -#define EXOSPHERE_TARGET_FIRMWARE_400 4 -#define EXOSPHERE_TARGET_FIRMWARE_500 5 -#define EXOSPHERE_TARGET_FIRMWARE_600 6 -#define EXOSPHERE_TARGET_FIRMWARE_620 7 - -#define EXOSPHERE_TARGET_FIRMWARE_CURRENT EXOSPHERE_TARGET_FIRMWARE_620 - -/* TODO: What should this be, for release? */ -#define EXOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG EXOSPHERE_TARGET_FIRMWARE_CURRENT #define EXOSPHERE_LOOSEN_PACKAGE2_RESTRICTIONS_FOR_DEBUG 1 #define MAILBOX_BASE_PHYS (MMIO_GET_DEVICE_PA(MMIO_DEVID_NXBOOTLOADER_MAILBOX)) @@ -70,7 +59,7 @@ static inline unsigned int exosphere_get_target_firmware_for_init(void) { if (magic == MAGIC_EXOSPHERE_BOOTCONFIG || magic == MAGIC_EXOSPHERE_BOOTCONFIG_0) { return MAILBOX_EXOSPHERE_CONFIG_PHYS.target_firmware; } else { - return EXOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG; + return ATMOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG; } } diff --git a/exosphere/src/fuse.c b/exosphere/src/fuse.c index 3cad511ea..b33459f42 100644 --- a/exosphere/src/fuse.c +++ b/exosphere/src/fuse.c @@ -207,7 +207,7 @@ uint32_t fuse_get_hardware_type(void) { /* This function is very different between 4.x and < 4.x */ uint32_t hardware_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 2) & 1); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { static const uint32_t types[] = {0,1,4,3}; hardware_type |= (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 14) & 0x3C; diff --git a/exosphere/src/mc.c b/exosphere/src/mc.c index 332614c4a..c1979eea3 100644 --- a/exosphere/src/mc.c +++ b/exosphere/src/mc.c @@ -47,7 +47,7 @@ void configure_gpu_ucode_carveout(void) { carveout->size_big_pages = 2; /* 0x40000 */ carveout->client_access_0 = 0; carveout->client_access_1 = 0; - carveout->client_access_2 = (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) ? (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR) | BIT(CSR_TSECSRD)) : (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR)); + carveout->client_access_2 = (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) ? (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR) | BIT(CSR_TSECSRD)) : (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR)); carveout->client_access_3 = 0; carveout->client_access_4 = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2)); carveout->client_force_internal_access_0 = 0; @@ -77,7 +77,7 @@ void configure_default_carveouts(void) { carveout->config = 0x4000006; /* Configure Carveout 2 (GPU UCODE) */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_600) { configure_gpu_ucode_carveout(); } @@ -99,7 +99,7 @@ void configure_default_carveouts(void) { carveout->config = 0x4401E7E; /* Configure default Kernel carveouts based on 2.0.0+. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_200) { /* Configure Carveout 4 (KERNEL_BUILTINS) */ configure_kernel_carveout(4, g_saved_carveouts[0].address, g_saved_carveouts[0].size); @@ -143,8 +143,8 @@ void configure_kernel_carveout(unsigned int carveout_id, uint64_t address, uint6 carveout->client_access_2 = (BIT(CSR_XUSB_HOSTR) | BIT(CSW_XUSB_HOSTW) | BIT(CSR_XUSB_DEVR) | BIT(CSW_XUSB_DEVW) | BIT(CSR_TSECSRD) | BIT(CSW_TSECSWR)); carveout->client_access_3 = (BIT(CSR_SDMMCRA) | BIT(CSR_SDMMCRAA) | BIT(CSR_SDMMCRAB) | BIT(CSW_SDMMCWA) | BIT(CSW_SDMMCWAA) | BIT(CSW_SDMMCWAB) | BIT(CSR_VICSRD) | BIT(CSW_VICSWR) | BIT(CSR_DISPLAYD) | BIT(CSR_NVDECSRD) | BIT(CSW_NVDECSWR) | BIT(CSR_APER) | BIT(CSW_APEW) | BIT(CSR_NVJPGSRD) | BIT(CSW_NVJPGSWR)); carveout->client_access_4 = (BIT(CSR_SESRD) | BIT(CSW_SESWR)); - carveout->client_force_internal_access_0 = ((exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSR_AVPCARM7R) : 0; - carveout->client_force_internal_access_1 = ((exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSW_AVPCARM7W) : 0; + carveout->client_force_internal_access_0 = ((exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSR_AVPCARM7R) : 0; + carveout->client_force_internal_access_1 = ((exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) && (carveout_id == 4)) ? BIT(CSW_AVPCARM7W) : 0; carveout->client_force_internal_access_2 = 0; carveout->client_force_internal_access_3 = 0; carveout->client_force_internal_access_4 = 0; diff --git a/exosphere/src/package2.c b/exosphere/src/package2.c index c4bed0142..80d3c1180 100644 --- a/exosphere/src/package2.c +++ b/exosphere/src/package2.c @@ -133,7 +133,7 @@ static void setup_se(void) { set_rsa_keyslot_flags(i, 0x41); } - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_620 && exosphere_should_perform_620_keygen()) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_620 && exosphere_should_perform_620_keygen()) { /* Start by generating device keys. */ se_aes_ecb_decrypt_block(KEYSLOT_SWITCH_6XTSECKEY, work_buffer, 0x10, keyblob_key_seed_00, 0x10); decrypt_data_into_keyslot(KEYSLOT_SWITCH_4XOLDDEVICEKEY, KEYSLOT_SWITCH_6XSBK, work_buffer, 0x10); @@ -152,16 +152,16 @@ static void setup_se(void) { /* Derive new device keys. */ switch (exosphere_get_target_firmware()) { - case EXOSPHERE_TARGET_FIRMWARE_100: - case EXOSPHERE_TARGET_FIRMWARE_200: - case EXOSPHERE_TARGET_FIRMWARE_300: + case ATMOSPHERE_TARGET_FIRMWARE_100: + case ATMOSPHERE_TARGET_FIRMWARE_200: + case ATMOSPHERE_TARGET_FIRMWARE_300: break; - case EXOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_400: derive_new_device_keys(KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY); break; - case EXOSPHERE_TARGET_FIRMWARE_500: - case EXOSPHERE_TARGET_FIRMWARE_600: - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_620: derive_new_device_keys(KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY); break; } @@ -188,7 +188,7 @@ static void setup_boot_config(void) { bootconfig_clear(); } else { void *bootconfig_ptr = NX_BOOTLOADER_BOOTCONFIG_POINTER; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) { bootconfig_ptr = NX_BOOTLOADER_BOOTCONFIG_POINTER_6X; } flush_dcache_range((uint8_t *)bootconfig_ptr, (uint8_t *)bootconfig_ptr + sizeof(bootconfig_t)); @@ -455,18 +455,18 @@ static void load_package2_sections(package2_meta_t *metadata, uint32_t master_ke static void copy_warmboot_bin_to_dram() { uint8_t *warmboot_src; switch (exosphere_get_target_firmware()) { - case EXOSPHERE_TARGET_FIRMWARE_100: - case EXOSPHERE_TARGET_FIRMWARE_200: - case EXOSPHERE_TARGET_FIRMWARE_300: + case ATMOSPHERE_TARGET_FIRMWARE_100: + case ATMOSPHERE_TARGET_FIRMWARE_200: + case ATMOSPHERE_TARGET_FIRMWARE_300: default: generic_panic(); break; - case EXOSPHERE_TARGET_FIRMWARE_400: - case EXOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_500: warmboot_src = (uint8_t *)0x4003B000; break; - case EXOSPHERE_TARGET_FIRMWARE_600: - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_620: warmboot_src = (uint8_t *)0x4003D800; break; } @@ -515,22 +515,22 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) { setup_se(); /* Perform initial PMC register writes, if relevant. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { MAKE_REG32(PMC_BASE + 0x054) = 0x8000D000; MAKE_REG32(PMC_BASE + 0x0A0) &= 0xFFF3FFFF; MAKE_REG32(PMC_BASE + 0x818) &= 0xFFFFFFFE; MAKE_REG32(PMC_BASE + 0x334) |= 0x10; switch (exosphere_get_target_firmware()) { - case EXOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_400: MAKE_REG32(PMC_BASE + 0x360) = 0x105; break; - case EXOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_500: MAKE_REG32(PMC_BASE + 0x360) = 6; break; - case EXOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_600: MAKE_REG32(PMC_BASE + 0x360) = 0x87; break; - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_620: MAKE_REG32(PMC_BASE + 0x360) = 0xA8; break; } @@ -564,7 +564,7 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) { setup_boot_config(); /* Set sysctr0 registers based on bootconfig. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { uint64_t sysctr0_val = bootconfig_get_value_for_sysctr0(); MAKE_SYSCTR0_REG(0x8) = (uint32_t)((sysctr0_val >> 0) & 0xFFFFFFFFULL); MAKE_SYSCTR0_REG(0xC) = (uint32_t)((sysctr0_val >> 32) & 0xFFFFFFFFULL); @@ -572,10 +572,10 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) { } /* Synchronize with NX BOOTLOADER. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { sync_with_nx_bootloader(NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X); copy_warmboot_bin_to_dram(); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) { setup_dram_magic_numbers(); } sync_with_nx_bootloader(NX_BOOTLOADER_STATE_LOADED_PACKAGE2_4X); @@ -628,7 +628,7 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) { } /* Synchronize with NX BOOTLOADER. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { sync_with_nx_bootloader(NX_BOOTLOADER_STATE_FINISHED_4X); setup_4x_mmio(); } else { diff --git a/exosphere/src/sc7.c b/exosphere/src/sc7.c index f168a895f..a7908c6f6 100644 --- a/exosphere/src/sc7.c +++ b/exosphere/src/sc7.c @@ -89,14 +89,14 @@ static void mitigate_jamais_vu(void) { } /* For debugging, make this check always pass. */ - if ((exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3)) { + if ((exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3)) { FLOW_CTLR_HALT_COP_EVENTS_0 = 0x50000000; } else { FLOW_CTLR_HALT_COP_EVENTS_0 = 0x40000000; } /* Jamais Vu mitigation #2: Ensure the BPMP is halted. */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400 || (get_debug_authentication_status() & 3) == 3) { /* BPMP should just be plainly halted, in debugging conditions. */ if (FLOW_CTLR_HALT_COP_EVENTS_0 != 0x50000000) { generic_panic(); @@ -166,7 +166,7 @@ static void save_tzram_state(void) { uint8_t *tzram_encryption_dst = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_ENCRYPTED_TZRAM)); uint8_t *tzram_encryption_src = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM)); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { tzram_encryption_src += 0x2000ull; } uint8_t *tzram_store_address = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_TZRAM)); @@ -203,7 +203,7 @@ static void save_tzram_state(void) { APBDEV_PMC_SEC_DISABLE8_0 = 0x550000; /* Perform pre-2.0.0 PMC writes. */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_200) { /* TODO: Give these writes appropriate defines in pmc.h */ /* Save Encrypted context location + lock scratch register. */ @@ -271,7 +271,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen notify_pmic_shutdown(); /* Validate that the shutdown has correct context. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_200) { mitigate_jamais_vu(); } @@ -279,7 +279,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen configure_pmc_for_deep_powerdown(); /* Ensure that BPMP SC7 firmware is active. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_200) { setup_bpmp_sc7_firmware(); } @@ -293,7 +293,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen /* Ensure that other cores are already asleep. */ if (!(APBDEV_PMC_PWRGATE_STATUS_0 & 0xE00)) { - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_200) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_200) { call_with_stack_pointer(get_smc_core012_stack_address(), save_se_and_power_down_cpu); } else { save_se_and_power_down_cpu(); diff --git a/exosphere/src/sealedkeys.c b/exosphere/src/sealedkeys.c index 14142b274..0d6e9ad48 100644 --- a/exosphere/src/sealedkeys.c +++ b/exosphere/src/sealedkeys.c @@ -37,7 +37,7 @@ static const uint8_t g_seal_key_sources[CRYPTOUSECASE_MAX_5X][0x10] = { }; bool usecase_is_invalid(unsigned int usecase) { - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { return usecase >= CRYPTOUSECASE_MAX_5X; } else { return usecase >= CRYPTOUSECASE_MAX; diff --git a/exosphere/src/smc_api.c b/exosphere/src/smc_api.c index 336f593cb..2cb028589 100644 --- a/exosphere/src/smc_api.c +++ b/exosphere/src/smc_api.c @@ -145,21 +145,21 @@ void set_suspend_for_debug(void) { void set_version_specific_smcs(void) { switch (exosphere_get_target_firmware()) { - case EXOSPHERE_TARGET_FIRMWARE_100: + case ATMOSPHERE_TARGET_FIRMWARE_100: /* 1.0.0 doesn't have ConfigureCarveout or ReadWriteRegister. */ g_smc_priv_table[7].handler = NULL; g_smc_priv_table[8].handler = NULL; /* 1.0.0 doesn't have UnwrapAesWrappedTitlekey. */ g_smc_user_table[0x12].handler = NULL; break; - case EXOSPHERE_TARGET_FIRMWARE_200: - case EXOSPHERE_TARGET_FIRMWARE_300: - case EXOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_200: + case ATMOSPHERE_TARGET_FIRMWARE_300: + case ATMOSPHERE_TARGET_FIRMWARE_400: /* Do nothing. */ break; - case EXOSPHERE_TARGET_FIRMWARE_500: - case EXOSPHERE_TARGET_FIRMWARE_600: - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_620: /* No more LoadSecureExpModKey. */ g_smc_user_table[0xE].handler = NULL; g_smc_user_table[0xC].id = 0xC300D60C; @@ -280,7 +280,7 @@ void call_smc_handler(uint32_t handler_id, smc_args_t *args) { #endif #if DEBUG_PANIC_ON_FAILURE - if (args->X[0] && (!is_aes_kek || args->X[3] <= EXOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG)) + if (args->X[0] && (!is_aes_kek || args->X[3] <= ATMOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG)) { MAKE_REG32(get_iram_address_for_debug() + 0x4FF0) = handler_id; MAKE_REG32(get_iram_address_for_debug() + 0x4FF4) = smc_id; @@ -594,7 +594,7 @@ uint32_t smc_read_write_register(smc_args_t *args) { } else { return 2; } - } else if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400 && MMIO_GET_DEVICE_PA(MMIO_DEVID_MC) <= address && + } else if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400 && MMIO_GET_DEVICE_PA(MMIO_DEVID_MC) <= address && address < MMIO_GET_DEVICE_PA(MMIO_DEVID_MC) + MMIO_GET_DEVICE_SIZE(MMIO_DEVID_MC)) { /* Memory Controller RW supported only on 4.0.0+ */ const uint8_t mc_whitelist[0x68] = { @@ -667,7 +667,7 @@ uint32_t smc_configure_carveout(smc_args_t *args) { } /* Configuration is one-shot, and cannot be done multiple times. */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_300) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_300) { if (g_configured_carveouts[carveout_id]) { return 2; } diff --git a/exosphere/src/smc_user.c b/exosphere/src/smc_user.c index 4ebf6369f..e042f179f 100644 --- a/exosphere/src/smc_user.c +++ b/exosphere/src/smc_user.c @@ -42,14 +42,14 @@ static uint8_t g_rsausecase_to_cryptousecase[5] = {1, 2, 3, 5, 6}; static bool is_user_keyslot_valid(unsigned int keyslot) { switch (exosphere_get_target_firmware()) { - case EXOSPHERE_TARGET_FIRMWARE_100: - case EXOSPHERE_TARGET_FIRMWARE_200: - case EXOSPHERE_TARGET_FIRMWARE_300: - case EXOSPHERE_TARGET_FIRMWARE_400: - case EXOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_100: + case ATMOSPHERE_TARGET_FIRMWARE_200: + case ATMOSPHERE_TARGET_FIRMWARE_300: + case ATMOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_500: return keyslot <= 3; - case EXOSPHERE_TARGET_FIRMWARE_600: - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_620: default: return keyslot <= 5; } @@ -157,7 +157,7 @@ uint32_t user_generate_aes_kek(smc_args_t *args) { uint8_t mask_id = (uint8_t)((packed_options >> 1) & 3); /* Switches the output based on how it will be used. */ - uint8_t usecase = (uint8_t)((packed_options >> 5) & (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500 ? 7 : 3)); + uint8_t usecase = (uint8_t)((packed_options >> 5) & (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500 ? 7 : 3)); /* Switched the output based on whether it should be console unique. */ bool is_personalized = (int)(packed_options & 1); @@ -165,7 +165,7 @@ uint32_t user_generate_aes_kek(smc_args_t *args) { bool is_recovery_boot = configitem_is_recovery_boot(); /* 5.0.0+ Bounds checking. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { if (is_personalized) { if (master_key_rev >= MASTERKEY_REVISION_MAX || (MASTERKEY_REVISION_300 <= master_key_rev && master_key_rev < MASTERKEY_REVISION_400_410)) { return 2; @@ -219,9 +219,9 @@ uint32_t user_generate_aes_kek(smc_args_t *args) { unsigned int keyslot; if (is_personalized) { /* Behavior changed in 4.0.0, and in 5.0.0. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { keyslot = devkey_get_keyslot(master_key_rev); - } else if (exosphere_get_target_firmware() == EXOSPHERE_TARGET_FIRMWARE_400) { + } else if (exosphere_get_target_firmware() == ATMOSPHERE_TARGET_FIRMWARE_400) { if (master_key_rev >= 1) { keyslot = KEYSLOT_SWITCH_DEVICEKEY; /* New device key, 4.x. */ } else { @@ -294,7 +294,7 @@ uint32_t user_crypt_aes(smc_args_t *args) { uint32_t keyslot = args->X[1] & 3; uint32_t mode = (args->X[1] >> 4) & 3; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) { keyslot = args->X[1] & 7; } @@ -310,7 +310,7 @@ uint32_t user_crypt_aes(smc_args_t *args) { return 2; } - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { /* Disallow dma lists outside of safe range. */ if (in_ll_paddr - 0x80000000 >= 0x3FF7F5) { return 2; @@ -358,7 +358,7 @@ uint32_t user_generate_specific_aes_key(smc_args_t *args) { if (master_key_rev > 0) { master_key_rev -= 1; } - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400) { master_key_rev = 0; } @@ -374,9 +374,9 @@ uint32_t user_generate_specific_aes_key(smc_args_t *args) { unsigned int keyslot; /* Behavior changed in 5.0.0. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { keyslot = devkey_get_keyslot(master_key_rev); - } else if (exosphere_get_target_firmware() == EXOSPHERE_TARGET_FIRMWARE_400) { + } else if (exosphere_get_target_firmware() == ATMOSPHERE_TARGET_FIRMWARE_400) { if (master_key_rev >= 1) { keyslot = KEYSLOT_SWITCH_DEVICEKEY; /* New device key, 4.x. */ } else { @@ -455,7 +455,7 @@ uint32_t user_load_rsa_oaep_key(smc_args_t *args) { upage_ref_t page_ref; /* This function no longer exists in 5.x+. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { generic_panic(); } @@ -504,7 +504,7 @@ uint32_t user_decrypt_rsa_private_key(smc_args_t *args) { upage_ref_t page_ref; /* This function no longer exists in 5.x+. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { generic_panic(); } @@ -562,7 +562,7 @@ uint32_t user_load_secure_exp_mod_key(smc_args_t *args) { upage_ref_t page_ref; /* This function no longer exists in 5.x+. */ - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { generic_panic(); } @@ -618,7 +618,7 @@ uint32_t user_secure_exp_mod(smc_args_t *args) { void *user_modulus = (void *)args->X[2]; unsigned int exponent_id = 1; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_500) { switch (args->X[3]) { case 0: exponent_id = 1; @@ -664,7 +664,7 @@ uint32_t user_unwrap_rsa_oaep_wrapped_titlekey(smc_args_t *args) { unsigned int option = (unsigned int)args->X[7]; unsigned int master_key_rev; unsigned int titlekey_type; - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_600) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_600) { master_key_rev = option & 0x3F; titlekey_type = (option >> 6) & 1; } else { @@ -676,7 +676,7 @@ uint32_t user_unwrap_rsa_oaep_wrapped_titlekey(smc_args_t *args) { master_key_rev -= 1; } - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_300) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_300) { if (master_key_rev >= MASTERKEY_REVISION_MAX) { return 2; } @@ -741,7 +741,7 @@ uint32_t user_unwrap_aes_wrapped_titlekey(smc_args_t *args) { if (master_key_rev > 0) { master_key_rev -= 1; } - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_300) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_300) { if (master_key_rev >= MASTERKEY_REVISION_MAX) { return 2; } @@ -837,7 +837,7 @@ uint32_t user_decrypt_or_import_rsa_key(smc_args_t *args) { upage_ref_t page_ref; /* This function only exists in 5.x+. */ - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_500) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_500) { generic_panic(); } diff --git a/exosphere/src/titlekey.c b/exosphere/src/titlekey.c index b5a35b6f5..3e0e5907a 100644 --- a/exosphere/src/titlekey.c +++ b/exosphere/src/titlekey.c @@ -44,7 +44,7 @@ void tkey_set_master_key_rev(unsigned int master_key_rev) { } static void tkey_validate_type(unsigned int type) { - if (type > TITLEKEY_TYPE_MAX || (type > 0 && exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_600)) { + if (type > TITLEKEY_TYPE_MAX || (type > 0 && exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_600)) { generic_panic(); } } diff --git a/exosphere/src/warmboot_init.c b/exosphere/src/warmboot_init.c index 6a22294a4..2422b03ba 100644 --- a/exosphere/src/warmboot_init.c +++ b/exosphere/src/warmboot_init.c @@ -25,7 +25,7 @@ #undef MC_BASE #define MC_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_MC)) -#define WARMBOOT_GET_TZRAM_SEGMENT_PA(x) ((g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) \ +#define WARMBOOT_GET_TZRAM_SEGMENT_PA(x) ((g_exosphere_target_firmware_for_init < ATMOSPHERE_TARGET_FIRMWARE_500) \ ? TZRAM_GET_SEGMENT_PA(x) : TZRAM_GET_SEGMENT_5X_PA(x)) /* start.s */ @@ -53,7 +53,7 @@ void warmboot_crt0_critical_section_enter(volatile critical_section_t *critical_ } void init_dma_controllers(unsigned int target_firmware) { - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400) { /* Set some unknown registers in HOST1X. */ MAKE_REG32(0x500038F8) &= 0xFFFFFFFE; MAKE_REG32(0x50003300) = 0; @@ -205,7 +205,7 @@ void warmboot_init(void) { /*identity_remap_tzram();*/ /* Nintendo pointlessly fully invalidate the TLB & invalidate the data cache on the modified ranges here */ - if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { + if (g_exosphere_target_firmware_for_init < ATMOSPHERE_TARGET_FIRMWARE_500) { set_memory_registers_enable_mmu_1x_ttbr0(); } else { set_memory_registers_enable_mmu_5x_ttbr0(); diff --git a/exosphere/src/warmboot_main.c b/exosphere/src/warmboot_main.c index d6f66aeb3..b782a61e9 100644 --- a/exosphere/src/warmboot_main.c +++ b/exosphere/src/warmboot_main.c @@ -79,7 +79,7 @@ void __attribute__((noreturn)) warmboot_main(void) { /* Make PMC (2.x+), MC (4.x+) registers secure-only */ secure_additional_devices(); - if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400 || configitem_get_hardware_type() == 0) { + if (exosphere_get_target_firmware() < ATMOSPHERE_TARGET_FIRMWARE_400 || configitem_get_hardware_type() == 0) { /* Enable input to I2C1 */ PINMUX_AUX_GEN1_I2C_SCL_0 = 0x40; PINMUX_AUX_GEN1_I2C_SDA_0 = 0x40; @@ -92,7 +92,7 @@ void __attribute__((noreturn)) warmboot_main(void) { clear_user_smc_in_progress(); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) { + if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) { setup_4x_mmio(); } } diff --git a/fusee/fusee-secondary/src/exocfg.h b/fusee/fusee-secondary/src/exocfg.h index d21abb4f9..55c8d12c5 100644 --- a/fusee/fusee-secondary/src/exocfg.h +++ b/fusee/fusee-secondary/src/exocfg.h @@ -17,6 +17,8 @@ #ifndef FUSEE_EXOSPHERE_CONFIG_H #define FUSEE_EXOSPHERE_CONFIG_H +#include + /* This serves to set configuration for *exosphere itself*, separate from the SecMon Exosphere mimics. */ /* "XBC0" */ @@ -24,16 +26,6 @@ /* "XBC1" */ #define MAGIC_EXOSPHERE_BOOTCONFIG (0x31434258) -#define EXOSPHERE_TARGET_FIRMWARE_100 1 -#define EXOSPHERE_TARGET_FIRMWARE_200 2 -#define EXOSPHERE_TARGET_FIRMWARE_300 3 -#define EXOSPHERE_TARGET_FIRMWARE_400 4 -#define EXOSPHERE_TARGET_FIRMWARE_500 5 -#define EXOSPHERE_TARGET_FIRMWARE_600 6 -#define EXOSPHERE_TARGET_FIRMWARE_620 7 - -#define EXOSPHERE_TARGET_FIRMWARE_MIN EXOSPHERE_TARGET_FIRMWARE_100 -#define EXOSPHERE_TARGET_FIRMWARE_MAX EXOSPHERE_TARGET_FIRMWARE_620 #define EXOSPHERE_FLAGS_DEFAULT 0x00000000 #define EXOSPHERE_FLAG_PERFORM_620_KEYGEN (1 << 0u) diff --git a/fusee/fusee-secondary/src/key_derivation.c b/fusee/fusee-secondary/src/key_derivation.c index 0daab0f38..3b934f59c 100644 --- a/fusee/fusee-secondary/src/key_derivation.c +++ b/fusee/fusee-secondary/src/key_derivation.c @@ -141,7 +141,7 @@ int derive_nx_keydata(uint32_t target_firmware, const nx_keyblob_t *keyblobs, ui } /* Do 6.2.0+ keygen. */ - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_620) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_620) { if (memcmp(tsec_root_key, zeroes, 0x10) != 0) { /* We got a valid key from emulation. */ set_aes_keyslot(0xC, tsec_root_key, 0x10); @@ -185,27 +185,27 @@ int derive_nx_keydata(uint32_t target_firmware, const nx_keyblob_t *keyblobs, ui set_aes_keyslot(0xC, g_dec_keyblobs[available_revision].master_kek, 0x10); /* Also set the Package1 key for the revision that is stored on the eMMC boot0 partition. */ - if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_620) { + if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_620) { load_package1_key(available_revision); } /* Derive keys for Exosphere, lock critical keyslots. */ switch (target_firmware) { - case EXOSPHERE_TARGET_FIRMWARE_100: - case EXOSPHERE_TARGET_FIRMWARE_200: - case EXOSPHERE_TARGET_FIRMWARE_300: + case ATMOSPHERE_TARGET_FIRMWARE_100: + case ATMOSPHERE_TARGET_FIRMWARE_200: + case ATMOSPHERE_TARGET_FIRMWARE_300: decrypt_data_into_keyslot(0xD, 0xF, devicekey_seed, 0x10); decrypt_data_into_keyslot(0xC, 0xC, masterkey_seed, 0x10); break; - case EXOSPHERE_TARGET_FIRMWARE_400: + case ATMOSPHERE_TARGET_FIRMWARE_400: decrypt_data_into_keyslot(0xD, 0xF, devicekey_4x_seed, 0x10); decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10); decrypt_data_into_keyslot(0xE, 0xC, masterkey_4x_seed, 0x10); decrypt_data_into_keyslot(0xC, 0xC, masterkey_seed, 0x10); break; - case EXOSPHERE_TARGET_FIRMWARE_500: - case EXOSPHERE_TARGET_FIRMWARE_600: - case EXOSPHERE_TARGET_FIRMWARE_620: + case ATMOSPHERE_TARGET_FIRMWARE_500: + case ATMOSPHERE_TARGET_FIRMWARE_600: + case ATMOSPHERE_TARGET_FIRMWARE_620: decrypt_data_into_keyslot(0xA, 0xF, devicekey_4x_seed, 0x10); decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10); decrypt_data_into_keyslot(0xE, 0xC, masterkey_4x_seed, 0x10); @@ -222,11 +222,11 @@ int derive_nx_keydata(uint32_t target_firmware, const nx_keyblob_t *keyblobs, ui /* Sets final keyslot flags, for handover to TZ/Exosphere. Setting these will prevent the BPMP from using the device key or master key. */ void finalize_nx_keydata(uint32_t target_firmware) { set_aes_keyslot_flags(0xC, 0xFF); - set_aes_keyslot_flags((target_firmware >= EXOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY), 0xFF); + set_aes_keyslot_flags((target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY), 0xFF); } static void generate_specific_aes_key(void *dst, const void *wrapped_key, bool should_mask, uint32_t target_firmware) { - unsigned int keyslot = (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY); + unsigned int keyslot = (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY); if (fuse_get_bootrom_patch_version() < 0x7F) { /* On dev units, use a fixed "all-zeroes" seed. */ /* Yes, this data really is all-zero in actual TrustZone .rodata. */ @@ -257,7 +257,7 @@ static void generate_personalized_aes_key_for_bis(void *dst, const void *wrapped 0x89, 0x61, 0x5E, 0xE0, 0x5C, 0x31, 0xB6, 0x80, 0x5F, 0xE5, 0x8F, 0x3D, 0xA2, 0x4F, 0x7A, 0xA8 }; - unsigned int keyslot = (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY); + unsigned int keyslot = (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400) ? (KEYSLOT_SWITCH_4XOLDDEVICEKEY) : (KEYSLOT_SWITCH_DEVICEKEY); /* Derive kek. */ decrypt_data_into_keyslot(KEYSLOT_SWITCH_TEMPKEY, keyslot, kek_source, 0x10); decrypt_data_into_keyslot(KEYSLOT_SWITCH_TEMPKEY, KEYSLOT_SWITCH_TEMPKEY, wrapped_kek, 0x10); diff --git a/fusee/fusee-secondary/src/nxboot.c b/fusee/fusee-secondary/src/nxboot.c index e023e23fa..37e4d293c 100644 --- a/fusee/fusee-secondary/src/nxboot.c +++ b/fusee/fusee-secondary/src/nxboot.c @@ -106,20 +106,20 @@ static uint32_t nxboot_get_target_firmware(const void *package1loader) { const package1loader_header_t *package1loader_header = (const package1loader_header_t *)package1loader; switch (package1loader_header->version) { case 0x01: /* 1.0.0 */ - return EXOSPHERE_TARGET_FIRMWARE_100; + return ATMOSPHERE_TARGET_FIRMWARE_100; case 0x02: /* 2.0.0 - 2.3.0 */ - return EXOSPHERE_TARGET_FIRMWARE_200; + return ATMOSPHERE_TARGET_FIRMWARE_200; case 0x04: /* 3.0.0 and 3.0.1 - 3.0.2 */ - return EXOSPHERE_TARGET_FIRMWARE_300; + return ATMOSPHERE_TARGET_FIRMWARE_300; case 0x07: /* 4.0.0 - 4.1.0 */ - return EXOSPHERE_TARGET_FIRMWARE_400; + return ATMOSPHERE_TARGET_FIRMWARE_400; case 0x0B: /* 5.0.0 - 5.1.0 */ - return EXOSPHERE_TARGET_FIRMWARE_500; + return ATMOSPHERE_TARGET_FIRMWARE_500; case 0x0E: { /* 6.0.0 - 6.2.0 */ if (memcmp(package1loader_header->build_timestamp, "20180802", 8) == 0) { - return EXOSPHERE_TARGET_FIRMWARE_600; + return ATMOSPHERE_TARGET_FIRMWARE_600; } else if (memcmp(package1loader_header->build_timestamp, "20181107", 8) == 0) { - return EXOSPHERE_TARGET_FIRMWARE_620; + return ATMOSPHERE_TARGET_FIRMWARE_620; } else { fatal_error("[NXBOOT]: Unable to identify package1!\n"); } @@ -144,7 +144,7 @@ static void nxboot_configure_exosphere(uint32_t target_firmware, unsigned int ke fatal_error("[NXBOOT]: Failed to parse BCT.ini!\n"); } - if ((exo_cfg.target_firmware < EXOSPHERE_TARGET_FIRMWARE_MIN) || (exo_cfg.target_firmware > EXOSPHERE_TARGET_FIRMWARE_MAX)) { + if ((exo_cfg.target_firmware < ATMOSPHERE_TARGET_FIRMWARE_MIN) || (exo_cfg.target_firmware > ATMOSPHERE_TARGET_FIRMWARE_MAX)) { fatal_error("[NXBOOT]: Invalid Exosphere target firmware!\n"); } @@ -164,7 +164,7 @@ static void nxboot_configure_stratosphere(uint32_t target_firmware) { } } else { /* Check if fuses are < 4.0.0, but firmware is >= 4.0.0 */ - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_400 && !(fuse_get_reserved_odm(7) & ~0x0000000F)) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_400 && !(fuse_get_reserved_odm(7) & ~0x0000000F)) { kip_patches_set_enable_nogc(); } } @@ -252,8 +252,8 @@ static void nxboot_move_bootconfig() { fclose(bcfile); /* Select the actual BootConfig size and destination address. */ - bootconfig_addr = (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_600) ? 0x4003D000 : 0x4003F800; - bootconfig_size = (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) ? 0x3000 : 0x1000; + bootconfig_addr = (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_600) ? 0x4003D000 : 0x4003F800; + bootconfig_size = (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) ? 0x3000 : 0x1000; /* Copy the BootConfig into IRAM. */ memset((void *)bootconfig_addr, 0, bootconfig_size); @@ -360,7 +360,7 @@ uint32_t nxboot_main(void) { if (!package1_get_tsec_fw(&tsec_fw, package1loader, package1loader_size)) { fatal_error("[NXBOOT]: Failed to read the TSEC firmware from Package1loader!\n"); } - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_620) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_620) { tsec_fw_size = 0x2900; } else { tsec_fw_size = 0xF00; @@ -372,7 +372,7 @@ uint32_t nxboot_main(void) { /* Get the TSEC keys. */ uint8_t tsec_key[0x10] = {0}; uint8_t tsec_root_key[0x10] = {0}; - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_620) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_620) { uint8_t tsec_keys[0x20] = {0}; /* Emulate the TSEC payload on 6.2.0+. */ @@ -398,7 +398,7 @@ uint32_t nxboot_main(void) { nxboot_configure_exosphere(target_firmware, keygen_type); /* Initialize Boot Reason on older firmware versions. */ - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT]: Initializing Boot Reason...\n"); nxboot_set_bootreason(); } @@ -420,7 +420,7 @@ uint32_t nxboot_main(void) { fatal_error("[NXBOOT]: Could not read the warmboot firmware from %s!\n", loader_ctx->warmboot_path); } } else { - if (target_firmware >= EXOSPHERE_TARGET_FIRMWARE_620) { + if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_620) { /* Package1 was decrypted during TSEC emulation. */ const uint8_t *package1_hdr = (const uint8_t *)package1loader + 0x7000 - 0x20; package1 = (package1_header_t *)(package1_hdr + 0x20); @@ -446,9 +446,9 @@ uint32_t nxboot_main(void) { } /* Select the right address for the warmboot firmware. */ - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { warmboot_memaddr = (void *)0x8000D000; - } else if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_600) { + } else if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_600) { warmboot_memaddr = (void *)0x4003B000; } else { warmboot_memaddr = (void *)0x4003D800; @@ -459,7 +459,7 @@ uint32_t nxboot_main(void) { /* Copy the warmboot firmware and set the address in PMC if necessary. */ if (warmboot_fw && (warmboot_fw_size > 0)) { memcpy(warmboot_memaddr, warmboot_fw, warmboot_fw_size); - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) pmc->scratch1 = (uint32_t)warmboot_memaddr; } @@ -474,7 +474,7 @@ uint32_t nxboot_main(void) { print(SCREEN_LOG_LEVEL_INFO, u8"[NXBOOT]: Reading Exosphère...\n"); /* Select the right address for Exosphère. */ - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { exosphere_memaddr = (void *)0x4002D000; } else { exosphere_memaddr = (void *)0x4002B000; @@ -502,7 +502,7 @@ uint32_t nxboot_main(void) { nxboot_move_bootconfig(); /* Set 3.0.0/3.0.1/3.0.2 warmboot security check. */ - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware == EXOSPHERE_TARGET_FIRMWARE_300) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware == ATMOSPHERE_TARGET_FIRMWARE_300) { const package1loader_header_t *package1loader_header = (const package1loader_header_t *)package1loader; if (!strcmp(package1loader_header->build_timestamp, "20170519101410")) pmc->secure_scratch32 = 0xE3; /* Warmboot 3.0.0 security check.*/ diff --git a/fusee/fusee-secondary/src/nxboot_iram.c b/fusee/fusee-secondary/src/nxboot_iram.c index 86466a072..0705af10d 100644 --- a/fusee/fusee-secondary/src/nxboot_iram.c +++ b/fusee/fusee-secondary/src/nxboot_iram.c @@ -36,7 +36,7 @@ void nxboot_finish(uint32_t boot_memaddr) { /* Lock keyslots. */ set_aes_keyslot_flags(KEYSLOT_SWITCH_MASTERKEY, 0xFF); - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { set_aes_keyslot_flags(KEYSLOT_SWITCH_DEVICEKEY, 0xFF); } else { set_aes_keyslot_flags(KEYSLOT_SWITCH_4XOLDDEVICEKEY, 0xFF); @@ -62,7 +62,7 @@ void nxboot_finish(uint32_t boot_memaddr) { /* Boot up Exosphère. */ MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE = 0; - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2; } else { MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X; @@ -93,7 +93,7 @@ void nxboot_finish(uint32_t boot_memaddr) { } /* Signal Exosphère. */ - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) { MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED; } else { MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED_4X; diff --git a/fusee/fusee-secondary/src/stratosphere.c b/fusee/fusee-secondary/src/stratosphere.c index 2a07e1ff0..acdaa7e89 100644 --- a/fusee/fusee-secondary/src/stratosphere.c +++ b/fusee/fusee-secondary/src/stratosphere.c @@ -62,7 +62,7 @@ ini1_header_t *stratosphere_get_ini1(uint32_t target_firmware) { return g_stratosphere_ini1; } - if (target_firmware <= EXOSPHERE_TARGET_FIRMWARE_100) { + if (target_firmware <= ATMOSPHERE_TARGET_FIRMWARE_100) { boot_kip = boot_100_kip; boot_kip_size = boot_100_kip_size; } else {