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kern: update ChangePermissions to use new iteration logic
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parent
d2656e3948
commit
e1e84d4450
@ -245,7 +245,6 @@ namespace ams::kern::arch::arm64 {
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static ALWAYS_INLINE void ClearPageTable(KVirtualAddress table) {
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cpu::ClearPageToZero(GetVoidPointer(table));
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cpu::DataSynchronizationBarrierInnerShareable();
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}
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ALWAYS_INLINE void OnTableUpdated() const {
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@ -293,6 +293,10 @@ namespace ams::kern::arch::arm64 {
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switch (operation) {
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case OperationType_Map:
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/* If mapping io or uncached pages, ensure that there is no pending reschedule. */
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if (properties.io || properties.uncached) {
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KScopedSchedulerLock sl;
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}
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R_RETURN(this->MapContiguous(virt_addr, phys_addr, num_pages, entry_template, properties.disable_merge_attributes == DisableMergeAttribute_DisableHead, page_list, reuse_ll));
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case OperationType_ChangePermissions:
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R_RETURN(this->ChangePermissions(virt_addr, num_pages, entry_template, properties.disable_merge_attributes, false, false, page_list, reuse_ll));
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@ -317,6 +321,10 @@ namespace ams::kern::arch::arm64 {
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switch (operation) {
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case OperationType_MapGroup:
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case OperationType_MapFirstGroup:
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/* If mapping io or uncached pages, ensure that there is no pending reschedule. */
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if (properties.io || properties.uncached) {
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KScopedSchedulerLock sl;
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}
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R_RETURN(this->MapGroup(virt_addr, page_group, num_pages, entry_template, properties.disable_merge_attributes == DisableMergeAttribute_DisableHead, operation != OperationType_MapFirstGroup, page_list, reuse_ll));
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MESOSPHERE_UNREACHABLE_DEFAULT_CASE();
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}
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@ -900,6 +908,9 @@ namespace ams::kern::arch::arm64 {
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Result KPageTable::ChangePermissions(KProcessAddress virt_addr, size_t num_pages, PageTableEntry entry_template, DisableMergeAttribute disable_merge_attr, bool refresh_mapping, bool flush_mapping, PageLinkedList *page_list, bool reuse_ll) {
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MESOSPHERE_ASSERT(this->IsLockedByCurrentThread());
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/* Ensure there are no pending data writes. */
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cpu::DataSynchronizationBarrier();
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/* Separate pages before we change permissions. */
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R_TRY(this->SeparatePages(virt_addr, num_pages, page_list, reuse_ll));
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@ -990,59 +1001,15 @@ namespace ams::kern::arch::arm64 {
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}
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/* Apply the entry template. */
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L1PageTableEntry *l1_entry = impl.GetL1Entry(cur_virt_addr);
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switch (next_entry.block_size) {
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case L1BlockSize:
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{
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/* Write the updated entry. */
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*l1_entry = L1PageTableEntry(PageTableEntry::BlockTag{}, next_entry.phys_addr, entry_template, sw_reserved_bits, false);
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}
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break;
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case L2ContiguousBlockSize:
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case L2BlockSize:
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{
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/* Get the number of L2 blocks. */
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const size_t num_l2_blocks = next_entry.block_size / L2BlockSize;
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{
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const size_t num_entries = context.is_contiguous ? BlocksPerContiguousBlock : 1;
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/* Get the L2 entry. */
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KPhysicalAddress l2_phys = Null<KPhysicalAddress>;
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MESOSPHERE_ABORT_UNLESS(l1_entry->GetTable(l2_phys));
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const KVirtualAddress l2_virt = GetPageTableVirtualAddress(l2_phys);
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/* Write the updated entry. */
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const bool contig = next_entry.block_size == L2ContiguousBlockSize;
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for (size_t i = 0; i < num_l2_blocks; i++) {
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*impl.GetL2EntryFromTable(l2_virt, cur_virt_addr + L2BlockSize * i) = L2PageTableEntry(PageTableEntry::BlockTag{}, next_entry.phys_addr + L2BlockSize * i, entry_template, sw_reserved_bits, contig);
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sw_reserved_bits &= ~(PageTableEntry::SoftwareReservedBit_DisableMergeHead);
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}
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}
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break;
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case L3ContiguousBlockSize:
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case L3BlockSize:
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{
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/* Get the number of L3 blocks. */
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const size_t num_l3_blocks = next_entry.block_size / L3BlockSize;
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/* Get the L2 entry. */
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KPhysicalAddress l2_phys = Null<KPhysicalAddress>;
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MESOSPHERE_ABORT_UNLESS(l1_entry->GetTable(l2_phys));
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const KVirtualAddress l2_virt = GetPageTableVirtualAddress(l2_phys);
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L2PageTableEntry *l2_entry = impl.GetL2EntryFromTable(l2_virt, cur_virt_addr);
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/* Get the L3 entry. */
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KPhysicalAddress l3_phys = Null<KPhysicalAddress>;
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MESOSPHERE_ABORT_UNLESS(l2_entry->GetTable(l3_phys));
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const KVirtualAddress l3_virt = GetPageTableVirtualAddress(l3_phys);
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/* Write the updated entry. */
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const bool contig = next_entry.block_size == L3ContiguousBlockSize;
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for (size_t i = 0; i < num_l3_blocks; i++) {
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*impl.GetL3EntryFromTable(l3_virt, cur_virt_addr + L3BlockSize * i) = L3PageTableEntry(PageTableEntry::BlockTag{}, next_entry.phys_addr + L3BlockSize * i, entry_template, sw_reserved_bits, contig);
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sw_reserved_bits &= ~(PageTableEntry::SoftwareReservedBit_DisableMergeHead);
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}
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}
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break;
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MESOSPHERE_UNREACHABLE_DEFAULT_CASE();
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auto * const pte = context.level_entries[context.level];
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const size_t block_size = impl.GetBlockSize(context.level);
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for (size_t i = 0; i < num_entries; ++i) {
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pte[i] = PageTableEntry(PageTableEntry::BlockTag{}, next_entry.phys_addr + i * block_size, entry_template, sw_reserved_bits, context.is_contiguous, context.level == KPageTableImpl::EntryLevel_L3);
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sw_reserved_bits &= ~(PageTableEntry::SoftwareReservedBit_DisableMergeHead);
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}
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}
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/* If our option asks us to, try to merge mappings. */
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