mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-12-15 01:01:26 +01:00
264 lines
8.8 KiB
C
264 lines
8.8 KiB
C
/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <vapours/ams_version.h>
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#include "car.h"
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#include "fuse.h"
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#include "pmc.h"
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#include "timers.h"
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/* Prototypes for internal commands. */
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void fuse_enable_power(void);
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void fuse_disable_power(void);
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void fuse_wait_idle(void);
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/* Initialize the fuse driver */
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void fuse_init(void) {
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/* Make all fuse registers visible, disable the private key and disable programming. */
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clkrst_enable_fuse_regs(true);
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fuse_disable_private_key();
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fuse_disable_programming();
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}
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/* Disable access to the private key and set the TZ sticky bit. */
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void fuse_disable_private_key(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
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}
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/* Disables all fuse programming. */
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void fuse_disable_programming(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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fuse->FUSE_DISABLEREGPROGRAM = 1;
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}
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/* Enable power to the fuse hardware array. */
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void fuse_enable_power(void) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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pmc->fuse_control &= ~(0x200); // Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR.
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mdelay(1);
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pmc->fuse_control |= 0x100; // Set PMC_FUSE_CTRL_PS18_LATCH_SET.
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mdelay(1);
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}
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/* Disable power to the fuse hardware array. */
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void fuse_disable_power(void) {
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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pmc->fuse_control &= ~(0x100); // Clear PMC_FUSE_CTRL_PS18_LATCH_SET.
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mdelay(1);
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pmc->fuse_control |= 0x200; // Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR.
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mdelay(1);
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}
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/* Wait for the fuse driver to go idle. */
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void fuse_wait_idle(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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uint32_t ctrl_val = 0;
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/* Wait for STATE_IDLE */
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while ((ctrl_val & (0xF0000)) != 0x40000)
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ctrl_val = fuse->FUSE_FUSECTRL;
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}
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/* Read a fuse from the hardware array. */
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uint32_t fuse_hw_read(uint32_t addr) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Program the target address. */
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fuse->FUSE_FUSEADDR = addr;
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/* Enable read operation in control register. */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x1; /* Set READ command. */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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return fuse->FUSE_FUSERDATA;
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}
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/* Write a fuse in the hardware array. */
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void fuse_hw_write(uint32_t value, uint32_t addr) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Program the target address and value. */
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fuse->FUSE_FUSEADDR = addr;
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fuse->FUSE_FUSEWDATA = value;
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/* Enable write operation in control register. */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x2; /* Set WRITE command. */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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}
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/* Sense the fuse hardware array into the shadow cache. */
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void fuse_hw_sense(void) {
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volatile tegra_fuse_t *fuse = fuse_get_regs();
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/* Wait for idle state. */
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fuse_wait_idle();
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/* Enable sense operation in control register */
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uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x3; /* Set SENSE_CTRL command */
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fuse->FUSE_FUSECTRL = ctrl_val;
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/* Wait for idle state. */
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fuse_wait_idle();
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}
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/* Read the SKU info register from the shadow cache. */
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uint32_t fuse_get_sku_info(void) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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return fuse_chip->FUSE_SKU_INFO;
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}
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/* Read the bootrom patch version from a register in the shadow cache. */
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uint32_t fuse_get_bootrom_patch_version(void) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
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}
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/* Read a spare bit register from the shadow cache */
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uint32_t fuse_get_spare_bit(uint32_t idx) {
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if (idx < 32) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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return fuse_chip->FUSE_SPARE_BIT[idx];
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} else {
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return 0;
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}
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}
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/* Read a reserved ODM register from the shadow cache. */
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uint32_t fuse_get_reserved_odm(uint32_t idx) {
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if (idx < 8) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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return fuse_chip->FUSE_RESERVED_ODM[idx];
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} else {
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return 0;
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}
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}
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/* Get the DRAM ID using values in the shadow cache. */
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uint32_t fuse_get_dram_id(void) {
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return ((fuse_get_reserved_odm(4) >> 3) & 0x7);
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}
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/* Derive the Device ID using values in the shadow cache. */
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uint64_t fuse_get_device_id(void) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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uint64_t device_id = 0;
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uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
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uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
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uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
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uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
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uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
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uint64_t derived_lot_code = 0;
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for (unsigned int i = 0; i < 5; i++) {
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derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
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}
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derived_lot_code &= 0x03FFFFFF;
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device_id |= y_coord << 0;
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device_id |= x_coord << 9;
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device_id |= wafer_id << 18;
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device_id |= derived_lot_code << 24;
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device_id |= fab_code << 50;
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return device_id;
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}
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/* Derive the Hardware Type using values in the shadow cache. */
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uint32_t fuse_get_hardware_type(uint32_t target_firmware) {
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uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
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uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
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/* Firmware from versions 1.0.0 to 3.0.2. */
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if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_400) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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if (hardware_type >= 1) {
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return (hardware_type > 2) ? 3 : hardware_type - 1;
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} else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) {
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return 0;
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} else {
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return 3;
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}
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} else if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_700) { /* Firmware versions from 4.0.0 to 6.2.0. */
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static const uint32_t types[] = {0,1,4,3};
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hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
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hardware_type--;
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return (hardware_type > 3) ? 4 : types[hardware_type];
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} else { /* Firmware versions from 7.0.0 onwards. */
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/* Always return 0 in retail. */
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return 0;
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}
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}
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/* Derive the Retail Type using values in the shadow cache. */
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uint32_t fuse_get_retail_type(void) {
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/* Retail Type = IS_RETAIL | UNIT_TYPE. */
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uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
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uint32_t retail_type = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
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if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */
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return 1;
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} else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */
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return 0;
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}
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return 2; /* IS_RETAIL | DEV_UNIT */
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}
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/* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */
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void fuse_get_hardware_info(void *dst) {
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volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
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uint32_t hw_info[0x4];
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uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
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uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
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uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
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uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
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uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
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uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
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uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
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uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
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/* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
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hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
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hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
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hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
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hw_info[3] = (uint32_t)(vendor_code);
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memcpy(dst, hw_info, 0x10);
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}
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