mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-24 07:40:26 +01:00
654 lines
32 KiB
C++
654 lines
32 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "fusee_registers_di.hpp"
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#include "fusee_display.hpp"
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#include "fusee_print.hpp"
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#include "fusee_fatal.hpp"
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namespace ams::nxboot {
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namespace {
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#include "fusee_display_config.inc"
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}
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namespace {
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/* Helpful defines. */
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constexpr int DsiWaitForCommandMilliSecondsMax = 250;
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constexpr int DsiWaitForCommandCompletionMilliSeconds = 5;
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constexpr int DsiWaitForHostControlMilliSecondsMax = 150;
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constexpr inline int I2cAddressMax77620Pmic = 0x3C;
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constexpr size_t GPIO_PORT3_CNF_0 = 0x200;
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constexpr size_t GPIO_PORT3_OE_0 = 0x210;
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constexpr size_t GPIO_PORT3_OUT_0 = 0x220;
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constexpr size_t GPIO_PORT6_CNF_1 = 0x504;
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constexpr size_t GPIO_PORT6_OE_1 = 0x514;
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constexpr size_t GPIO_PORT6_OUT_1 = 0x524;
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/* Globals. */
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constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc .GetAddress();
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constexpr inline const uintptr_t g_disp1_regs = secmon::MemoryRegionPhysicalDeviceDisp1 .GetAddress();
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constexpr inline const uintptr_t g_dsi_regs = secmon::MemoryRegionPhysicalDeviceDsi .GetAddress();
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constexpr inline const uintptr_t g_clk_rst_regs = secmon::MemoryRegionPhysicalDeviceClkRst .GetAddress();
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constexpr inline const uintptr_t g_gpio_regs = secmon::MemoryRegionPhysicalDeviceGpio .GetAddress();
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constexpr inline const uintptr_t g_apb_misc_regs = secmon::MemoryRegionPhysicalDeviceApbMisc.GetAddress();
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constexpr inline const uintptr_t g_mipi_cal_regs = secmon::MemoryRegionPhysicalDeviceMipiCal.GetAddress();
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constinit u32 *g_frame_buffer = nullptr;
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constinit u32 g_lcd_vendor = 0;
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constinit bool g_display_initialized = false;
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inline void DoRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes, size_t num_writes) {
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for (size_t i = 0; i < num_writes; i++) {
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reg::Write(base_address + reg_writes[i].offset, reg_writes[i].value);
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}
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}
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inline void DoSocDependentRegisterWrites(uintptr_t base_address, const RegisterWrite *reg_writes_erista, size_t num_writes_erista, const RegisterWrite *reg_writes_mariko, size_t num_writes_mariko) {
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switch (fuse::GetSocType()) {
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case fuse::SocType_Erista: DoRegisterWrites(base_address, reg_writes_erista, num_writes_erista); break;
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case fuse::SocType_Mariko: DoRegisterWrites(base_address, reg_writes_mariko, num_writes_mariko); break;
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AMS_UNREACHABLE_DEFAULT_CASE();
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}
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}
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inline void DoSleepOrRegisterWrites(uintptr_t base_address, const SleepOrRegisterWrite *reg_writes, size_t num_writes) {
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for (size_t i = 0; i < num_writes; i++) {
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switch (reg_writes[i].kind) {
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case SleepOrRegisterWriteKind_Write:
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reg::Write(base_address + sizeof(u32) * reg_writes[i].offset, reg_writes[i].value);
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break;
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case SleepOrRegisterWriteKind_Sleep:
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util::WaitMicroSeconds(reg_writes[i].offset * UINT64_C(1000));
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break;
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AMS_UNREACHABLE_DEFAULT_CASE();
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}
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}
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}
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void WaitDsiTrigger() {
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const u32 timeout = util::GetMicroSeconds() + (DsiWaitForCommandMilliSecondsMax * 1000u);
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while (true) {
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if (util::GetMicroSeconds() >= timeout) {
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break;
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}
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if (reg::Read(g_dsi_regs + sizeof(u32) * DSI_TRIGGER) == 0) {
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break;
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}
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}
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util::WaitMicroSeconds(DsiWaitForCommandCompletionMilliSeconds * 1000u);
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}
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void WaitDsiHostControl() {
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const u32 timeout = util::GetMicroSeconds() + (DsiWaitForHostControlMilliSecondsMax * 1000u);
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while (true) {
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if (util::GetMicroSeconds() >= timeout) {
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break;
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}
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if ((reg::Read(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL) & DSI_HOST_CONTROL_IMM_BTA) == 0) {
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break;
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}
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}
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}
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void EnableBacklightForVendor2050ForAula(int brightness) {
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/* Enable FRAME_END_INT */
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reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_ENABLE, 2);
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/* Configure DSI_LINE_TYPE as FOUR */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 1);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 9);
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/* Set and wait for FRAME_END_INT */
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reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2);
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while ((reg::Read(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS) & 2) != 0) { /* ... */ }
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/* Configure display brightness. */
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const u32 brightness_val = ((0x7FF * brightness) / 100);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x339);
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51);
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/* Set and wait for FRAME_END_INT */
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reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2);
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while ((reg::Read(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS) & 2) != 0) { /* ... */ }
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/* Set client sync point block reset. */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_INCR_SYNCPT_CNTRL, 1);
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util::WaitMicroSeconds(300'000ul);
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/* Clear client sync point block resest. */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_INCR_SYNCPT_CNTRL, 0);
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util::WaitMicroSeconds(300'000ul);
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/* Clear DSI_LINE_TYPE config. */
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 0);
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/* Disable FRAME_END_INT */
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reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_ENABLE, 0);
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reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2);
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}
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void EnableBacklightForGeneric(int brightness) {
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AMS_UNUSED(brightness);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
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}
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#define DO_REGISTER_WRITES(base_address, writes) DoRegisterWrites(base_address, writes, util::size(writes))
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#define DO_SOC_DEPENDENT_REGISTER_WRITES(base_address, writes) DoSocDependentRegisterWrites(base_address, writes##Erista, util::size(writes##Erista), writes##Mariko, util::size(writes##Mariko))
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#define DO_SLEEP_OR_REGISTER_WRITES(base_address, writes) DoSleepOrRegisterWrites(base_address, writes, util::size(writes))
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void InitializeFrameBuffer() {
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if (g_frame_buffer == nullptr) {
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g_frame_buffer = reinterpret_cast<u32 *>(0xC0400000);
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}
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hw::FlushDataCache(g_frame_buffer, FrameBufferSize);
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}
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[[maybe_unused]] void FinalizeFrameBuffer() {
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/* We don't actually support finalizing the framebuffer, so do nothing here. */
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}
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constexpr const char *GetErrorDescription(u32 error_desc) {
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switch (error_desc) {
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case 0x100:
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return "Instruction Abort";
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case 0x101:
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return "Data Abort";
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case 0x102:
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return "PC Misalignment";
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case 0x103:
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return "SP Misalignment";
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case 0x104:
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return "Trap";
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case 0x106:
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return "SError";
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case 0x301:
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return "Bad SVC";
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case 0xF00:
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return "Kernel Panic";
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case 0xFFD:
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return "Stack overflow";
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case 0xFFE:
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return "std::abort() called";
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default:
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return "Unknown";
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}
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}
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void PrintSuggestedErrorFix(const ams::impl::FatalErrorContext *f_ctx) {
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/* Try to recognize certain errors automatically, and suggest fixes for them. */
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const char *suggestion = nullptr;
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constexpr u64 ProgramIdAmsMitm = UINT64_C(0x010041544D530000);
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constexpr u64 ProgramIdBoot = UINT64_C(0x0100000000000005);
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if (f_ctx->error_desc == 0xFFE) {
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if (f_ctx->program_id == ProgramIdAmsMitm) {
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/* When a user has archive bits set improperly, attempting to create an automatic backup will fail */
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/* to create the file path with error 0x202 */
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if (f_ctx->gprs[0] == fs::ResultPathNotFound().GetValue()) {
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/* When the archive bit error is occurring, it manifests as failure to create automatic backup. */
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/* Thus, we can search the stack for the automatic backups path. */
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const char * const automatic_backups_prefix = "automatic_backups/X" /* ..... */;
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const int prefix_len = std::strlen(automatic_backups_prefix);
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for (size_t i = 0; i + prefix_len < f_ctx->stack_dump_size; ++i) {
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if (std::memcmp(&f_ctx->stack_dump[i], automatic_backups_prefix, prefix_len) == 0) {
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suggestion = "The atmosphere directory may improperly have archive bits set.\n"
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"Please try running an archive bit fixer tool (for example, the one in Hekate).\n";
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break;
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}
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}
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} else if (f_ctx->gprs[0] == fs::ResultExFatUnavailable().GetValue()) {
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/* When a user installs non-exFAT firm but has an exFAT formatted SD card, this error will */
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/* be returned on attempt to access the SD card. */
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suggestion = "Your console has non-exFAT firmware installed, but your SD card\n"
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"is formatted as exFAT. Format your SD card as FAT32, or manually\n"
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"flash exFAT firmware to package2.\n";
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}
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} else if (f_ctx->program_id == ProgramIdBoot) {
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/* 9.x -> 10.x updated the API for SvcQueryIoMapping. */
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/* This can cause the kernel to reject incorrect-ABI calls by boot when a partial update is applied */
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/* (older kernel in package2, for some reason). */
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for (size_t i = 0; i < 8; ++i) {
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if (f_ctx->gprs[i] == svc::ResultNotFound().GetValue()) {
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suggestion = "A partial update may have been improperly performed.\n"
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"To fix, try manually flashing latest package2 to MMC.\n"
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"\n"
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"For help doing this, seek support in the ReSwitched or\n"
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"Nintendo Homebrew discord servers.\n";
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break;
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}
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}
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}
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} else if (f_ctx->error_desc == 0xF00) { /* Kernel Panic */
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suggestion = "Please contact SciresM#0524 on Discord, or create an issue on the Atmosphere\n"
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"GitHub issue tracker. Thank you very much for helping to test mesosphere.\n";
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}
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/* If we found a suggestion, print it. */
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if (suggestion != nullptr) {
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Print("%s", suggestion);
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}
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}
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}
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bool IsDisplayInitialized() {
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return g_display_initialized;
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}
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void InitializeDisplay() {
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if (IsDisplayInitialized()) {
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return;
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}
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/* Setup the framebuffer. */
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InitializeFrameBuffer();
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/* Get the hardware type. */
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const auto hw_type = fuse::GetHardwareType();
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/* Turn on DSI/voltage rail. */
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{
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if (fuse::GetSocType() == fuse::SocType_Mariko) {
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i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, 0x18, 0x3A);
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i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, 0x18, 0x3A);
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}
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i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, 0x23, 0xD0);
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}
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/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_H_CLR_CLR_MIPI_CAL_RST, ENABLE),
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CLK_RST_REG_BITS_ENUM(RST_DEV_H_CLR_CLR_DSI_RST, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_H_SET_SET_CLK_ENB_MIPI_CAL, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_ENB_H_SET_SET_CLK_ENB_DSI, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_HOST1X_RST, ENABLE),
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CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_DISP1_RST, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_L_SET_SET_CLK_ENB_HOST1X, ENABLE),
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CLK_RST_REG_BITS_ENUM(CLK_ENB_L_SET_SET_CLK_ENB_DISP1, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_X_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_X_SET_SET_CLK_ENB_UART_FST_MIPI_CAL, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_DIVISOR, 10),
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CLK_RST_REG_BITS_ENUM (CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_SRC, PLLP_OUT3));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_W_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_W_SET_SET_CLK_ENB_DSIA_LP, ENABLE));
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reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_DIVISOR, 10),
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CLK_RST_REG_BITS_ENUM (CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_SRC, PLLP_OUT0));
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/* Set IO_DPD_REQ to DPD_OFF. */
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reg::ReadWrite(PMC + APBDEV_PMC_IO_DPD_REQ, PMC_REG_BITS_ENUM(IO_DPD_REQ_CODE, DPD_OFF));
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reg::ReadWrite(PMC + APBDEV_PMC_IO_DPD2_REQ, PMC_REG_BITS_ENUM(IO_DPD2_REQ_CODE, DPD_OFF));
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/* Configure LCD pinmux tristate + passthrough. */
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reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_NFC_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
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reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_NFC_INT, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
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reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_PWM, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
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reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
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reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_RST, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
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if (hw_type == fuse::HardwareType_Aula) {
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/* Configure LCD backlight. */
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reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x4);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x4);
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} else {
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/* Configure LCD power, VDD. */
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reg::SetBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
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util::WaitMicroSeconds(10'000ul);
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reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
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util::WaitMicroSeconds(10'000ul);
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/* Configure LCD backlight. */
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reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x7);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x7);
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2);
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}
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/* Configure display interface and display. */
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reg::Write(g_mipi_cal_regs + MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0);
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if (fuse::GetSocType() == fuse::SocType_Mariko) {
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reg::Write(g_mipi_cal_regs + MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0);
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reg::Write(g_apb_misc_regs + APB_MISC_GP_DSI_PAD_CONTROL, 0);
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}
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/* Execute configs. */
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01);
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DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init01);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init02);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init03);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init04);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init05);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init06);
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DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
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DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init07);
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util::WaitMicroSeconds(10'000ul);
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/* Enable backlight reset. */
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reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
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util::WaitMicroSeconds(60'000ul);
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if (hw_type == fuse::HardwareType_Aula) {
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x40103);
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} else {
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204);
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}
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reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x337);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
WaitDsiTrigger();
|
|
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x406);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
WaitDsiTrigger();
|
|
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
|
|
WaitDsiHostControl();
|
|
util::WaitMicroSeconds(5'000ul);
|
|
|
|
/* Parse LCD vendor. */
|
|
{
|
|
u32 host_response[3];
|
|
for (size_t i = 0; i < util::size(host_response); i++) {
|
|
host_response[i] = reg::Read(g_dsi_regs + sizeof(u32) * DSI_RD_DATA);
|
|
}
|
|
|
|
/* The last word from host response is:
|
|
Bits 0-7: FAB
|
|
Bits 8-15: REV
|
|
Bits 16-23: Minor REV
|
|
*/
|
|
u32 lcd_vendor;
|
|
if ((host_response[2] & 0xFF) == 0x10) {
|
|
lcd_vendor = 0;
|
|
} else {
|
|
lcd_vendor = (host_response[2] >> 8) & 0xFF00;
|
|
}
|
|
g_lcd_vendor = (lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF);
|
|
}
|
|
|
|
/* LCD vendor specific configuration. */
|
|
switch (g_lcd_vendor) {
|
|
case 0x10: /* Japan Display Inc screens. */
|
|
DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificInit01);
|
|
break;
|
|
case 0xF20: /* Innolux first revision screens. */
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(180'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(5'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(5'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
break;
|
|
case 0xF30: /* AUO first revision screens. */
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(180'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(5'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(5'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
break;
|
|
case 0x2050: /* Unknown (hardware type 5) screen. */
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(180'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xA015);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x205315);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x339);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x51);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(5'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
break;
|
|
case 0x1020: /* Innolux second revision screen. */
|
|
case 0x1030: /* AUO second revision screen. */
|
|
case 0x1040: /* Unknown second revision screen. */
|
|
default:
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
util::WaitMicroSeconds(120'000ul);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905);
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST);
|
|
break;
|
|
}
|
|
util::WaitMicroSeconds(20'000ul);
|
|
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld02);
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init08);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming);
|
|
DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init09);
|
|
|
|
reg::Write(g_disp1_regs + sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, SHIFT_CLK_DIVIDER(4));
|
|
DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init10);
|
|
util::WaitMicroSeconds(10'000ul);
|
|
|
|
/* Configure MIPI CAL. */
|
|
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal01);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
|
|
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
|
|
if (fuse::GetSocType() == fuse::SocType_Mariko) {
|
|
/* On Mariko the above configurations are executed twice, for some reason. */
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal02);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init11);
|
|
DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03);
|
|
DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04);
|
|
}
|
|
util::WaitMicroSeconds(10'000ul);
|
|
|
|
/* Write DISP1, FrameBuffer config. */
|
|
DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc02);
|
|
DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigFrameBuffer);
|
|
if (g_lcd_vendor != 0x2050) {
|
|
util::WaitMicroSeconds(35'000ul);
|
|
}
|
|
|
|
g_display_initialized = true;
|
|
}
|
|
|
|
void FinalizeDisplay() {
|
|
if (!IsDisplayInitialized()) {
|
|
return;
|
|
}
|
|
|
|
/* TODO: What other configuration is needed, if any? */
|
|
|
|
/* Configure LCD pinmux tristate + passthrough. */
|
|
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_NFC_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
|
|
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_NFC_INT, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
|
|
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_PWM, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
|
|
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
|
|
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_RST, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
|
|
|
|
if (fuse::GetHardwareType() == fuse::HardwareType_Aula) {
|
|
/* Configure LCD backlight. */
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x4);
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x4);
|
|
} else {
|
|
/* Configure LCD power, VDD. */
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3);
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3);
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
|
|
util::WaitMicroSeconds(10'000ul);
|
|
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
|
|
util::WaitMicroSeconds(10'000ul);
|
|
|
|
/* Configure LCD backlight. */
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x7);
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x7);
|
|
reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2);
|
|
}
|
|
|
|
/* Disable the LCD backlight. */
|
|
if (g_lcd_vendor == 0x2050) {
|
|
/* TODO: We're not sure display is alive. How to manage this? */
|
|
/* This is probably incorrect backlight disable for hw-type 5. */
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
|
|
} else {
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1);
|
|
}
|
|
|
|
/* Disable backlight RST/Voltage. */
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
|
|
if (g_lcd_vendor == 0x2050) {
|
|
util::WaitMicroSeconds(30'000ul);
|
|
} else {
|
|
util::WaitMicroSeconds(10'000ul);
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2);
|
|
util::WaitMicroSeconds(10'000ul);
|
|
reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1);
|
|
util::WaitMicroSeconds(10'000ul);
|
|
}
|
|
|
|
/* Cut clock to DSI. */
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_SET, CLK_RST_REG_BITS_ENUM(RST_DEV_H_SET_SET_MIPI_CAL_RST, ENABLE),
|
|
CLK_RST_REG_BITS_ENUM(RST_DEV_H_SET_SET_DSI_RST, ENABLE));
|
|
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLR_CLR_CLK_ENB_MIPI_CAL, ENABLE),
|
|
CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLR_CLR_CLK_ENB_DSI, ENABLE));
|
|
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_SET, CLK_RST_REG_BITS_ENUM(RST_DEV_L_SET_SET_HOST1X_RST, ENABLE),
|
|
CLK_RST_REG_BITS_ENUM(RST_DEV_L_SET_SET_DISP1_RST, ENABLE));
|
|
|
|
reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, CLK_RST_REG_BITS_ENUM(CLK_ENB_L_CLR_CLR_CLK_ENB_HOST1X, ENABLE),
|
|
CLK_RST_REG_BITS_ENUM(CLK_ENB_L_CLR_CLR_CLK_ENB_DISP1, ENABLE));
|
|
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_PAD_CONTROL_0, (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)));
|
|
reg::Write(g_dsi_regs + sizeof(u32) * DSI_POWER_CONTROL, 0);
|
|
|
|
g_display_initialized = false;
|
|
}
|
|
|
|
void ShowDisplay() {
|
|
/* Enable backlight. */
|
|
constexpr auto DisplayBrightness = 100;
|
|
if (g_lcd_vendor == 0x2050) {
|
|
EnableBacklightForVendor2050ForAula(DisplayBrightness);
|
|
} else {
|
|
EnableBacklightForGeneric(DisplayBrightness);
|
|
}
|
|
}
|
|
|
|
u16 GetDisplayLcdVendor() {
|
|
return g_lcd_vendor;
|
|
}
|
|
|
|
void ShowFatalError(const ams::impl::FatalErrorContext *f_ctx, const Result save_result) {
|
|
/* If needed, initialize the display. */
|
|
if (!IsDisplayInitialized()) {
|
|
InitializeDisplay();
|
|
}
|
|
|
|
/* Initialize the console. */
|
|
InitializeConsole(g_frame_buffer);
|
|
|
|
{
|
|
Print("%s\n", "A fatal error occurred when running Atmosph\xe8re.");
|
|
Print("Program ID: %016" PRIx64 "\n", f_ctx->program_id);
|
|
Print("Error Desc: %s (0x%" PRIx32 ")\n", GetErrorDescription(f_ctx->error_desc), f_ctx->error_desc);
|
|
Print("\n");
|
|
|
|
if (R_SUCCEEDED(save_result)) {
|
|
Print("Report saved to /atmosphere/fatal_errors/report_%016" PRIx64 ".bin", f_ctx->report_identifier);
|
|
} else {
|
|
Print("Failed to save report to the SD card! (%08" PRIx32 ")\n", save_result.GetValue());
|
|
}
|
|
|
|
PrintSuggestedErrorFix(f_ctx);
|
|
|
|
Print("\nPress POWER to reboot.\n");
|
|
}
|
|
|
|
/* Ensure the device will see consistent data. */
|
|
hw::FlushDataCache(g_frame_buffer, FrameBufferSize);
|
|
|
|
/* Show the console. */
|
|
ShowDisplay();
|
|
}
|
|
|
|
void ShowFatalError(const char *fmt, ...) {
|
|
/* If needed, initialize the display. */
|
|
if (!IsDisplayInitialized()) {
|
|
InitializeDisplay();
|
|
}
|
|
|
|
/* Initialize the console. */
|
|
InitializeConsole(g_frame_buffer);
|
|
|
|
{
|
|
Print("%s\n", "A fatal error occurred when running Fus" "\xe9" "e.");
|
|
{
|
|
std::va_list vl;
|
|
va_start(vl, fmt);
|
|
VPrint(fmt, vl);
|
|
va_end(vl);
|
|
}
|
|
Print("\n");
|
|
|
|
Print("\nPress POWER to reboot.\n");
|
|
}
|
|
|
|
/* Ensure the device will see consistent data. */
|
|
hw::FlushDataCache(g_frame_buffer, FrameBufferSize);
|
|
|
|
/* Show the console. */
|
|
ShowDisplay();
|
|
|
|
WaitForReboot();
|
|
}
|
|
|
|
}
|