Jumperless/JumperlessNano/include/rp2040.svd

<?xml version="1.0" encoding="utf-8"?>
<!--
  Copyright (c) 2020 Raspberry Pi (Trading) Ltd.

  SPDX-License-Identifier: BSD-3-Clause
-->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <addressUnitBits>8</addressUnitBits>
  <vendor>Raspberry Pi</vendor>
  <name>RP2040</name>
  <licenseText>
    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
    \n
    SPDX-License-Identifier: BSD-3-Clause
  </licenseText>
  <version>0.1</version>
  <width>32</width>
  <cpu>
    <name>CM0PLUS</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <nvicPrioBits>2</nvicPrioBits>
    <vtorPresent>1</vtorPresent>
    <vendorSystickConfig>false</vendorSystickConfig>
    <deviceNumInterrupts>26</deviceNumInterrupts>
  </cpu>
  <peripherals>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0020</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x14000000</baseAddress>
      <description>QSPI flash execute-in-place block</description>
      <interrupt>
        <name>XIP_IRQ</name>
        <value>6</value>
      </interrupt>
      <name>XIP_CTRL</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Cache control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>When 1, the cache memories are powered down. They retain state,\n
                but can not be accessed. This reduces static power dissipation.\n
                Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n
                be enabled when powered down.\n
                Cache-as-SRAM accesses will produce a bus error response when\n
                the cache is powered down.</description>
              <name>POWER_DOWN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>When 1, writes to any alias other than 0x0 (caching, allocating)\n
                will produce a bus fault. When 0, these writes are silently ignored.\n
                In either case, writes to the 0x0 alias will deallocate on tag match,\n
                as usual.</description>
              <name>ERR_BADWRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>When 1, enable the cache. When the cache is disabled, all XIP accesses\n
                will go straight to the flash, without querying the cache. When enabled,\n
                cacheable XIP accesses will query the cache, and the flash will\n
                not be accessed if the tag matches and the valid bit is set.\n\n
                If the cache is enabled, cache-as-SRAM accesses have no effect on the\n
                cache data RAM, and will produce a bus error response.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000003</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Cache Flush control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Write 1 to flush the cache. This clears the tag memory, but\n
                the data memory retains its contents. (This means cache-as-SRAM\n
                contents is not affected by flush or reset.)\n
                Reading will hold the bus (stall the processor) until the flush\n
                completes. Alternatively STAT can be polled until completion.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>FLUSH</name>
            </field>
          </fields>
          <name>FLUSH</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Cache Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>When 1, indicates the XIP streaming FIFO is completely full.\n
                The streaming FIFO is 2 entries deep, so the full and empty\n
                flag allow its level to be ascertained.</description>
              <name>FIFO_FULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
              <name>FIFO_EMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
                The cache is flushed whenever the XIP block is reset, and also\n
                when requested via the FLUSH register.</description>
              <name>FLUSH_READY</name>
            </field>
          </fields>
          <name>STAT</name>
          <resetValue>0x00000002</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x000c</addressOffset>
          <description>Cache Hit counter\n
            A 32 bit saturating counter that increments upon each cache hit,\n
            i.e. when an XIP access is serviced directly from cached data.\n
            Write any value to clear.</description>
          <modifiedWriteValues>oneToClear</modifiedWriteValues>
          <name>CTR_HIT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0010</addressOffset>
          <description>Cache Access counter\n
            A 32 bit saturating counter that increments upon each XIP access,\n
            whether the cache is hit or not. This includes noncacheable accesses.\n
            Write any value to clear.</description>
          <modifiedWriteValues>oneToClear</modifiedWriteValues>
          <name>CTR_ACC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>FIFO stream address</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:2]</bitRange>
              <description>The address of the next word to be streamed from flash to the streaming FIFO.\n
                Increments automatically after each flash access.\n
                Write the initial access address here before starting a streaming read.</description>
              <name>STREAM_ADDR</name>
            </field>
          </fields>
          <name>STREAM_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>FIFO stream control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[21:0]</bitRange>
              <description>Write a nonzero value to start a streaming read. This will then\n
                progress in the background, using flash idle cycles to transfer\n
                a linear data block from flash to the streaming FIFO.\n
                Decrements automatically (1 at a time) as the stream\n
                progresses, and halts on reaching 0.\n
                Write 0 to halt an in-progress stream, and discard any in-flight\n
                read, so that a new stream can immediately be started (after\n
                draining the FIFO and reinitialising STREAM_ADDR)</description>
              <name>STREAM_CTR</name>
            </field>
          </fields>
          <name>STREAM_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x001c</addressOffset>
          <description>FIFO stream data\n
            Streamed data is buffered here, for retrieval by the system DMA.\n
            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n
            the DMA to bus stalls caused by other XIP traffic.</description>
          <name>STREAM_FIFO</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0100</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x18000000</baseAddress>
      <description>DW_apb_ssi has the following features:\n
        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n
        * APB3 and APB4 protocol support.\n
        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n
        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n
        * Programmable Dual/Quad/Octal SPI support in Master Mode.\n
        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n
        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n
        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n
        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n
        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n
        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n
        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n
        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n
        * Programmable features:\n
        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n
        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n
        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n
        * Configured features:\n
        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
        - 1 slave select output.\n
        - Hardware slave-select – Dedicated hardware slave-select line.\n
        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n
        - Interrupt polarity – active high interrupt lines.\n
        - Serial clock polarity – low serial-clock polarity directly after reset.\n
        - Serial clock phase – capture on first edge of serial-clock directly after reset.</description>
      <name>XIP_SSI</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Control register 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>Slave select toggle enable</description>
              <name>SSTE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:21]</bitRange>
              <description>SPI frame format</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex</description>
                  <name>STD</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Dual-SPI frame format; two bits per SCK, half-duplex</description>
                  <name>DUAL</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Quad-SPI frame format; four bits per SCK, half-duplex</description>
                  <name>QUAD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SPI_FRF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:16]</bitRange>
              <description>Data frame size in 32b transfer mode\n
                Value of n -&gt; n+1 clocks per frame.</description>
              <name>DFS_32</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:12]</bitRange>
              <description>Control frame size\n
                Value of n -&gt; n+1 clocks per frame.</description>
              <name>CFS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Shift register loop (test mode)</description>
              <name>SRL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Slave output enable</description>
              <name>SLV_OE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Transfer mode</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Both transmit and receive</description>
                  <name>TX_AND_RX</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Transmit only (not for FRF == 0, standard SPI mode)</description>
                  <name>TX_ONLY</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Receive only (not for FRF == 0, standard SPI mode)</description>
                  <name>RX_ONLY</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>EEPROM read mode (TX then RX; RX starts after control data TX'd)</description>
                  <name>EEPROM_READ</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TMOD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Serial clock polarity</description>
              <name>SCPOL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Serial clock phase</description>
              <name>SCPH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Frame format</description>
              <name>FRF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Data frame size</description>
              <name>DFS</name>
            </field>
          </fields>
          <name>CTRLR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Master Control register 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Number of data frames</description>
              <name>NDF</name>
            </field>
          </fields>
          <name>CTRLR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>SSI Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>SSI enable</description>
              <name>SSI_EN</name>
            </field>
          </fields>
          <name>SSIENR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Microwire Control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Microwire handshaking</description>
              <name>MHS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Microwire control</description>
              <name>MDD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Microwire transfer mode</description>
              <name>MWMOD</name>
            </field>
          </fields>
          <name>MWCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Slave enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>For each bit:\n
                0 -&gt; slave not selected\n
                1 -&gt; slave selected</description>
              <name>SER</name>
            </field>
          </fields>
          <name>SER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Baud rate</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>SSI clock divider</description>
              <name>SCKDV</name>
            </field>
          </fields>
          <name>BAUDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>TX FIFO threshold level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit FIFO threshold</description>
              <name>TFT</name>
            </field>
          </fields>
          <name>TXFTLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>RX FIFO threshold level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive FIFO threshold</description>
              <name>RFT</name>
            </field>
          </fields>
          <name>RXFTLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>TX FIFO level</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit FIFO level</description>
              <name>TFTFL</name>
            </field>
          </fields>
          <name>TXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>RX FIFO level</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive FIFO level</description>
              <name>RXTFL</name>
            </field>
          </fields>
          <name>RXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Status register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Data collision error</description>
              <name>DCOL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmission error</description>
              <name>TXE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full</description>
              <name>RFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO not empty</description>
              <name>RFNE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Transmit FIFO empty</description>
              <name>TFE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO not full</description>
              <name>TFNF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>SSI busy flag</description>
              <name>BUSY</name>
            </field>
          </fields>
          <name>SR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Interrupt mask</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention interrupt mask</description>
              <name>MSTIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full interrupt mask</description>
              <name>RXFIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow interrupt mask</description>
              <name>RXOIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow interrupt mask</description>
              <name>RXUIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow interrupt mask</description>
              <name>TXOIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty interrupt mask</description>
              <name>TXEIM</name>
            </field>
          </fields>
          <name>IMR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Interrupt status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention interrupt status</description>
              <name>MSTIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full interrupt status</description>
              <name>RXFIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow interrupt status</description>
              <name>RXOIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow interrupt status</description>
              <name>RXUIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow interrupt status</description>
              <name>TXOIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty interrupt status</description>
              <name>TXEIS</name>
            </field>
          </fields>
          <name>ISR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Raw interrupt status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention raw interrupt status</description>
              <name>MSTIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full raw interrupt status</description>
              <name>RXFIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow raw interrupt status</description>
              <name>RXOIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow raw interrupt status</description>
              <name>RXUIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow raw interrupt status</description>
              <name>TXOIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty raw interrupt status</description>
              <name>TXEIR</name>
            </field>
          </fields>
          <name>RISR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>TX FIFO overflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read transmit FIFO overflow interrupt</description>
              <name>TXOICR</name>
            </field>
          </fields>
          <name>TXOICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>RX FIFO overflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read receive FIFO overflow interrupt</description>
              <name>RXOICR</name>
            </field>
          </fields>
          <name>RXOICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>RX FIFO underflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read receive FIFO underflow interrupt</description>
              <name>RXUICR</name>
            </field>
          </fields>
          <name>RXUICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Multi-master interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read multi-master contention interrupt</description>
              <name>MSTICR</name>
            </field>
          </fields>
          <name>MSTICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read all active interrupts</description>
              <name>ICR</name>
            </field>
          </fields>
          <name>ICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>DMA control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit DMA enable</description>
              <name>TDMAE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive DMA enable</description>
              <name>RDMAE</name>
            </field>
          </fields>
          <name>DMACR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>DMA TX data level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit data watermark level</description>
              <name>DMATDL</name>
            </field>
          </fields>
          <name>DMATDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>DMA RX data level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive data watermark level (DMARDLR+1)</description>
              <name>DMARDL</name>
            </field>
          </fields>
          <name>DMARDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Identification register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <description>Peripheral dentification code</description>
              <name>IDCODE</name>
            </field>
          </fields>
          <name>IDR</name>
          <resetValue>0x51535049</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Version ID</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <description>SNPS component version (format X.YY)</description>
              <name>SSI_COMP_VERSION</name>
            </field>
          </fields>
          <name>SSI_VERSION_ID</name>
          <resetValue>0x3430312a</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Data Register 0 (of 36)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>First data register of 36</description>
              <name>DR</name>
            </field>
          </fields>
          <name>DR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>RX sample delay</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>RXD sample delay (in SCLK cycles)</description>
              <name>RSD</name>
            </field>
          </fields>
          <name>RX_SAMPLE_DLY</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>SPI control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:24]</bitRange>
              <description>SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)</description>
              <name>XIP_CMD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Read data strobe enable</description>
              <name>SPI_RXDS_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Instruction DDR transfer enable</description>
              <name>INST_DDR_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>SPI DDR transfer enable</description>
              <name>SPI_DDR_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:11]</bitRange>
              <description>Wait cycles between control frame transmit and data reception (in SCLK cycles)</description>
              <name>WAIT_CYCLES</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Instruction length (0/4/8/16b)</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>No instruction</description>
                  <name>NONE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>4-bit instruction</description>
                  <name>4B</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>8-bit instruction</description>
                  <name>8B</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>16-bit instruction</description>
                  <name>16B</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INST_L</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:2]</bitRange>
              <description>Address length (0b-60b in 4b increments)</description>
              <name>ADDR_L</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:0]</bitRange>
              <description>Address and instruction transfer format</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Command and address both in standard SPI frame format</description>
                  <name>1C1A</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Command in standard SPI format, address in format specified by FRF</description>
                  <name>1C2A</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Command and address both in format specified by FRF (e.g. Dual-SPI)</description>
                  <name>2C2A</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TRANS_TYPE</name>
            </field>
          </fields>
          <name>SPI_CTRLR0</name>
          <resetValue>0x03000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>TX drive edge</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>TXD drive edge</description>
              <name>TDE</name>
            </field>
          </fields>
          <name>TXD_DRIVE_EDGE</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40000000</baseAddress>
      <name>SYSINFO</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>JEDEC JEP-106 compliant chip identifier.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:28]</bitRange>
              <name>REVISION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:12]</bitRange>
              <name>PART</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:0]</bitRange>
              <name>MANUFACTURER</name>
            </field>
          </fields>
          <name>CHIP_ID</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Platform register. Allows software to know what environment it is running in.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>ASIC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>FPGA</name>
            </field>
          </fields>
          <name>PLATFORM</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0040</addressOffset>
          <description>Git hash of the chip source. Used to identify chip version.</description>
          <name>GITREF_RP2040</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40004000</baseAddress>
      <description>Register block for various chip control signals</description>
      <name>SYSCFG</name>
      <registers>
        <register>
          <access>read-write</access>
          <addressOffset>0x0000</addressOffset>
          <description>Processor core 0 NMI source mask\n
            Set a bit high to enable NMI from that IRQ</description>
          <name>PROC0_NMI_MASK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0004</addressOffset>
          <description>Processor core 1 NMI source mask\n
            Set a bit high to enable NMI from that IRQ</description>
          <name>PROC1_NMI_MASK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Configuration for processors</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:28]</bitRange>
              <description>Configure proc1 DAP instance ID.\n
                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
                WARNING: do not set to 15 as this is reserved for RescueDP</description>
              <name>PROC1_DAP_INSTID</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:24]</bitRange>
              <description>Configure proc0 DAP instance ID.\n
                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
                WARNING: do not set to 15 as this is reserved for RescueDP</description>
              <name>PROC0_DAP_INSTID</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Indication that proc1 has halted</description>
              <name>PROC1_HALTED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Indication that proc0 has halted</description>
              <name>PROC0_HALTED</name>
            </field>
          </fields>
          <name>PROC_CONFIG</name>
          <resetValue>0x10000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
            and the GPIO input register in the SIO. The input synchronizers should\n
            generally be unbypassed, to avoid injecting metastabilities into processors.\n
            If you're feeling brave, you can bypass to save two cycles of input\n
            latency. This register applies to GPIO 0...29.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:0]</bitRange>
              <name>PROC_IN_SYNC_BYPASS</name>
            </field>
          </fields>
          <name>PROC_IN_SYNC_BYPASS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
            and the GPIO input register in the SIO. The input synchronizers should\n
            generally be unbypassed, to avoid injecting metastabilities into processors.\n
            If you're feeling brave, you can bypass to save two cycles of input\n
            latency. This register applies to GPIO 30...35 (the QSPI IOs).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <name>PROC_IN_SYNC_BYPASS_HI</name>
            </field>
          </fields>
          <name>PROC_IN_SYNC_BYPASS_HI</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Directly control the SWD debug port of either processor</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
              <name>PROC1_ATTACH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Directly drive processor 1 SWCLK, if PROC1_ATTACH is set</description>
              <name>PROC1_SWCLK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set</description>
              <name>PROC1_SWDI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Observe the value of processor 1 SWDIO output.</description>
              <name>PROC1_SWDO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
              <name>PROC0_ATTACH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Directly drive processor 0 SWCLK, if PROC0_ATTACH is set</description>
              <name>PROC0_SWCLK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set</description>
              <name>PROC0_SWDI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Observe the value of processor 0 SWDIO output.</description>
              <name>PROC0_SWDO</name>
            </field>
          </fields>
          <name>DBGFORCE</name>
          <resetValue>0x00000066</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Control power downs to memories. Set high to power down memories.\n
            Use with extreme caution</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>ROM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>USB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SRAM5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SRAM4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SRAM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SRAM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SRAM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SRAM0</name>
            </field>
          </fields>
          <name>MEMPOWERDOWN</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40008000</baseAddress>
      <interrupt>
        <name>CLOCKS_IRQ</name>
        <value>17</value>
      </interrupt>
      <name>CLOCKS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT0_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT0_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0008</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT0_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT1_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0014</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT1_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT2_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0020</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT2_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT3_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x002c</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT3_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[6:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:0]</bitRange>
              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_clk_ref_aux</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SRC</name>
            </field>
          </fields>
          <name>CLK_REF_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_REF_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0038</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
          <name>CLK_REF_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_clk_sys_aux</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SRC</name>
            </field>
          </fields>
          <name>CLK_SYS_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_SYS_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0044</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
          <name>CLK_SYS_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>6</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_PERI_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0050</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_PERI_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_USB_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_USB_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x005c</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_USB_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_ADC_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_ADC_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0068</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_ADC_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_RTC_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_RTC_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0074</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_RTC_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>For clearing the resus after the fault that triggered it has been corrected</description>
              <name>CLEAR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Force a resus, for test purposes only</description>
              <name>FRCE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Enable resus</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>This is expressed as a number of clk_ref cycles\n
                and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
              <name>TIMEOUT</name>
            </field>
          </fields>
          <name>CLK_SYS_RESUS_CTRL</name>
          <resetValue>0x000000ff</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
              <name>RESUSSED</name>
            </field>
          </fields>
          <name>CLK_SYS_RESUS_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Reference clock frequency in kHz</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[19:0]</bitRange>
              <name>FC0_REF_KHZ</name>
            </field>
          </fields>
          <name>FC0_REF_KHZ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:0]</bitRange>
              <name>FC0_MIN_KHZ</name>
            </field>
          </fields>
          <name>FC0_MIN_KHZ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:0]</bitRange>
              <name>FC0_MAX_KHZ</name>
            </field>
          </fields>
          <name>FC0_MAX_KHZ</name>
          <resetValue>0x01ffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Delays the start of frequency counting to allow the mux to settle\n
            Delay is measured in multiples of the reference clock period</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:0]</bitRange>
              <name>FC0_DELAY</name>
            </field>
          </fields>
          <name>FC0_DELAY</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
            The default gives a test interval of 250us</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FC0_INTERVAL</name>
            </field>
          </fields>
          <name>FC0_INTERVAL</name>
          <resetValue>0x00000008</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Clock sent to frequency counter, set to 0 when not required\n
            Writing to this register initiates the frequency count</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NULL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pll_sys_clksrc_primary</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pll_usb_clksrc_primary</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_peri</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>13</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FC0_SRC</name>
            </field>
          </fields>
          <name>FC0_SRC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Frequency counter status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <description>Test clock stopped during test</description>
              <name>DIED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>Test clock faster than expected, only valid when status_done=1</description>
              <name>FAST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <description>Test clock slower than expected, only valid when status_done=1</description>
              <name>SLOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Test failed</description>
              <name>FAIL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Waiting for test clock to start</description>
              <name>WAITING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Test running</description>
              <name>RUNNING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Test complete</description>
              <name>DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Test passed</description>
              <name>PASS</name>
            </field>
          </fields>
          <name>FC0_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>Result of frequency measurement, only valid when status_done=1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[29:5]</bitRange>
              <name>KHZ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>FC0_RESULT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>enable clock in wake mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>WAKE_EN0</name>
          <resetValue>0xffffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>enable clock in wake mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>WAKE_EN1</name>
          <resetValue>0x00007fff</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>enable clock in sleep mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>SLEEP_EN0</name>
          <resetValue>0xffffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>enable clock in sleep mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>SLEEP_EN1</name>
          <resetValue>0x00007fff</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>indicates the state of the clock enable</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>ENABLED0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>indicates the state of the clock enable</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>ENABLED1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00bc</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c0</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c4</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4000c000</baseAddress>
      <name>RESETS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>pads_qspi</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>pads_bank0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>io_qspi</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>io_bank0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>adc</name>
            </field>
          </fields>
          <name>RESET</name>
          <resetValue>0x01ffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>pads_qspi</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>pads_bank0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>io_qspi</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>io_bank0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>adc</name>
            </field>
          </fields>
          <name>WDSEL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>usbctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>uart1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>uart0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>timer</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>tbman</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>sysinfo</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>syscfg</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>spi1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>spi0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>rtc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>pwm</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>pll_usb</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>pll_sys</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>pio1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>pio0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>pads_qspi</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>pads_bank0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>jtag</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>io_qspi</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>io_bank0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>i2c1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>i2c0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>dma</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>busctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>adc</name>
            </field>
          </fields>
          <name>RESET_DONE</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40010000</baseAddress>
      <name>PSM</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Force block out of reset (i.e. power it on)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>proc1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>proc0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>sram4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clocks</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>rosc</name>
            </field>
          </fields>
          <name>FRCE_ON</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Force into reset (i.e. power it off)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>proc1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>proc0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>sram4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clocks</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>rosc</name>
            </field>
          </fields>
          <name>FRCE_OFF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Set to 1 if this peripheral should be reset when the watchdog fires.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>proc1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>proc0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>sram4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clocks</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>rosc</name>
            </field>
          </fields>
          <name>WDSEL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Indicates the peripheral's registers are ready to access.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>proc1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>proc0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>sio</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>xip</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>sram5</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>sram4</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>sram3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>sram2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>sram1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>sram0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>rom</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>busfabric</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>resets</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>clocks</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>xosc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>rosc</name>
            </field>
          </fields>
          <name>DONE</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40014000</baseAddress>
      <interrupt>
        <name>IO_IRQ_BANK0</name>
        <value>13</value>
      </interrupt>
      <name>IO_BANK0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO0_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>jtag_tck</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>spi0_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_0</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_0</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_0</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO0_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO1_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>jtag_tms</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>spi0_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_1</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_1</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_1</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO1_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO2_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>jtag_tdi</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>spi0_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_1</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_2</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_2</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_2</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO2_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO3_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>jtag_tdo</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>spi0_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_1</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_3</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_3</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_3</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO3_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO4_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_2</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_4</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_4</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_4</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO4_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO5_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_2</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_5</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_5</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_5</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO5_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO6_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_3</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_6</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_6</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_6</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_softcon</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO6_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO7_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_3</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_7</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_7</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_7</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_oe_n</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO7_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO8_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_4</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_8</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_8</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_8</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_rcv</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO8_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO9_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_4</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_9</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_9</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_9</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_vp</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO9_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO10_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_5</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_10</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_10</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_10</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_vm</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO10_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO11_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_5</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_11</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_11</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_11</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_suspnd</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO11_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO12_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_6</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_12</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_12</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_12</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_speed</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO12_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO13_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_6</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_13</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_13</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_13</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_vpo</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO13_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO14_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_7</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_14</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_14</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_14</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_extphy_vmo</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO14_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO15_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_7</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_15</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_15</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_15</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_digital_dp</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO15_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO16_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_16</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_16</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_16</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_digital_dm</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO16_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO17_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_17</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_17</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_17</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO17_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO18_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_1</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_18</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_18</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_18</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO18_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO19_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_1</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_19</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_19</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_19</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO19_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO20_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_2</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_20</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_20</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_20</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpin_0</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO20_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO21_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_2</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_21</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_21</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_21</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpout_0</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO21_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO22_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_3</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_22</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_22</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_22</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpin_1</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO22_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO23_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00bc</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi0_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_3</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_23</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_23</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_23</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpout_1</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO23_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00c0</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO24_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c4</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_4</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_24</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_24</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_24</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpout_2</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO24_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00c8</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO25_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00cc</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_4</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_25</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_25</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_25</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clocks_gpout_3</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO25_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00d0</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO26_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d4</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_sclk</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_cts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_5</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_26</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_26</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_26</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO26_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00d8</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO27_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00dc</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_tx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart1_rts</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c1_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_5</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_27</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_27</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_27</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_overcurr_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO27_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00e0</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO28_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e4</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_rx</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_tx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_sda</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_a_6</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_28</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_28</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_28</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_detect</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO28_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00e8</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO29_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ec</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>spi1_ss_n</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>uart0_rx</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>i2c0_scl</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pwm_b_6</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_29</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio0_29</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pio1_29</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>usb_muxing_vbus_en</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO29_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>INTR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>INTR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>INTR2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00fc</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>INTR3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0100</addressOffset>
          <description>Interrupt Enable for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0104</addressOffset>
          <description>Interrupt Enable for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0108</addressOffset>
          <description>Interrupt Enable for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTE2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x010c</addressOffset>
          <description>Interrupt Enable for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTE3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0110</addressOffset>
          <description>Interrupt Force for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0114</addressOffset>
          <description>Interrupt Force for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0118</addressOffset>
          <description>Interrupt Force for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTF2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x011c</addressOffset>
          <description>Interrupt Force for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTF3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0120</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTS0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0124</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTS1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0128</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTS2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x012c</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTS3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0130</addressOffset>
          <description>Interrupt Enable for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0134</addressOffset>
          <description>Interrupt Enable for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0138</addressOffset>
          <description>Interrupt Enable for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTE2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x013c</addressOffset>
          <description>Interrupt Enable for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTE3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0140</addressOffset>
          <description>Interrupt Force for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0144</addressOffset>
          <description>Interrupt Force for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0148</addressOffset>
          <description>Interrupt Force for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTF2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x014c</addressOffset>
          <description>Interrupt Force for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTF3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0150</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTS0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0154</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTS1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0158</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTS2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x015c</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTS3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0160</addressOffset>
          <description>Interrupt Enable for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0164</addressOffset>
          <description>Interrupt Enable for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0168</addressOffset>
          <description>Interrupt Enable for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTE2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x016c</addressOffset>
          <description>Interrupt Enable for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTE3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0170</addressOffset>
          <description>Interrupt Force for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0174</addressOffset>
          <description>Interrupt Force for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0178</addressOffset>
          <description>Interrupt Force for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTF2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x017c</addressOffset>
          <description>Interrupt Force for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTF3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0180</addressOffset>
          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO7_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO7_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO7_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO7_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO6_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO6_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO6_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO6_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO5_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO5_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO5_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO5_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO4_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO4_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO4_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO4_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO0_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTS0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0184</addressOffset>
          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO15_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO15_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO15_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO15_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO14_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO14_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO14_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO14_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO13_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO13_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO13_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO13_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO12_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO12_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO12_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO12_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO11_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO11_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO11_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO11_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO10_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO10_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO10_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO10_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO9_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO9_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO9_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO9_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO8_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO8_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO8_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO8_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTS1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0188</addressOffset>
          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>GPIO23_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>GPIO23_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>GPIO23_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>GPIO23_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>GPIO22_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>GPIO22_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>GPIO22_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>GPIO22_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO21_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO21_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO21_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO21_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO20_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO20_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO20_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO20_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO19_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO19_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO19_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO19_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO18_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO18_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO18_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO18_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO17_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO17_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO17_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO17_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO16_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO16_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO16_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO16_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTS2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x018c</addressOffset>
          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO29_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO29_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO29_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO29_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO28_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO28_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO28_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO28_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO27_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO27_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO27_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO27_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO26_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO26_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO26_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO26_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO25_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO25_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO25_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO25_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO24_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO24_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO24_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO24_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTS3</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40018000</baseAddress>
      <interrupt>
        <name>IO_IRQ_QSPI</name>
        <value>14</value>
      </interrupt>
      <name>IO_QSPI</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SCLK_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_sclk</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_30</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SCLK_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SS_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_ss_n</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_31</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SS_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD0_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_sd0</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_32</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD0_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD1_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_sd1</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_33</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD1_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD2_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_sd2</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_34</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD2_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>GPIO status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <description>interrupt to processors, after override is applied</description>
              <name>IRQTOPROC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>interrupt from pad before override is applied</description>
              <name>IRQFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>input signal to peripheral, after override is applied</description>
              <name>INTOPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>input signal from pad, before override is applied</description>
              <name>INFROMPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>output enable to pad after register override is applied</description>
              <name>OETOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>output enable from selected peripheral, before register override is applied</description>
              <name>OEFROMPERI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>output signal to pad after register override is applied</description>
              <name>OUTTOPAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>output signal from selected peripheral, before register override is applied</description>
              <name>OUTFROMPERI</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD3_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>GPIO control including function select and overrides.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:28]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the interrupt</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the interrupt</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive interrupt high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IRQOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>don't invert the peri input</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>invert the peri input</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive peri input high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:12]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output enable from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>disable output</description>
                  <name>DISABLE</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>enable output</description>
                  <name>ENABLE</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OEOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>drive output from peripheral signal selected by funcsel</description>
                  <name>NORMAL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
                  <name>INVERT</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output low</description>
                  <name>LOW</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>drive output high</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>OUTOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>0-31 -&gt; selects pin function according to the gpio table\n
                31 == NULL</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>xip_sd3</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sio_35</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>null</name>
                  <value>31</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FUNCSEL</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD3_CTRL</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Interrupt Enable for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Interrupt Force for proc0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC0_INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Interrupt Enable for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Interrupt Force for proc1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Interrupt status after masking &amp; forcing for proc1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>PROC1_INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>Interrupt Enable for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Interrupt Force for dormant_wake</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>GPIO_QSPI_SS_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
            </field>
          </fields>
          <name>DORMANT_WAKE_INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4001c000</baseAddress>
      <name>PADS_BANK0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Voltage select. Per bank control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
                  <name>3v3</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
                  <name>1v8</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>VOLTAGE_SELECT</name>
            </field>
          </fields>
          <name>VOLTAGE_SELECT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO0</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO1</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO2</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO3</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO4</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO5</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO6</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO7</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO8</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO9</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO10</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO11</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO12</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO13</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO14</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO15</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO16</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO17</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO18</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO19</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO20</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO21</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO22</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO23</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO24</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO25</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO26</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO27</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO28</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO29</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>SWCLK</name>
          <resetValue>0x000000da</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>SWD</name>
          <resetValue>0x0000005a</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40020000</baseAddress>
      <name>PADS_QSPI</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Voltage select. Per bank control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
                  <name>3v3</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
                  <name>1v8</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>VOLTAGE_SELECT</name>
            </field>
          </fields>
          <name>VOLTAGE_SELECT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SCLK</name>
          <resetValue>0x00000056</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD0</name>
          <resetValue>0x00000052</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD1</name>
          <resetValue>0x00000052</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD2</name>
          <resetValue>0x00000052</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SD3</name>
          <resetValue>0x00000052</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Pad control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Output disable. Has priority over output enable from peripherals</description>
              <name>OD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Input enable</description>
              <name>IE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Drive strength.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>2mA</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>4mA</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>8mA</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>12mA</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DRIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Pull up enable</description>
              <name>PUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pull down enable</description>
              <name>PDE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enable schmitt trigger</description>
              <name>SCHMITT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
              <name>SLEWFAST</name>
            </field>
          </fields>
          <name>GPIO_QSPI_SS</name>
          <resetValue>0x0000005a</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40024000</baseAddress>
      <description>Controls the crystal oscillator</description>
      <name>XOSC</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Crystal Oscillator Control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:12]</bitRange>
              <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n
                If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n
                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <value>3358</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <value>4011</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:0]</bitRange>
              <description>Frequency range. This resets to 0xAA0 and cannot be changed.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>1_15MHZ</name>
                  <value>2720</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_1</name>
                  <value>2721</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_2</name>
                  <value>2722</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_3</name>
                  <value>2723</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FREQ_RANGE</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Crystal Oscillator Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Oscillator is running and stable</description>
              <name>STABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BADWRITE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Oscillator is enabled but not necessarily running and stable, resets to 0</description>
              <name>ENABLED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:0]</bitRange>
              <description>The current frequency range setting, always reads 0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>1_15MHZ</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_1</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_2</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RESERVED_3</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FREQ_RANGE</name>
            </field>
          </fields>
          <name>STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0008</addressOffset>
          <description>Crystal Oscillator pause control\n
            This is used to save power by pausing the XOSC\n
            On power-up this field is initialised to WAKE\n
            An invalid write will also select WAKE\n
            WARNING: stop the PLLs before selecting dormant mode\n
            WARNING: setup the irq before selecting dormant mode</description>
          <name>DORMANT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Controls the startup delay</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.</description>
              <name>X4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:0]</bitRange>
              <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
              <name>DELAY</name>
            </field>
          </fields>
          <name>STARTUP</name>
          <resetValue>0x000000c4</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>A down counter running at the xosc frequency which counts to zero and stops.\n
            To start the counter write a non-zero value.\n
            Can be used for short software pauses when setting up time sensitive hardware.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <name>COUNT</name>
            </field>
          </fields>
          <name>COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40028000</baseAddress>
      <name>PLL_SYS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Control and Status\n
            GENERAL CONSTRAINTS:\n
            Reference clock frequency min=5MHz, max=800MHz\n
            Feedback divider min=16, max=320\n
            VCO frequency min=750MHz, max=1600MHz</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>PLL is locked</description>
              <name>LOCK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</description>
              <name>BYPASS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>Divides the PLL input reference clock.\n
                Behaviour is undefined for div=0.\n
                PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</description>
              <name>REFDIV</name>
            </field>
          </fields>
          <name>CS</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Controls the PLL power modes.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>PLL VCO powerdown\n
                To save power set high when PLL output not required or bypass=1.</description>
              <name>VCOPD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>PLL post divider powerdown\n
                To save power set high when PLL output not required or bypass=1.</description>
              <name>POSTDIVPD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>PLL DSM powerdown\n
                Nothing is achieved by setting this low.</description>
              <name>DSMPD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>PLL powerdown\n
                To save power set high when PLL output not required.</description>
              <name>PD</name>
            </field>
          </fields>
          <name>PWR</name>
          <resetValue>0x0000002d</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Feedback divisor\n
            (note: this PLL does not support fractional division)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:0]</bitRange>
              <description>see ctrl reg description for constraints</description>
              <name>FBDIV_INT</name>
            </field>
          </fields>
          <name>FBDIV_INT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Controls the PLL post dividers for the primary output\n
            (note: this PLL does not have a secondary output)\n
            the primary output is driven from VCO divided by postdiv1*postdiv2</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[18:16]</bitRange>
              <description>divide by 1-7</description>
              <name>POSTDIV1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:12]</bitRange>
              <description>divide by 1-7</description>
              <name>POSTDIV2</name>
            </field>
          </fields>
          <name>PRIM</name>
          <resetValue>0x00077000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral derivedFrom="PLL_SYS">
      <baseAddress>0x4002c000</baseAddress>
      <name>PLL_USB</name>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40030000</baseAddress>
      <description>Register block for busfabric control signals and performance counters</description>
      <name>BUSCTRL</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Set the priority of each master for bus arbitration.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>0 - low priority, 1 - high priority</description>
              <name>DMA_W</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>0 - low priority, 1 - high priority</description>
              <name>DMA_R</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>0 - low priority, 1 - high priority</description>
              <name>PROC1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>0 - low priority, 1 - high priority</description>
              <name>PROC0</name>
            </field>
          </fields>
          <name>BUS_PRIORITY</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Bus priority acknowledge</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Goes to 1 once all arbiters have registered the new global priority levels.\n
                Arbiters update their local priority when servicing a new nonsequential access.\n
                In normal circumstances this will happen almost immediately.</description>
              <name>BUS_PRIORITY_ACK</name>
            </field>
          </fields>
          <name>BUS_PRIORITY_ACK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Bus fabric performance counter 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Busfabric saturating performance counter 0\n
                Count some event signal from the busfabric arbiters.\n
                Write any value to clear. Select an event to count using PERFSEL0</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PERFCTR0</name>
            </field>
          </fields>
          <name>PERFCTR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Bus fabric performance event select for PERFCTR0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>apb_contested</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>apb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi_contested</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5_contested</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4_contested</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3_contested</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2_contested</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1_contested</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1</name>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0_contested</name>
                  <value>14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0</name>
                  <value>15</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main_contested</name>
                  <value>16</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main</name>
                  <value>17</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom_contested</name>
                  <value>18</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom</name>
                  <value>19</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PERFSEL0</name>
            </field>
          </fields>
          <name>PERFSEL0</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Bus fabric performance counter 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Busfabric saturating performance counter 1\n
                Count some event signal from the busfabric arbiters.\n
                Write any value to clear. Select an event to count using PERFSEL1</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PERFCTR1</name>
            </field>
          </fields>
          <name>PERFCTR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Bus fabric performance event select for PERFCTR1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>apb_contested</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>apb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi_contested</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5_contested</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4_contested</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3_contested</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2_contested</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1_contested</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1</name>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0_contested</name>
                  <value>14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0</name>
                  <value>15</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main_contested</name>
                  <value>16</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main</name>
                  <value>17</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom_contested</name>
                  <value>18</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom</name>
                  <value>19</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PERFSEL1</name>
            </field>
          </fields>
          <name>PERFSEL1</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Bus fabric performance counter 2</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Busfabric saturating performance counter 2\n
                Count some event signal from the busfabric arbiters.\n
                Write any value to clear. Select an event to count using PERFSEL2</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PERFCTR2</name>
            </field>
          </fields>
          <name>PERFCTR2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Bus fabric performance event select for PERFCTR2</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>apb_contested</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>apb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi_contested</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5_contested</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4_contested</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3_contested</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2_contested</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1_contested</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1</name>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0_contested</name>
                  <value>14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0</name>
                  <value>15</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main_contested</name>
                  <value>16</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main</name>
                  <value>17</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom_contested</name>
                  <value>18</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom</name>
                  <value>19</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PERFSEL2</name>
            </field>
          </fields>
          <name>PERFSEL2</name>
          <resetValue>0x0000001f</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Bus fabric performance counter 3</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Busfabric saturating performance counter 3\n
                Count some event signal from the busfabric arbiters.\n
                Write any value to clear. Select an event to count using PERFSEL3</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PERFCTR3</name>
            </field>
          </fields>
          <name>PERFCTR3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Bus fabric performance event select for PERFCTR3</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>apb_contested</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>apb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi_contested</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>fastperi</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5_contested</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram5</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4_contested</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram4</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3_contested</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram3</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2_contested</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram2</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1_contested</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram1</name>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0_contested</name>
                  <value>14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>sram0</name>
                  <value>15</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main_contested</name>
                  <value>16</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xip_main</name>
                  <value>17</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom_contested</name>
                  <value>18</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rom</name>
                  <value>19</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PERFSEL3</name>
            </field>
          </fields>
          <name>PERFSEL3</name>
          <resetValue>0x0000001f</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40034000</baseAddress>
      <interrupt>
        <name>UART0_IRQ</name>
        <value>20</value>
      </interrupt>
      <name>UART0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Data Register, UARTDR</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.</description>
              <name>OE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.</description>
              <name>BE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
              <name>PE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
              <name>FE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive (read) data character. Transmit (write) data character.</description>
              <name>DATA</name>
            </field>
          </fields>
          <name>UARTDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>OE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>FE</name>
            </field>
          </fields>
          <name>UARTRSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Flag Register, UARTFR</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.</description>
              <name>RI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.</description>
              <name>TXFE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.</description>
              <name>RXFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.</description>
              <name>TXFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.</description>
              <name>RXFE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.</description>
              <name>DCD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.</description>
              <name>DSR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.</description>
              <name>CTS</name>
            </field>
          </fields>
          <name>UARTFR</name>
          <resetValue>0x00000090</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>IrDA Low-Power Counter Register, UARTILPR</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>8-bit low-power divisor value. These bits are cleared to 0 at reset.</description>
              <name>ILPDVSR</name>
            </field>
          </fields>
          <name>UARTILPR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Integer Baud Rate Register, UARTIBRD</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>The integer baud rate divisor. These bits are cleared to 0 on reset.</description>
              <name>BAUD_DIVINT</name>
            </field>
          </fields>
          <name>UARTIBRD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Fractional Baud Rate Register, UARTFBRD</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>The fractional baud rate divisor. These bits are cleared to 0 on reset.</description>
              <name>BAUD_DIVFRAC</name>
            </field>
          </fields>
          <name>UARTFBRD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Line Control Register, UARTLCR_H</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.</description>
              <name>SPS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:5]</bitRange>
              <description>Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.</description>
              <name>WLEN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).</description>
              <name>FEN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.</description>
              <name>STP2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.</description>
              <name>EPS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.</description>
              <name>PEN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.</description>
              <name>BRK</name>
            </field>
          </fields>
          <name>UARTLCR_H</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Control Register, UARTCR</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</description>
              <name>CTSEN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</description>
              <name>RTSEN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</description>
              <name>OUT2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</description>
              <name>OUT1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</description>
              <name>RTS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</description>
              <name>DTR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</description>
              <name>RXE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</description>
              <name>TXE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</description>
              <name>LBE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</description>
              <name>SIRLP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</description>
              <name>SIREN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</description>
              <name>UARTEN</name>
            </field>
          </fields>
          <name>UARTCR</name>
          <resetValue>0x00000300</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Interrupt FIFO Level Select Register, UARTIFLS</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:3]</bitRange>
              <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes &gt;= 1 / 8 full b001 = Receive FIFO becomes &gt;= 1 / 4 full b010 = Receive FIFO becomes &gt;= 1 / 2 full b011 = Receive FIFO becomes &gt;= 3 / 4 full b100 = Receive FIFO becomes &gt;= 7 / 8 full b101-b111 = reserved.</description>
              <name>RXIFLSEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:0]</bitRange>
              <description>Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved.</description>
              <name>TXIFLSEL</name>
            </field>
          </fields>
          <name>UARTIFLS</name>
          <resetValue>0x00000012</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Interrupt Mask Set/Clear Register, UARTIMSC</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>OEIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>BEIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>PEIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>FEIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>RTIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>TXIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>RXIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>DSRMIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>DCDMIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>CTSMIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.</description>
              <name>RIMIM</name>
            </field>
          </fields>
          <name>UARTIMSC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Raw Interrupt Status Register, UARTRIS</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.</description>
              <name>OERIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.</description>
              <name>BERIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.</description>
              <name>PERIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.</description>
              <name>FERIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a</description>
              <name>RTRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.</description>
              <name>TXRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.</description>
              <name>RXRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.</description>
              <name>DSRRMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.</description>
              <name>DCDRMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.</description>
              <name>CTSRMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.</description>
              <name>RIRMIS</name>
            </field>
          </fields>
          <name>UARTRIS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Masked Interrupt Status Register, UARTMIS</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.</description>
              <name>OEMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.</description>
              <name>BEMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.</description>
              <name>PEMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.</description>
              <name>FEMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.</description>
              <name>RTMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.</description>
              <name>TXMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.</description>
              <name>RXMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.</description>
              <name>DSRMMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.</description>
              <name>DCDMMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.</description>
              <name>CTSMMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.</description>
              <name>RIMMIS</name>
            </field>
          </fields>
          <name>UARTMIS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Interrupt Clear Register, UARTICR</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Overrun error interrupt clear. Clears the UARTOEINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>OEIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Break error interrupt clear. Clears the UARTBEINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BEIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Parity error interrupt clear. Clears the UARTPEINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PEIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Framing error interrupt clear. Clears the UARTFEINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>FEIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RTIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmit interrupt clear. Clears the UARTTXINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>TXIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive interrupt clear. Clears the UARTRXINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RXIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>DSRMIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>DCDMIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CTSMIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RIMIC</name>
            </field>
          </fields>
          <name>UARTICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>DMA Control Register, UARTDMACR</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.</description>
              <name>DMAONERR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
              <name>TXDMAE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
              <name>RXDMAE</name>
            </field>
          </fields>
          <name>UARTDMACR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe0</addressOffset>
          <description>UARTPeriphID0 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x11</description>
              <name>PARTNUMBER0</name>
            </field>
          </fields>
          <name>UARTPERIPHID0</name>
          <resetValue>0x00000011</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe4</addressOffset>
          <description>UARTPeriphID1 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:4]</bitRange>
              <description>These bits read back as 0x1</description>
              <name>DESIGNER0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>These bits read back as 0x0</description>
              <name>PARTNUMBER1</name>
            </field>
          </fields>
          <name>UARTPERIPHID1</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe8</addressOffset>
          <description>UARTPeriphID2 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:4]</bitRange>
              <description>This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3</description>
              <name>REVISION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>These bits read back as 0x4</description>
              <name>DESIGNER1</name>
            </field>
          </fields>
          <name>UARTPERIPHID2</name>
          <resetValue>0x00000034</resetValue>
        </register>
        <register>
          <addressOffset>0x0fec</addressOffset>
          <description>UARTPeriphID3 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x00</description>
              <name>CONFIGURATION</name>
            </field>
          </fields>
          <name>UARTPERIPHID3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff0</addressOffset>
          <description>UARTPCellID0 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x0D</description>
              <name>UARTPCELLID0</name>
            </field>
          </fields>
          <name>UARTPCELLID0</name>
          <resetValue>0x0000000d</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff4</addressOffset>
          <description>UARTPCellID1 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0xF0</description>
              <name>UARTPCELLID1</name>
            </field>
          </fields>
          <name>UARTPCELLID1</name>
          <resetValue>0x000000f0</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff8</addressOffset>
          <description>UARTPCellID2 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x05</description>
              <name>UARTPCELLID2</name>
            </field>
          </fields>
          <name>UARTPCELLID2</name>
          <resetValue>0x00000005</resetValue>
        </register>
        <register>
          <addressOffset>0x0ffc</addressOffset>
          <description>UARTPCellID3 Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0xB1</description>
              <name>UARTPCELLID3</name>
            </field>
          </fields>
          <name>UARTPCELLID3</name>
          <resetValue>0x000000b1</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral derivedFrom="UART0">
      <baseAddress>0x40038000</baseAddress>
      <interrupt>
        <name>UART1_IRQ</name>
        <value>21</value>
      </interrupt>
      <name>UART1</name>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4003c000</baseAddress>
      <interrupt>
        <name>SPI0_IRQ</name>
        <value>18</value>
      </interrupt>
      <name>SPI0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Control register 0, SSPCR0 on page 3-4</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.</description>
              <name>SCR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
              <name>SPH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
              <name>SPO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.</description>
              <name>FRF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.</description>
              <name>DSS</name>
            </field>
          </fields>
          <name>SSPCR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Control register 1, SSPCR1 on page 3-5</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.</description>
              <name>SOD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.</description>
              <name>MS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.</description>
              <name>SSE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.</description>
              <name>LBM</name>
            </field>
          </fields>
          <name>SSPCR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Data register, SSPDR on page 3-6</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.</description>
              <name>DATA</name>
            </field>
          </fields>
          <name>SSPDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Status register, SSPSR on page 3-7</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.</description>
              <name>BSY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.</description>
              <name>RFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.</description>
              <name>RNE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.</description>
              <name>TNF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.</description>
              <name>TFE</name>
            </field>
          </fields>
          <name>SSPSR</name>
          <resetValue>0x00000003</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Clock prescale register, SSPCPSR on page 3-8</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.</description>
              <name>CPSDVSR</name>
            </field>
          </fields>
          <name>SSPCPSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Interrupt mask set or clear register, SSPIMSC on page 3-9</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.</description>
              <name>TXIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.</description>
              <name>RXIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.</description>
              <name>RTIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.</description>
              <name>RORIM</name>
            </field>
          </fields>
          <name>SSPIMSC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Raw interrupt status register, SSPRIS on page 3-10</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt</description>
              <name>TXRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt</description>
              <name>RXRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt</description>
              <name>RTRIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt</description>
              <name>RORRIS</name>
            </field>
          </fields>
          <name>SSPRIS</name>
          <resetValue>0x00000008</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Masked interrupt status register, SSPMIS on page 3-11</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt</description>
              <name>TXMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt</description>
              <name>RXMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt</description>
              <name>RTMIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt</description>
              <name>RORMIS</name>
            </field>
          </fields>
          <name>SSPMIS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Interrupt clear register, SSPICR on page 3-11</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Clears the SSPRTINTR interrupt</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RTIC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Clears the SSPRORINTR interrupt</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RORIC</name>
            </field>
          </fields>
          <name>SSPICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>DMA control register, SSPDMACR on page 3-12</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
              <name>TXDMAE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
              <name>RXDMAE</name>
            </field>
          </fields>
          <name>SSPDMACR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe0</addressOffset>
          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x22</description>
              <name>PARTNUMBER0</name>
            </field>
          </fields>
          <name>SSPPERIPHID0</name>
          <resetValue>0x00000022</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe4</addressOffset>
          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:4]</bitRange>
              <description>These bits read back as 0x1</description>
              <name>DESIGNER0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>These bits read back as 0x0</description>
              <name>PARTNUMBER1</name>
            </field>
          </fields>
          <name>SSPPERIPHID1</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0fe8</addressOffset>
          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:4]</bitRange>
              <description>These bits return the peripheral revision</description>
              <name>REVISION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>These bits read back as 0x4</description>
              <name>DESIGNER1</name>
            </field>
          </fields>
          <name>SSPPERIPHID2</name>
          <resetValue>0x00000034</resetValue>
        </register>
        <register>
          <addressOffset>0x0fec</addressOffset>
          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x00</description>
              <name>CONFIGURATION</name>
            </field>
          </fields>
          <name>SSPPERIPHID3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff0</addressOffset>
          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x0D</description>
              <name>SSPPCELLID0</name>
            </field>
          </fields>
          <name>SSPPCELLID0</name>
          <resetValue>0x0000000d</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff4</addressOffset>
          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0xF0</description>
              <name>SSPPCELLID1</name>
            </field>
          </fields>
          <name>SSPPCELLID1</name>
          <resetValue>0x000000f0</resetValue>
        </register>
        <register>
          <addressOffset>0x0ff8</addressOffset>
          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0x05</description>
              <name>SSPPCELLID2</name>
            </field>
          </fields>
          <name>SSPPCELLID2</name>
          <resetValue>0x00000005</resetValue>
        </register>
        <register>
          <addressOffset>0x0ffc</addressOffset>
          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>These bits read back as 0xB1</description>
              <name>SSPPCELLID3</name>
            </field>
          </fields>
          <name>SSPPCELLID3</name>
          <resetValue>0x000000b1</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral derivedFrom="SPI0">
      <baseAddress>0x40040000</baseAddress>
      <interrupt>
        <name>SPI1_IRQ</name>
        <value>19</value>
      </interrupt>
      <name>SPI1</name>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0100</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40044000</baseAddress>
      <description>DW_apb_i2c address block\n\n
        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
        IC_ULTRA_FAST_MODE ................ 0x0\n
        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
        IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
        IC_TX_TL .......................... 0x0\n
        IC_TX_CMD_BLOCK ................... 0x1\n
        IC_HAS_DMA ........................ 0x1\n
        IC_HAS_ASYNC_FIFO ................. 0x0\n
        IC_SMBUS_ARP ...................... 0x0\n
        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
        IC_INTR_IO ........................ 0x1\n
        IC_MASTER_MODE .................... 0x1\n
        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
        IC_INTR_POL ....................... 0x1\n
        IC_OPTIONAL_SAR ................... 0x0\n
        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
        IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
        IC_DEFAULT_HS_SPKLEN .............. 0x1\n
        IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
        IC_HS_SCL_LOW_COUNT ............... 0x0008\n
        IC_DEVICE_ID_VALUE ................ 0x0\n
        IC_10BITADDR_MASTER ............... 0x0\n
        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
        IC_DEFAULT_FS_SPKLEN .............. 0x7\n
        IC_ADD_ENCODED_PARAMS ............. 0x0\n
        IC_DEFAULT_SDA_HOLD ............... 0x000001\n
        IC_DEFAULT_SDA_SETUP .............. 0x64\n
        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
        IC_CLOCK_PERIOD ................... 100\n
        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
        IC_RESTART_EN ..................... 0x1\n
        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
        IC_BUS_CLEAR_FEATURE .............. 0x0\n
        IC_CAP_LOADING .................... 100\n
        IC_FS_SCL_LOW_COUNT ............... 0x000d\n
        APB_DATA_WIDTH .................... 32\n
        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
        IC_SLV_DATA_NACK_ONLY ............. 0x1\n
        IC_10BITADDR_SLAVE ................ 0x0\n
        IC_CLK_TYPE ....................... 0x0\n
        IC_SMBUS_UDID_MSB ................. 0x0\n
        IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
        IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
        IC_SLV_RESTART_DET_EN ............. 0x1\n
        IC_SMBUS .......................... 0x0\n
        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
        IC_USE_COUNTS ..................... 0x0\n
        IC_RX_BUFFER_DEPTH ................ 16\n
        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
        IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
        IC_SLAVE_DISABLE .................. 0x1\n
        IC_RX_TL .......................... 0x0\n
        IC_DEVICE_ID ...................... 0x0\n
        IC_HC_COUNT_VALUES ................ 0x0\n
        I2C_DYNAMIC_TAR_UPDATE ............ 0\n
        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
        IC_HS_MASTER_CODE ................. 0x1\n
        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
        IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
        IC_SS_SCL_LOW_COUNT ............... 0x002f\n
        IC_MAX_SPEED_MODE ................. 0x2\n
        IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
        IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
        IC_TX_BUFFER_DEPTH ................ 16</description>
      <interrupt>
        <name>I2C0_IRQ</name>
        <value>23</value>
      </interrupt>
      <name>I2C0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
            Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Master issues the STOP_DET interrupt irrespective of whether master is active or not</description>
              <name>STOP_DET_IF_MASTER_ACTIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n
                Reset value: 0x0.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Overflow when RX_FIFO is full</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Hold bus when RX_FIFO is full</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RX_FIFO_FULL_HLD_CTRL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Default behaviour of TX_EMPTY interrupt</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Controlled generation of TX_EMPTY interrupt</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TX_EMPTY_CTRL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is addressed. - 1'b0:  issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n
                NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>slave issues STOP_DET intr always</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>slave issues STOP_DET intr only if addressed</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STOP_DET_IFADDRESSED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n
                If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n
                NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave mode is enabled</description>
                  <name>SLAVE_ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave mode is disabled</description>
                  <name>SLAVE_DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IC_SLAVE_DISABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: ENABLED</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master restart disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master restart enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IC_RESTART_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master 7Bit addressing mode</description>
                  <name>ADDR_7BITS</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master 10Bit addressing mode</description>
                  <name>ADDR_10BITS</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IC_10BITADDR_MASTER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave 7Bit addressing</description>
                  <name>ADDR_7BITS</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave 10Bit addressing</description>
                  <name>ADDR_10BITS</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IC_10BITADDR_SLAVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:1]</bitRange>
              <description>These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n
                This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n
                1: standard mode (100 kbit/s)\n\n
                2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)\n\n
                3: high speed mode (3.4 Mbit/s)\n\n
                Note: This field is not applicable when IC_ULTRA_FAST_MODE=1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Standard Speed mode of operation</description>
                  <name>STANDARD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fast or Fast Plus mode of operation</description>
                  <name>FAST</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>High Speed mode of operation</description>
                  <name>HIGH</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SPEED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>This bit controls whether the DW_apb_i2c master is enabled.\n\n
                NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master mode is disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master mode is enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>MASTER_MODE</name>
            </field>
          </fields>
          <name>IC_CON</name>
          <resetValue>0x00000065</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>I2C Target Address Register\n\n
            This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n
            Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Disables programming of GENERAL_CALL or START_BYTE transmission</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Enables programming of GENERAL_CALL or START_BYTE transmission</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SPECIAL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>GENERAL_CALL byte transmission</description>
                  <name>GENERAL_CALL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>START byte transmission</description>
                  <name>START_BYTE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>GC_OR_START</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n
                If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.</description>
              <name>IC_TAR</name>
            </field>
          </fields>
          <name>IC_TAR</name>
          <resetValue>0x00000055</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>I2C Slave Address Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
                Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs&gt;&gt; for a complete list of these reserved values.</description>
              <name>IC_SAR</name>
            </field>
          </fields>
          <name>IC_SAR</name>
          <resetValue>0x00000055</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n
            The size of the register changes as follows:\n\n
            Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n
                Reset value : 0x0\n\n
                NOTE:  In case of APB_DATA_WIDTH=8,\n\n
                1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n
                2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n
                3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Sequential data byte received</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Non sequential data byte received</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FIRST_DATA_BYTE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>This bit controls whether a RESTART is issued before the byte is sent or received.\n\n
                1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
                0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Don't Issue RESTART before this command</description>
                  <name>DISABLE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Issue RESTART before this command</description>
                  <name>ENABLE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>RESTART</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>This bit controls whether a STOP is issued after the byte is sent or received.\n\n
                - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Don't Issue STOP after this command</description>
                  <name>DISABLE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Issue STOP after this command</description>
                  <name>ENABLE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>STOP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n
                When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n
                When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master Write Command</description>
                  <name>WRITE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master Read Command</description>
                  <name>READ</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>CMD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n
                Reset value: 0x0</description>
              <name>DAT</name>
            </field>
          </fields>
          <name>IC_DATA_CMD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Standard Speed I2C Clock SCL High Count Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n
                NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.</description>
              <name>IC_SS_SCL_HCNT</name>
            </field>
          </fields>
          <name>IC_SS_SCL_HCNT</name>
          <resetValue>0x00000028</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Standard Speed I2C Clock SCL Low Count Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n
                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.</description>
              <name>IC_SS_SCL_LCNT</name>
            </field>
          </fields>
          <name>IC_SS_SCL_LCNT</name>
          <resetValue>0x0000002f</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.</description>
              <name>IC_FS_SCL_HCNT</name>
            </field>
          </fields>
          <name>IC_FS_SCL_HCNT</name>
          <resetValue>0x00000006</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n
                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.</description>
              <name>IC_FS_SCL_LCNT</name>
            </field>
          </fields>
          <name>IC_FS_SCL_LCNT</name>
          <resetValue>0x0000000d</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>I2C Interrupt Status Register\n\n
            Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_RESTART_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_RESTART_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RESTART_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_GEN_CALL interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_GEN_CALL interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_GEN_CALL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_START_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_START_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_START_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_STOP_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_STOP_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_STOP_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_ACTIVITY interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_ACTIVITY interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_ACTIVITY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_RX_DONE interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_RX_DONE interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RX_DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_TX_ABRT interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_TX_ABRT interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_TX_ABRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_RD_REQ interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_RD_REQ interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RD_REQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_TX_EMPTY interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_TX_EMPTY interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_TX_EMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_TX_OVER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_TX_OVER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_TX_OVER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_RX_FULL interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_RX_FULL interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RX_FULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>R_RX_OVER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>R_RX_OVER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RX_OVER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>R_RX_UNDER</name>
            </field>
          </fields>
          <name>IC_INTR_STAT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>I2C Interrupt Mask Register.\n\n
            These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RESTART_DET interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RESTART_DET interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RESTART_DET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>GEN_CALL interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>GEN_CALL interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_GEN_CALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>START_DET interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>START_DET interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_START_DET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>STOP_DET interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>STOP_DET interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_STOP_DET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>ACTIVITY interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>ACTIVITY interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_ACTIVITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_DONE interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_DONE interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RX_DONE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_ABORT interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_ABORT interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_TX_ABRT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RD_REQ interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RD_REQ interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RD_REQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_EMPTY interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_EMPTY interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_TX_EMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_OVER interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_OVER interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_TX_OVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_FULL interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_FULL interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RX_FULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_OVER interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_OVER interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RX_OVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
                Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is masked</description>
                  <name>ENABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is unmasked</description>
                  <name>DISABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>M_RX_UNDER</name>
            </field>
          </fields>
          <name>IC_INTR_MASK</name>
          <resetValue>0x000008ff</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>I2C Raw Interrupt Status Register\n\n
            Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
                Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RESTART_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RESTART_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RESTART_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>GEN_CALL interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>GEN_CALL interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>GEN_CALL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>START_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>START_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>START_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
                In Slave Mode: - If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>STOP_DET interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>STOP_DET interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STOP_DET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RAW_INTR_ACTIVITY interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RAW_INTR_ACTIVITY interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ACTIVITY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_DONE interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_DONE interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RX_DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n
                Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_ABRT interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_ABRT interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TX_ABRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RD_REQ interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RD_REQ interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RD_REQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n
                Reset value: 0x0.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_EMPTY interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_EMPTY interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TX_EMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>TX_OVER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>TX_OVER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TX_OVER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_FULL interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_FULL interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RX_FULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
                Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_OVER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_OVER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RX_OVER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is inactive</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>RX_UNDER interrupt is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RX_UNDER</name>
            </field>
          </fields>
          <name>IC_RAW_INTR_STAT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>I2C Receive FIFO Threshold Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive FIFO Threshold Level.\n\n
                Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.</description>
              <name>RX_TL</name>
            </field>
          </fields>
          <name>IC_RX_TL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>I2C Transmit FIFO Threshold Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit FIFO Threshold Level.\n\n
                Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.</description>
              <name>TX_TL</name>
            </field>
          </fields>
          <name>IC_TX_TL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Clear Combined and Individual Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
                Reset value: 0x0</description>
              <name>CLR_INTR</name>
            </field>
          </fields>
          <name>IC_CLR_INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Clear RX_UNDER Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_RX_UNDER</name>
            </field>
          </fields>
          <name>IC_CLR_RX_UNDER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Clear RX_OVER Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_RX_OVER</name>
            </field>
          </fields>
          <name>IC_CLR_RX_OVER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>Clear TX_OVER Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_TX_OVER</name>
            </field>
          </fields>
          <name>IC_CLR_TX_OVER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Clear RD_REQ Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_RD_REQ</name>
            </field>
          </fields>
          <name>IC_CLR_RD_REQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Clear TX_ABRT Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
                Reset value: 0x0</description>
              <name>CLR_TX_ABRT</name>
            </field>
          </fields>
          <name>IC_CLR_TX_ABRT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Clear RX_DONE Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_RX_DONE</name>
            </field>
          </fields>
          <name>IC_CLR_RX_DONE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Clear ACTIVITY Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_ACTIVITY</name>
            </field>
          </fields>
          <name>IC_CLR_ACTIVITY</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Clear STOP_DET Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_STOP_DET</name>
            </field>
          </fields>
          <name>IC_CLR_STOP_DET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Clear START_DET Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_START_DET</name>
            </field>
          </fields>
          <name>IC_CLR_START_DET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>Clear GEN_CALL Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_GEN_CALL</name>
            </field>
          </fields>
          <name>IC_CLR_GEN_CALL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>I2C Enable Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Tx Command execution not blocked</description>
                  <name>NOT_BLOCKED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Tx Command execution blocked</description>
                  <name>BLOCKED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TX_CMD_BLOCK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n
                For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>ABORT operation not in progress</description>
                  <name>DISABLE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>ABORT operation in progress</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABORT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n
                When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n
                In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>I2C is disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>I2C is enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENABLE</name>
            </field>
          </fields>
          <name>IC_ENABLE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>I2C Status Register\n\n
            This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n
            When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave is idle</description>
                  <name>IDLE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave not idle</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SLV_ACTIVITY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master is idle</description>
                  <name>IDLE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master not idle</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>MST_ACTIVITY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Rx FIFO not full</description>
                  <name>NOT_FULL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Rx FIFO is full</description>
                  <name>FULL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Rx FIFO is empty</description>
                  <name>EMPTY</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Rx FIFO not empty</description>
                  <name>NOT_EMPTY</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RFNE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Tx FIFO not empty</description>
                  <name>NON_EMPTY</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Tx FIFO is empty</description>
                  <name>EMPTY</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TFE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Tx FIFO is full</description>
                  <name>FULL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Tx FIFO not full</description>
                  <name>NOT_FULL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TFNF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>I2C Activity Status. Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>I2C is idle</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>I2C is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ACTIVITY</name>
            </field>
          </fields>
          <name>IC_STATUS</name>
          <resetValue>0x00000006</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <description>Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n
                Reset value: 0x0</description>
              <name>TXFLR</name>
            </field>
          </fields>
          <name>IC_TXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <description>Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n
                Reset value: 0x0</description>
              <name>RXFLR</name>
            </field>
          </fields>
          <name>IC_RXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>I2C SDA Hold Time Length Register\n\n
            The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
            The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
            Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
            The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n
            The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:16]</bitRange>
              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n
                Reset value: IC_DEFAULT_SDA_HOLD[23:16].</description>
              <name>IC_SDA_RX_HOLD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n
                Reset value: IC_DEFAULT_SDA_HOLD[15:0].</description>
              <name>IC_SDA_TX_HOLD</name>
            </field>
          </fields>
          <name>IC_SDA_HOLD</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>I2C Transmit Abort Source Register\n\n
            This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n
            Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:23]</bitRange>
              <description>This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
              <name>TX_FLUSH_CNT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Transfer abort detected by master- scenario not present</description>
                  <name>ABRT_USER_ABRT_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Transfer abort detected by master</description>
                  <name>ABRT_USER_ABRT_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_USER_ABRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <description>1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Slave-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave trying to transmit to remote master in read mode- scenario not present</description>
                  <name>ABRT_SLVRD_INTX_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave trying to transmit to remote master in read mode</description>
                  <name>ABRT_SLVRD_INTX_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_SLVRD_INTX</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <description>This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Slave-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave lost arbitration to remote master- scenario not present</description>
                  <name>ABRT_SLV_ARBLOST_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave lost arbitration to remote master</description>
                  <name>ABRT_SLV_ARBLOST_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_SLV_ARBLOST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Slave-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave flushes existing data in TX-FIFO upon getting read command- scenario not present</description>
                  <name>ABRT_SLVFLUSH_TXFIFO_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave flushes existing data in TX-FIFO upon getting read command</description>
                  <name>ABRT_SLVFLUSH_TXFIFO_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_SLVFLUSH_TXFIFO</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master or Slave-Transmitter lost arbitration- scenario not present</description>
                  <name>ABRT_LOST_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master or Slave-Transmitter lost arbitration</description>
                  <name>ABRT_LOST_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ARB_LOST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>User initiating master operation when MASTER disabled- scenario not present</description>
                  <name>ABRT_MASTER_DIS_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>User initiating master operation when MASTER disabled</description>
                  <name>ABRT_MASTER_DIS_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_MASTER_DIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Master not trying to read in 10Bit addressing mode when RESTART disabled</description>
                  <name>ABRT_10B_RD_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Master trying to read in 10Bit addressing mode when RESTART disabled</description>
                  <name>ABRT_10B_RD_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_10B_RD_NORSTRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>User trying to send START byte when RESTART disabled- scenario not present</description>
                  <name>ABRT_SBYTE_NORSTRT_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>User trying to send START byte when RESTART disabled</description>
                  <name>ABRT_SBYTE_NORSTRT_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_SBYTE_NORSTRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>User trying to switch Master to HS mode when RESTART disabled- scenario not present</description>
                  <name>ABRT_HS_NORSTRT_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>User trying to switch Master to HS mode when RESTART disabled</description>
                  <name>ABRT_HS_NORSTRT_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_HS_NORSTRT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>ACK detected for START byte- scenario not present</description>
                  <name>ABRT_SBYTE_ACKDET_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>ACK detected for START byte</description>
                  <name>ABRT_SBYTE_ACKDET_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_SBYTE_ACKDET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>HS Master code ACKed in HS Mode- scenario not present</description>
                  <name>ABRT_HS_ACK_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>HS Master code ACKed in HS Mode</description>
                  <name>ABRT_HS_ACK_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_HS_ACKDET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>GCALL is followed by read from bus-scenario not present</description>
                  <name>ABRT_GCALL_READ_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>GCALL is followed by read from bus</description>
                  <name>ABRT_GCALL_READ_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_GCALL_READ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>GCALL not ACKed by any slave-scenario not present</description>
                  <name>ABRT_GCALL_NOACK_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>GCALL not ACKed by any slave</description>
                  <name>ABRT_GCALL_NOACK_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_GCALL_NOACK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Transmitted data non-ACKed by addressed slave-scenario not present</description>
                  <name>ABRT_TXDATA_NOACK_VOID</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Transmitted data not ACKed by addressed slave</description>
                  <name>ABRT_TXDATA_NOACK_GENERATED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_TXDATA_NOACK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>This abort is not generated</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Byte 2 of 10Bit Address not ACKed by any slave</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_10ADDR2_NOACK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>This abort is not generated</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Byte 1 of 10Bit Address not ACKed by any slave</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_10ADDR1_NOACK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n
                Reset value: 0x0\n\n
                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>This abort is not generated</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>This abort is generated because of NOACK for 7-bit address</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ABRT_7B_ADDR_NOACK</name>
            </field>
          </fields>
          <name>IC_TX_ABRT_SOURCE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Generate Slave Data NACK Register\n\n
            The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n
            A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n
                When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave receiver generates NACK normally</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave receiver generates NACK upon data reception only</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>NACK</name>
            </field>
          </fields>
          <name>IC_SLV_DATA_NACK_ONLY</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>DMA Control Register\n\n
            The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>transmit FIFO DMA channel disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Transmit FIFO DMA channel enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TDMAE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Receive FIFO DMA channel disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Receive FIFO DMA channel enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RDMAE</name>
            </field>
          </fields>
          <name>IC_DMA_CR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>DMA Transmit Data Level Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
                Reset value: 0x0</description>
              <name>DMATDL</name>
            </field>
          </fields>
          <name>IC_DMA_TDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>I2C Receive Data Level Register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n
                Reset value: 0x0</description>
              <name>DMARDL</name>
            </field>
          </fields>
          <name>IC_DMA_RDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>I2C SDA Setup Register\n\n
            This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n
            Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n
            Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.</description>
              <name>SDA_SETUP</name>
            </field>
          </fields>
          <name>IC_SDA_SETUP</name>
          <resetValue>0x00000064</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>I2C ACK General Call Register\n\n
            The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n
            This register is applicable only when the DW_apb_i2c is in slave mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Generate NACK for a General Call</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Generate ACK for a General Call</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ACK_GEN_CALL</name>
            </field>
          </fields>
          <name>IC_ACK_GENERAL_CALL</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>I2C Enable Status Register\n\n
            The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n
            If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n
            If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n
            Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n
                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n
                When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n
                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave RX Data is not lost</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave RX Data is lost</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SLV_RX_DATA_LOST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n
                (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n
                OR,\n\n
                (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n
                When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n
                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n
                When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n
                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Slave is disabled when it is idle</description>
                  <name>INACTIVE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Slave is disabled when it is active</description>
                  <name>ACTIVE</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SLV_DISABLED_WHILE_BUSY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
                Reset value: 0x0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>I2C disabled</description>
                  <name>DISABLED</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>I2C enabled</description>
                  <name>ENABLED</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>IC_EN</name>
            </field>
          </fields>
          <name>IC_ENABLE_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>I2C SS, FS or FM+ spike suppression limit\n\n
            This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.</description>
              <name>IC_FS_SPKLEN</name>
            </field>
          </fields>
          <name>IC_FS_SPKLEN</name>
          <resetValue>0x00000007</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>Clear RESTART_DET Interrupt Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n
                Reset value: 0x0</description>
              <name>CLR_RESTART_DET</name>
            </field>
          </fields>
          <name>IC_CLR_RESTART_DET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>Component Parameter Register 1\n\n
            Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:16]</bitRange>
              <description>TX Buffer Depth = 16</description>
              <name>TX_BUFFER_DEPTH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:8]</bitRange>
              <description>RX Buffer Depth = 16</description>
              <name>RX_BUFFER_DEPTH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Encoded parameters not visible</description>
              <name>ADD_ENCODED_PARAMS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>DMA handshaking signals are enabled</description>
              <name>HAS_DMA</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>COMBINED Interrupt outputs</description>
              <name>INTR_IO</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Programmable count values for each mode.</description>
              <name>HC_COUNT_VALUES</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:2]</bitRange>
              <description>MAX SPEED MODE = FAST MODE</description>
              <name>MAX_SPEED_MODE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:0]</bitRange>
              <description>APB data bus width is 32 bits</description>
              <name>APB_DATA_WIDTH</name>
            </field>
          </fields>
          <name>IC_COMP_PARAM_1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>I2C Component Version Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <name>IC_COMP_VERSION</name>
            </field>
          </fields>
          <name>IC_COMP_VERSION</name>
          <resetValue>0x3230312a</resetValue>
        </register>
        <register>
          <addressOffset>0x00fc</addressOffset>
          <description>I2C Component Type Register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <description>Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.</description>
              <name>IC_COMP_TYPE</name>
            </field>
          </fields>
          <name>IC_COMP_TYPE</name>
          <resetValue>0x44570140</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral derivedFrom="I2C0">
      <baseAddress>0x40048000</baseAddress>
      <interrupt>
        <name>I2C1_IRQ</name>
        <value>24</value>
      </interrupt>
      <name>I2C1</name>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4004c000</baseAddress>
      <description>Control and data interface to SAR ADC</description>
      <interrupt>
        <name>ADC_IRQ_FIFO</name>
        <value>22</value>
      </interrupt>
      <name>ADC</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>ADC Control and Status</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:16]</bitRange>
              <description>Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n
                Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n
                The first channel to be sampled will be the one currently indicated by AINSEL.\n
                AINSEL will be updated after each conversion with the newly-selected channel.</description>
              <name>RROBIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:12]</bitRange>
              <description>Select analog mux input. Updated automatically in round-robin mode.</description>
              <name>AINSEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Some past ADC conversion encountered an error. Write 1 to clear.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ERR_STICKY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>The most recent ADC conversion encountered an error; result is undefined or noisy.</description>
              <name>ERR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n
                0 whilst conversion in progress.</description>
              <name>READY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.</description>
              <name>START_MANY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>START_ONCE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Power on temperature sensor. 1 - enabled. 0 - disabled.</description>
              <name>TS_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Power on ADC and enable its clock.\n
                1 - enabled. 0 - disabled.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Result of most recent ADC conversion</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:0]</bitRange>
              <name>RESULT</name>
            </field>
          </fields>
          <name>RESULT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>FIFO control and status</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[27:24]</bitRange>
              <description>DREQ/IRQ asserted when level &gt;= threshold</description>
              <name>THRESH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:16]</bitRange>
              <description>The number of conversion results currently waiting in the FIFO</description>
              <name>LEVEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>1 if the FIFO has been overflowed. Write 1 to clear.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>OVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>1 if the FIFO has been underflowed. Write 1 to clear.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>UNDER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>FULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>EMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>If 1: assert DMA requests when FIFO contains data</description>
              <name>DREQ_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>If 1: conversion error bit appears in the FIFO alongside the result</description>
              <name>ERR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.</description>
              <name>SHIFT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>If 1: write result to the FIFO after each conversion.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>FCS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Conversion result FIFO</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <description>1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.</description>
              <name>ERR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:0]</bitRange>
              <name>VAL</name>
            </field>
          </fields>
          <name>FIFO</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Clock divider. If non-zero, CS_START_MANY will start conversions\n
            at regular intervals rather than back-to-back.\n
            The divider is reset when either of these fields are written.\n
            Total period is 1 + INT + FRAC / 256</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:8]</bitRange>
              <description>Integer part of clock divisor.</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional part of clock divisor. First-order delta-sigma.</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>DIV</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Triggered when the sample FIFO reaches a certain level.\n
                This level can be programmed via the FCS_THRESH field.</description>
              <name>FIFO</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Triggered when the sample FIFO reaches a certain level.\n
                This level can be programmed via the FCS_THRESH field.</description>
              <name>FIFO</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Triggered when the sample FIFO reaches a certain level.\n
                This level can be programmed via the FCS_THRESH field.</description>
              <name>FIFO</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Triggered when the sample FIFO reaches a certain level.\n
                This level can be programmed via the FCS_THRESH field.</description>
              <name>FIFO</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>2</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40050000</baseAddress>
      <description>Simple PWM</description>
      <interrupt>
        <name>PWM_IRQ_WRAP</name>
        <value>4</value>
      </interrupt>
      <name>PWM</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH0_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH0_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH0_CTR</name>
            </field>
          </fields>
          <name>CH0_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH0_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH0_TOP</name>
            </field>
          </fields>
          <name>CH0_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH1_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH1_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH1_CTR</name>
            </field>
          </fields>
          <name>CH1_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH1_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH1_TOP</name>
            </field>
          </fields>
          <name>CH1_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH2_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH2_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH2_CTR</name>
            </field>
          </fields>
          <name>CH2_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH2_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH2_TOP</name>
            </field>
          </fields>
          <name>CH2_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH3_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH3_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH3_CTR</name>
            </field>
          </fields>
          <name>CH3_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH3_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH3_TOP</name>
            </field>
          </fields>
          <name>CH3_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH4_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH4_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH4_CTR</name>
            </field>
          </fields>
          <name>CH4_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH4_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH4_TOP</name>
            </field>
          </fields>
          <name>CH4_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH5_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH5_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH5_CTR</name>
            </field>
          </fields>
          <name>CH5_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH5_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH5_TOP</name>
            </field>
          </fields>
          <name>CH5_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH6_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH6_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH6_CTR</name>
            </field>
          </fields>
          <name>CH6_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH6_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH6_TOP</name>
            </field>
          </fields>
          <name>CH6_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Control and status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Advance the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running\n
                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_ADV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Retard the phase of the counter by 1 count, while it is running.\n
                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>PH_RET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Free-running counting at rate dictated by fractional divider</description>
                  <name>div</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Fractional divider operation is gated by the PWM B pin.</description>
                  <name>level</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each rising edge of the PWM B pin.</description>
                  <name>rise</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Counter advances with each falling edge of the PWM B pin.</description>
                  <name>fall</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIVMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Invert output B</description>
              <name>B_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Invert output A</description>
              <name>A_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
              <name>PH_CORRECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the PWM channel.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH7_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>INT and FRAC form a fixed-point fractional number.\n
            Counting rate is system clock frequency divided by this number.\n
            Fractional division uses simple 1st-order sigma-delta.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CH7_DIV</name>
          <resetValue>0x00000010</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Direct access to the PWM counter</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH7_CTR</name>
            </field>
          </fields>
          <name>CH7_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Counter compare values</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>B</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>A</name>
            </field>
          </fields>
          <name>CH7_CC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>Counter wrap value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CH7_TOP</name>
            </field>
          </fields>
          <name>CH7_TOP</name>
          <resetValue>0x0000ffff</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>This register aliases the CSR_EN bits for all channels.\n
            Writing to this register allows multiple channels to be enabled\n
            or disabled simultaneously, so they can run in perfect sync.\n
            For each channel, there is only one physical EN register bit,\n
            which can be accessed through here or CHx_CSR.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>CH7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>CH6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>CH5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>CH4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>CH3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>CH2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>CH1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CH0</name>
            </field>
          </fields>
          <name>EN</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH0</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>CH7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>CH6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>CH5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>CH4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>CH3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>CH2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>CH1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CH0</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>CH7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>CH6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>CH5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>CH4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>CH3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>CH2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>CH1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CH0</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>CH7</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>CH6</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>CH5</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>CH4</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>CH3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>CH2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>CH1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>CH0</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40054000</baseAddress>
      <description>Controls time and alarms\n
        time is a 64 bit value indicating the time in usec since power-on\n
        timeh is the top 32 bits of time &amp; timel is the bottom 32 bits\n
        to change time write to timelw before timehw\n
        to read time read from timelr before timehr\n
        An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n
        When an alarm is pending, the corresponding alarm_running signal will be high\n
        An alarm can be cancelled before it has finished by clearing the alarm_enable\n
        When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n
        To clear the interrupt write a 1 to the corresponding alarm_irq</description>
      <interrupt>
        <name>TIMER_IRQ_0</name>
        <value>0</value>
      </interrupt>
      <interrupt>
        <name>TIMER_IRQ_1</name>
        <value>1</value>
      </interrupt>
      <interrupt>
        <name>TIMER_IRQ_2</name>
        <value>2</value>
      </interrupt>
      <interrupt>
        <name>TIMER_IRQ_3</name>
        <value>3</value>
      </interrupt>
      <name>TIMER</name>
      <registers>
        <register>
          <access>write-only</access>
          <addressOffset>0x0000</addressOffset>
          <description>Write to bits 63:32 of time\n
            always write timelw before timehw</description>
          <name>TIMEHW</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x0004</addressOffset>
          <description>Write to bits 31:0 of time\n
            writes do not get copied to time until timehw is written</description>
          <name>TIMELW</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0008</addressOffset>
          <description>Read from bits 63:32 of time\n
            always read timelr before timehr</description>
          <name>TIMEHR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x000c</addressOffset>
          <description>Read from bits 31:0 of time</description>
          <name>TIMELR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0010</addressOffset>
          <description>Arm alarm 0, and configure the time it will fire.\n
            Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n
            The alarm will disarm itself once it fires, and can\n
            be disarmed early using the ARMED status register.</description>
          <name>ALARM0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0014</addressOffset>
          <description>Arm alarm 1, and configure the time it will fire.\n
            Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n
            The alarm will disarm itself once it fires, and can\n
            be disarmed early using the ARMED status register.</description>
          <name>ALARM1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0018</addressOffset>
          <description>Arm alarm 2, and configure the time it will fire.\n
            Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n
            The alarm will disarm itself once it fires, and can\n
            be disarmed early using the ARMED status register.</description>
          <name>ALARM2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x001c</addressOffset>
          <description>Arm alarm 3, and configure the time it will fire.\n
            Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n
            The alarm will disarm itself once it fires, and can\n
            be disarmed early using the ARMED status register.</description>
          <name>ALARM3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Indicates the armed/disarmed status of each alarm.\n
            A write to the corresponding ALARMx register arms the alarm.\n
            Alarms automatically disarm upon firing, but writing ones here\n
            will disarm immediately without waiting to fire.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ARMED</name>
            </field>
          </fields>
          <name>ARMED</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0024</addressOffset>
          <description>Raw read from bits 63:32 of time (no side effects)</description>
          <name>TIMERAWH</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0028</addressOffset>
          <description>Raw read from bits 31:0 of time (no side effects)</description>
          <name>TIMERAWL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Set bits high to enable pause when the corresponding debug ports are active</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Pause when processor 1 is in debug mode</description>
              <name>DBG1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Pause when processor 0 is in debug mode</description>
              <name>DBG0</name>
            </field>
          </fields>
          <name>DBGPAUSE</name>
          <resetValue>0x00000007</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Set high to pause the timer</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>PAUSE</name>
            </field>
          </fields>
          <name>PAUSE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ALARM_3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ALARM_2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ALARM_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ALARM_0</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>ALARM_3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>ALARM_2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>ALARM_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>ALARM_0</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>ALARM_3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>ALARM_2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>ALARM_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>ALARM_0</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>ALARM_3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>ALARM_2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>ALARM_1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>ALARM_0</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40058000</baseAddress>
      <name>WATCHDOG</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Watchdog control\n
            The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n
            The watchdog can be triggered in software.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Trigger a watchdog reset</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>TRIGGER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>When not enabled the watchdog timer is paused</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Pause the watchdog timer when processor 1 is in debug mode</description>
              <name>PAUSE_DBG1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Pause the watchdog timer when processor 0 is in debug mode</description>
              <name>PAUSE_DBG0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>Pause the watchdog timer when JTAG is accessing the bus fabric</description>
              <name>PAUSE_JTAG</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:0]</bitRange>
              <description>Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered</description>
              <name>TIME</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x07000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[23:0]</bitRange>
              <name>LOAD</name>
            </field>
          </fields>
          <name>LOAD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>FORCE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>TIMER</name>
            </field>
          </fields>
          <name>REASON</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x000c</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0010</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0014</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0018</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x001c</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH4</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0020</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH5</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0024</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH6</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0028</addressOffset>
          <description>Scratch register. Information persists through soft reset of the chip.</description>
          <name>SCRATCH7</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Controls the tick generator</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[19:11]</bitRange>
              <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
              <name>COUNT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Is the tick generator running?</description>
              <name>RUNNING</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>start / stop tick generation</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:0]</bitRange>
              <description>Total number of clk_tick cycles before the next tick.</description>
              <name>CYCLES</name>
            </field>
          </fields>
          <name>TICK</name>
          <resetValue>0x00000200</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4005c000</baseAddress>
      <description>Register block to control RTC</description>
      <interrupt>
        <name>RTC_IRQ</name>
        <value>25</value>
      </interrupt>
      <name>RTC</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>CLKDIV_M1</name>
            </field>
          </fields>
          <name>CLKDIV_M1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>RTC setup register 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:12]</bitRange>
              <description>Year</description>
              <name>YEAR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:8]</bitRange>
              <description>Month (1..12)</description>
              <name>MONTH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Day of the month (1..31)</description>
              <name>DAY</name>
            </field>
          </fields>
          <name>SETUP_0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>RTC setup register 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:24]</bitRange>
              <description>Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7</description>
              <name>DOTW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:16]</bitRange>
              <description>Hours</description>
              <name>HOUR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:8]</bitRange>
              <description>Minutes</description>
              <name>MIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>Seconds</description>
              <name>SEC</name>
            </field>
          </fields>
          <name>SETUP_1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>RTC Control and status</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>If set, leapyear is forced off.\n
                Useful for years divisible by 100 but not by 400</description>
              <name>FORCE_NOTLEAPYEAR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Load RTC</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>LOAD</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>RTC enabled (running)</description>
              <name>RTC_ACTIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable RTC</description>
              <name>RTC_ENABLE</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Interrupt setup register 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>MATCH_ACTIVE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Global match enable. Don't change any other value while this one is enabled</description>
              <name>MATCH_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Enable year matching</description>
              <name>YEAR_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Enable month matching</description>
              <name>MONTH_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>Enable day matching</description>
              <name>DAY_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:12]</bitRange>
              <description>Year</description>
              <name>YEAR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:8]</bitRange>
              <description>Month (1..12)</description>
              <name>MONTH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Day of the month (1..31)</description>
              <name>DAY</name>
            </field>
          </fields>
          <name>IRQ_SETUP_0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Interrupt setup register 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable day of the week matching</description>
              <name>DOTW_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Enable hour matching</description>
              <name>HOUR_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Enable minute matching</description>
              <name>MIN_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Enable second matching</description>
              <name>SEC_ENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:24]</bitRange>
              <description>Day of the week</description>
              <name>DOTW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:16]</bitRange>
              <description>Hours</description>
              <name>HOUR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:8]</bitRange>
              <description>Minutes</description>
              <name>MIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>Seconds</description>
              <name>SEC</name>
            </field>
          </fields>
          <name>IRQ_SETUP_1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>RTC register 1.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:12]</bitRange>
              <description>Year</description>
              <name>YEAR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:8]</bitRange>
              <description>Month (1..12)</description>
              <name>MONTH</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <description>Day of the month (1..31)</description>
              <name>DAY</name>
            </field>
          </fields>
          <name>RTC_1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>RTC register 0\n
            Read this before RTC 1!</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[26:24]</bitRange>
              <description>Day of the week</description>
              <name>DOTW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:16]</bitRange>
              <description>Hours</description>
              <name>HOUR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:8]</bitRange>
              <description>Minutes</description>
              <name>MIN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Seconds</description>
              <name>SEC</name>
            </field>
          </fields>
          <name>RTC_0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>RTC</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>RTC</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>RTC</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>RTC</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40060000</baseAddress>
      <name>ROSC</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Ring Oscillator control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:12]</bitRange>
              <description>On power-up this field is initialised to ENABLE\n
                The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n
                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <value>3358</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <value>4011</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:0]</bitRange>
              <description>Controls the number of delay stages in the ROSC ring\n
                LOW uses stages 0 to 7\n
                MEDIUM uses stages 0 to 5\n
                HIGH uses stages 0 to 3\n
                TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n
                The clock output will not glitch when changing the range up one step at a time\n
                The clock output will glitch when changing the range down\n
                Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <value>4004</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MEDIUM</name>
                  <value>4005</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <value>4007</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOOHIGH</name>
                  <value>4006</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FREQ_RANGE</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000aa0</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage\n
            The drive strength has 4 levels determined by the number of bits set\n
            Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n
            0 bits set is the default drive strength\n
            1 bit set doubles the drive strength\n
            2 bits set triples drive strength\n
            3 bits set quadruples drive strength</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Set to 0x9696 to apply the settings\n
                Any other value in this field will set all drive strengths to 0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PASS</name>
                  <value>38550</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PASSWD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:12]</bitRange>
              <description>Stage 3 drive strength</description>
              <name>DS3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:8]</bitRange>
              <description>Stage 2 drive strength</description>
              <name>DS2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:4]</bitRange>
              <description>Stage 1 drive strength</description>
              <name>DS1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:0]</bitRange>
              <description>Stage 0 drive strength</description>
              <name>DS0</name>
            </field>
          </fields>
          <name>FREQA</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>For a detailed description see freqa register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Set to 0x9696 to apply the settings\n
                Any other value in this field will set all drive strengths to 0</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PASS</name>
                  <value>38550</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>PASSWD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:12]</bitRange>
              <description>Stage 7 drive strength</description>
              <name>DS7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:8]</bitRange>
              <description>Stage 6 drive strength</description>
              <name>DS6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:4]</bitRange>
              <description>Stage 5 drive strength</description>
              <name>DS5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:0]</bitRange>
              <description>Stage 4 drive strength</description>
              <name>DS4</name>
            </field>
          </fields>
          <name>FREQB</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x000c</addressOffset>
          <description>Ring Oscillator pause control\n
            This is used to save power by pausing the ROSC\n
            On power-up this field is initialised to WAKE\n
            An invalid write will also select WAKE\n
            Warning: setup the irq before selecting dormant mode</description>
          <name>DORMANT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Controls the output divider</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:0]</bitRange>
              <description>set to 0xaa0 + div where\n
                div = 0 divides by 32\n
                div = 1-31 divides by div\n
                any other value sets div=31\n
                this register resets to div=16</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PASS</name>
                  <value>2720</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DIV</name>
            </field>
          </fields>
          <name>DIV</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Controls the phase shifted output</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:4]</bitRange>
              <description>set to 0xaa\n
                any other value enables the output with shift=0</description>
              <name>PASSWD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>enable the phase-shifted output\n
                this can be changed on-the-fly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>invert the phase-shifted output\n
                this is ignored when div=1</description>
              <name>FLIP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:0]</bitRange>
              <description>phase shift the phase-shifted output by SHIFT input clocks\n
                this can be changed on-the-fly\n
                must be set to 0 before setting div=1</description>
              <name>SHIFT</name>
            </field>
          </fields>
          <name>PHASE</name>
          <resetValue>0x00000008</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Ring Oscillator Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Oscillator is running and stable</description>
              <name>STABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BADWRITE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>post-divider is running\n
                this resets to 0 but transitions to 1 during chip startup</description>
              <name>DIV_RUNNING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Oscillator is enabled but not necessarily running and stable\n
                this resets to 0 but transitions to 1 during chip startup</description>
              <name>ENABLED</name>
            </field>
          </fields>
          <name>STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>RANDOMBIT</name>
            </field>
          </fields>
          <name>RANDOMBIT</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>A down counter running at the ROSC frequency which counts to zero and stops.\n
            To start the counter write a non-zero value.\n
            Can be used for short software pauses when setting up time sensitive hardware.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <name>COUNT</name>
            </field>
          </fields>
          <name>COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40064000</baseAddress>
      <description>control and status for on-chip voltage regulator and chip level reset subsystem</description>
      <name>VREG_AND_CHIP_RESET</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Voltage regulator control and status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>regulation status\n
                0=not in regulation, 1=in regulation</description>
              <name>ROK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:4]</bitRange>
              <description>output voltage select\n
                0000 to 0101 - 0.80V\n
                0110         - 0.85V\n
                0111         - 0.90V\n
                1000         - 0.95V\n
                1001         - 1.00V\n
                1010         - 1.05V\n
                1011         - 1.10V (default)\n
                1100         - 1.15V\n
                1101         - 1.20V\n
                1110         - 1.25V\n
                1111         - 1.30V</description>
              <name>VSEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>high impedance mode select\n
                0=not in high impedance mode, 1=in high impedance mode</description>
              <name>HIZ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>enable\n
                0=not enabled, 1=enabled</description>
              <name>EN</name>
            </field>
          </fields>
          <name>VREG</name>
          <resetValue>0x000000b1</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>brown-out detection control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:4]</bitRange>
              <description>threshold select\n
                0000 - 0.473V\n
                0001 - 0.516V\n
                0010 - 0.559V\n
                0011 - 0.602V\n
                0100 - 0.645V\n
                0101 - 0.688V\n
                0110 - 0.731V\n
                0111 - 0.774V\n
                1000 - 0.817V\n
                1001 - 0.860V (default)\n
                1010 - 0.903V\n
                1011 - 0.946V\n
                1100 - 0.989V\n
                1101 - 1.032V\n
                1110 - 1.075V\n
                1111 - 1.118V</description>
              <name>VSEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>enable\n
                0=not enabled, 1=enabled</description>
              <name>EN</name>
            </field>
          </fields>
          <name>BOD</name>
          <resetValue>0x00000091</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Chip reset control and status</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>This is set by psm_restart from the debugger.\n
                Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n
                In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>PSM_RESTART_FLAG</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <description>Last reset was from the debug port</description>
              <name>HAD_PSM_RESTART</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Last reset was from the RUN pin</description>
              <name>HAD_RUN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Last reset was from the power-on reset or brown-out detection blocks</description>
              <name>HAD_POR</name>
            </field>
          </fields>
          <name>CHIP_RESET</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4006c000</baseAddress>
      <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description>
      <name>TBMAN</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Indicates the type of platform in use</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Indicates the platform is an FPGA</description>
              <name>FPGA</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Indicates the platform is an ASIC</description>
              <name>ASIC</name>
            </field>
          </fields>
          <name>PLATFORM</name>
          <resetValue>0x00000005</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x50000000</baseAddress>
      <description>DMA with separate read and write masters</description>
      <interrupt>
        <name>DMA_IRQ_0</name>
        <value>11</value>
      </interrupt>
      <interrupt>
        <name>DMA_IRQ_1</name>
        <value>12</value>
      </interrupt>
      <name>DMA</name>
      <registers>
        <register>
          <access>read-write</access>
          <addressOffset>0x0000</addressOffset>
          <description>DMA Channel 0 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH0_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0004</addressOffset>
          <description>DMA Channel 0 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH0_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0008</addressOffset>
          <description>DMA Channel 0 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH0_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>DMA Channel 0 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH0_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0010</addressOffset>
          <description>Alias for channel 0 CTRL register</description>
          <name>CH0_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0014</addressOffset>
          <description>Alias for channel 0 READ_ADDR register</description>
          <name>CH0_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0018</addressOffset>
          <description>Alias for channel 0 WRITE_ADDR register</description>
          <name>CH0_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x001c</addressOffset>
          <description>Alias for channel 0 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH0_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0020</addressOffset>
          <description>Alias for channel 0 CTRL register</description>
          <name>CH0_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0024</addressOffset>
          <description>Alias for channel 0 TRANS_COUNT register</description>
          <name>CH0_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0028</addressOffset>
          <description>Alias for channel 0 READ_ADDR register</description>
          <name>CH0_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x002c</addressOffset>
          <description>Alias for channel 0 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH0_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0030</addressOffset>
          <description>Alias for channel 0 CTRL register</description>
          <name>CH0_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0034</addressOffset>
          <description>Alias for channel 0 WRITE_ADDR register</description>
          <name>CH0_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0038</addressOffset>
          <description>Alias for channel 0 TRANS_COUNT register</description>
          <name>CH0_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x003c</addressOffset>
          <description>Alias for channel 0 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH0_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0040</addressOffset>
          <description>DMA Channel 1 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0044</addressOffset>
          <description>DMA Channel 1 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0048</addressOffset>
          <description>DMA Channel 1 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH1_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>DMA Channel 1 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH1_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0050</addressOffset>
          <description>Alias for channel 1 CTRL register</description>
          <name>CH1_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0054</addressOffset>
          <description>Alias for channel 1 READ_ADDR register</description>
          <name>CH1_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0058</addressOffset>
          <description>Alias for channel 1 WRITE_ADDR register</description>
          <name>CH1_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x005c</addressOffset>
          <description>Alias for channel 1 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH1_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0060</addressOffset>
          <description>Alias for channel 1 CTRL register</description>
          <name>CH1_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0064</addressOffset>
          <description>Alias for channel 1 TRANS_COUNT register</description>
          <name>CH1_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0068</addressOffset>
          <description>Alias for channel 1 READ_ADDR register</description>
          <name>CH1_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x006c</addressOffset>
          <description>Alias for channel 1 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH1_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0070</addressOffset>
          <description>Alias for channel 1 CTRL register</description>
          <name>CH1_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0074</addressOffset>
          <description>Alias for channel 1 WRITE_ADDR register</description>
          <name>CH1_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0078</addressOffset>
          <description>Alias for channel 1 TRANS_COUNT register</description>
          <name>CH1_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x007c</addressOffset>
          <description>Alias for channel 1 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH1_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0080</addressOffset>
          <description>DMA Channel 2 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0084</addressOffset>
          <description>DMA Channel 2 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH2_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0088</addressOffset>
          <description>DMA Channel 2 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>DMA Channel 2 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH2_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0090</addressOffset>
          <description>Alias for channel 2 CTRL register</description>
          <name>CH2_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0094</addressOffset>
          <description>Alias for channel 2 READ_ADDR register</description>
          <name>CH2_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0098</addressOffset>
          <description>Alias for channel 2 WRITE_ADDR register</description>
          <name>CH2_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x009c</addressOffset>
          <description>Alias for channel 2 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH2_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00a0</addressOffset>
          <description>Alias for channel 2 CTRL register</description>
          <name>CH2_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00a4</addressOffset>
          <description>Alias for channel 2 TRANS_COUNT register</description>
          <name>CH2_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00a8</addressOffset>
          <description>Alias for channel 2 READ_ADDR register</description>
          <name>CH2_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00ac</addressOffset>
          <description>Alias for channel 2 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH2_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00b0</addressOffset>
          <description>Alias for channel 2 CTRL register</description>
          <name>CH2_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00b4</addressOffset>
          <description>Alias for channel 2 WRITE_ADDR register</description>
          <name>CH2_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00b8</addressOffset>
          <description>Alias for channel 2 TRANS_COUNT register</description>
          <name>CH2_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00bc</addressOffset>
          <description>Alias for channel 2 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH2_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c0</addressOffset>
          <description>DMA Channel 3 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH3_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c4</addressOffset>
          <description>DMA Channel 3 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c8</addressOffset>
          <description>DMA Channel 3 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00cc</addressOffset>
          <description>DMA Channel 3 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH3_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00d0</addressOffset>
          <description>Alias for channel 3 CTRL register</description>
          <name>CH3_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00d4</addressOffset>
          <description>Alias for channel 3 READ_ADDR register</description>
          <name>CH3_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00d8</addressOffset>
          <description>Alias for channel 3 WRITE_ADDR register</description>
          <name>CH3_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00dc</addressOffset>
          <description>Alias for channel 3 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH3_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00e0</addressOffset>
          <description>Alias for channel 3 CTRL register</description>
          <name>CH3_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00e4</addressOffset>
          <description>Alias for channel 3 TRANS_COUNT register</description>
          <name>CH3_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00e8</addressOffset>
          <description>Alias for channel 3 READ_ADDR register</description>
          <name>CH3_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00ec</addressOffset>
          <description>Alias for channel 3 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH3_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00f0</addressOffset>
          <description>Alias for channel 3 CTRL register</description>
          <name>CH3_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00f4</addressOffset>
          <description>Alias for channel 3 WRITE_ADDR register</description>
          <name>CH3_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00f8</addressOffset>
          <description>Alias for channel 3 TRANS_COUNT register</description>
          <name>CH3_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00fc</addressOffset>
          <description>Alias for channel 3 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH3_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0100</addressOffset>
          <description>DMA Channel 4 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH4_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0104</addressOffset>
          <description>DMA Channel 4 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH4_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0108</addressOffset>
          <description>DMA Channel 4 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH4_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x010c</addressOffset>
          <description>DMA Channel 4 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH4_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0110</addressOffset>
          <description>Alias for channel 4 CTRL register</description>
          <name>CH4_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0114</addressOffset>
          <description>Alias for channel 4 READ_ADDR register</description>
          <name>CH4_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0118</addressOffset>
          <description>Alias for channel 4 WRITE_ADDR register</description>
          <name>CH4_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x011c</addressOffset>
          <description>Alias for channel 4 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH4_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0120</addressOffset>
          <description>Alias for channel 4 CTRL register</description>
          <name>CH4_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0124</addressOffset>
          <description>Alias for channel 4 TRANS_COUNT register</description>
          <name>CH4_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0128</addressOffset>
          <description>Alias for channel 4 READ_ADDR register</description>
          <name>CH4_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x012c</addressOffset>
          <description>Alias for channel 4 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH4_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0130</addressOffset>
          <description>Alias for channel 4 CTRL register</description>
          <name>CH4_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0134</addressOffset>
          <description>Alias for channel 4 WRITE_ADDR register</description>
          <name>CH4_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0138</addressOffset>
          <description>Alias for channel 4 TRANS_COUNT register</description>
          <name>CH4_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x013c</addressOffset>
          <description>Alias for channel 4 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH4_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0140</addressOffset>
          <description>DMA Channel 5 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH5_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0144</addressOffset>
          <description>DMA Channel 5 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH5_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0148</addressOffset>
          <description>DMA Channel 5 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH5_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x014c</addressOffset>
          <description>DMA Channel 5 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH5_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0150</addressOffset>
          <description>Alias for channel 5 CTRL register</description>
          <name>CH5_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0154</addressOffset>
          <description>Alias for channel 5 READ_ADDR register</description>
          <name>CH5_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0158</addressOffset>
          <description>Alias for channel 5 WRITE_ADDR register</description>
          <name>CH5_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x015c</addressOffset>
          <description>Alias for channel 5 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH5_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0160</addressOffset>
          <description>Alias for channel 5 CTRL register</description>
          <name>CH5_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0164</addressOffset>
          <description>Alias for channel 5 TRANS_COUNT register</description>
          <name>CH5_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0168</addressOffset>
          <description>Alias for channel 5 READ_ADDR register</description>
          <name>CH5_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x016c</addressOffset>
          <description>Alias for channel 5 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH5_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0170</addressOffset>
          <description>Alias for channel 5 CTRL register</description>
          <name>CH5_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0174</addressOffset>
          <description>Alias for channel 5 WRITE_ADDR register</description>
          <name>CH5_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0178</addressOffset>
          <description>Alias for channel 5 TRANS_COUNT register</description>
          <name>CH5_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x017c</addressOffset>
          <description>Alias for channel 5 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH5_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0180</addressOffset>
          <description>DMA Channel 6 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH6_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0184</addressOffset>
          <description>DMA Channel 6 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH6_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0188</addressOffset>
          <description>DMA Channel 6 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH6_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x018c</addressOffset>
          <description>DMA Channel 6 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH6_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0190</addressOffset>
          <description>Alias for channel 6 CTRL register</description>
          <name>CH6_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0194</addressOffset>
          <description>Alias for channel 6 READ_ADDR register</description>
          <name>CH6_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0198</addressOffset>
          <description>Alias for channel 6 WRITE_ADDR register</description>
          <name>CH6_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x019c</addressOffset>
          <description>Alias for channel 6 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH6_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01a0</addressOffset>
          <description>Alias for channel 6 CTRL register</description>
          <name>CH6_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01a4</addressOffset>
          <description>Alias for channel 6 TRANS_COUNT register</description>
          <name>CH6_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01a8</addressOffset>
          <description>Alias for channel 6 READ_ADDR register</description>
          <name>CH6_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01ac</addressOffset>
          <description>Alias for channel 6 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH6_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01b0</addressOffset>
          <description>Alias for channel 6 CTRL register</description>
          <name>CH6_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01b4</addressOffset>
          <description>Alias for channel 6 WRITE_ADDR register</description>
          <name>CH6_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01b8</addressOffset>
          <description>Alias for channel 6 TRANS_COUNT register</description>
          <name>CH6_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01bc</addressOffset>
          <description>Alias for channel 6 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH6_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01c0</addressOffset>
          <description>DMA Channel 7 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH7_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01c4</addressOffset>
          <description>DMA Channel 7 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH7_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01c8</addressOffset>
          <description>DMA Channel 7 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH7_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x01cc</addressOffset>
          <description>DMA Channel 7 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH7_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01d0</addressOffset>
          <description>Alias for channel 7 CTRL register</description>
          <name>CH7_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01d4</addressOffset>
          <description>Alias for channel 7 READ_ADDR register</description>
          <name>CH7_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01d8</addressOffset>
          <description>Alias for channel 7 WRITE_ADDR register</description>
          <name>CH7_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01dc</addressOffset>
          <description>Alias for channel 7 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH7_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01e0</addressOffset>
          <description>Alias for channel 7 CTRL register</description>
          <name>CH7_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01e4</addressOffset>
          <description>Alias for channel 7 TRANS_COUNT register</description>
          <name>CH7_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01e8</addressOffset>
          <description>Alias for channel 7 READ_ADDR register</description>
          <name>CH7_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01ec</addressOffset>
          <description>Alias for channel 7 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH7_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01f0</addressOffset>
          <description>Alias for channel 7 CTRL register</description>
          <name>CH7_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01f4</addressOffset>
          <description>Alias for channel 7 WRITE_ADDR register</description>
          <name>CH7_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01f8</addressOffset>
          <description>Alias for channel 7 TRANS_COUNT register</description>
          <name>CH7_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x01fc</addressOffset>
          <description>Alias for channel 7 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH7_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0200</addressOffset>
          <description>DMA Channel 8 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH8_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0204</addressOffset>
          <description>DMA Channel 8 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH8_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0208</addressOffset>
          <description>DMA Channel 8 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH8_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x020c</addressOffset>
          <description>DMA Channel 8 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH8_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0210</addressOffset>
          <description>Alias for channel 8 CTRL register</description>
          <name>CH8_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0214</addressOffset>
          <description>Alias for channel 8 READ_ADDR register</description>
          <name>CH8_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0218</addressOffset>
          <description>Alias for channel 8 WRITE_ADDR register</description>
          <name>CH8_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x021c</addressOffset>
          <description>Alias for channel 8 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH8_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0220</addressOffset>
          <description>Alias for channel 8 CTRL register</description>
          <name>CH8_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0224</addressOffset>
          <description>Alias for channel 8 TRANS_COUNT register</description>
          <name>CH8_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0228</addressOffset>
          <description>Alias for channel 8 READ_ADDR register</description>
          <name>CH8_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x022c</addressOffset>
          <description>Alias for channel 8 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH8_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0230</addressOffset>
          <description>Alias for channel 8 CTRL register</description>
          <name>CH8_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0234</addressOffset>
          <description>Alias for channel 8 WRITE_ADDR register</description>
          <name>CH8_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0238</addressOffset>
          <description>Alias for channel 8 TRANS_COUNT register</description>
          <name>CH8_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x023c</addressOffset>
          <description>Alias for channel 8 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH8_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0240</addressOffset>
          <description>DMA Channel 9 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH9_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0244</addressOffset>
          <description>DMA Channel 9 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH9_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0248</addressOffset>
          <description>DMA Channel 9 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH9_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x024c</addressOffset>
          <description>DMA Channel 9 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH9_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0250</addressOffset>
          <description>Alias for channel 9 CTRL register</description>
          <name>CH9_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0254</addressOffset>
          <description>Alias for channel 9 READ_ADDR register</description>
          <name>CH9_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0258</addressOffset>
          <description>Alias for channel 9 WRITE_ADDR register</description>
          <name>CH9_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x025c</addressOffset>
          <description>Alias for channel 9 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH9_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0260</addressOffset>
          <description>Alias for channel 9 CTRL register</description>
          <name>CH9_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0264</addressOffset>
          <description>Alias for channel 9 TRANS_COUNT register</description>
          <name>CH9_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0268</addressOffset>
          <description>Alias for channel 9 READ_ADDR register</description>
          <name>CH9_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x026c</addressOffset>
          <description>Alias for channel 9 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH9_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0270</addressOffset>
          <description>Alias for channel 9 CTRL register</description>
          <name>CH9_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0274</addressOffset>
          <description>Alias for channel 9 WRITE_ADDR register</description>
          <name>CH9_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0278</addressOffset>
          <description>Alias for channel 9 TRANS_COUNT register</description>
          <name>CH9_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x027c</addressOffset>
          <description>Alias for channel 9 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH9_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0280</addressOffset>
          <description>DMA Channel 10 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH10_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0284</addressOffset>
          <description>DMA Channel 10 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH10_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0288</addressOffset>
          <description>DMA Channel 10 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH10_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x028c</addressOffset>
          <description>DMA Channel 10 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH10_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0290</addressOffset>
          <description>Alias for channel 10 CTRL register</description>
          <name>CH10_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0294</addressOffset>
          <description>Alias for channel 10 READ_ADDR register</description>
          <name>CH10_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0298</addressOffset>
          <description>Alias for channel 10 WRITE_ADDR register</description>
          <name>CH10_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x029c</addressOffset>
          <description>Alias for channel 10 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH10_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02a0</addressOffset>
          <description>Alias for channel 10 CTRL register</description>
          <name>CH10_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02a4</addressOffset>
          <description>Alias for channel 10 TRANS_COUNT register</description>
          <name>CH10_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02a8</addressOffset>
          <description>Alias for channel 10 READ_ADDR register</description>
          <name>CH10_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02ac</addressOffset>
          <description>Alias for channel 10 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH10_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02b0</addressOffset>
          <description>Alias for channel 10 CTRL register</description>
          <name>CH10_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02b4</addressOffset>
          <description>Alias for channel 10 WRITE_ADDR register</description>
          <name>CH10_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02b8</addressOffset>
          <description>Alias for channel 10 TRANS_COUNT register</description>
          <name>CH10_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02bc</addressOffset>
          <description>Alias for channel 10 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH10_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02c0</addressOffset>
          <description>DMA Channel 11 Read Address pointer\n
            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
          <name>CH11_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02c4</addressOffset>
          <description>DMA Channel 11 Write Address pointer\n
            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
          <name>CH11_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02c8</addressOffset>
          <description>DMA Channel 11 Transfer Count\n
            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
          <name>CH11_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x02cc</addressOffset>
          <description>DMA Channel 11 Control and Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
              <name>AHB_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the channel received a read bus error. Write one to clear.\n
                READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>READ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, the channel received a write bus error. Write one to clear.\n
                WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WRITE_ERROR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
              <name>BUSY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
              <name>SNIFF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Apply byte-swap transformation to DMA data.\n
                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
              <name>IRQ_QUIET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:15]</bitRange>
              <description>Select a Transfer Request signal.\n
                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Select Timer 0 as TREQ</description>
                  <name>TIMER0</name>
                  <value>59</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 1 as TREQ</description>
                  <name>TIMER1</name>
                  <value>60</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 2 as TREQ (Optional)</description>
                  <name>TIMER2</name>
                  <value>61</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Select Timer 3 as TREQ (Optional)</description>
                  <name>TIMER3</name>
                  <value>62</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Permanent request, for unpaced transfers.</description>
                  <name>PERMANENT</name>
                  <value>63</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TREQ_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:11]</bitRange>
              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
              <name>CHAIN_TO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Select whether RING_SIZE applies to read or write addresses.\n
                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
              <name>RING_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:6]</bitRange>
              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RING_NONE</name>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>RING_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
                Generally this should be disabled for memory-to-peripheral transfers.</description>
              <name>INCR_WRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
                Generally this should be disabled for peripheral-to-memory transfers.</description>
              <name>INCR_READ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:2]</bitRange>
              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SIZE_BYTE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_HALFWORD</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SIZE_WORD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DATA_SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
              <name>HIGH_PRIORITY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>DMA Channel Enable.\n
                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CH11_CTRL_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02d0</addressOffset>
          <description>Alias for channel 11 CTRL register</description>
          <name>CH11_AL1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02d4</addressOffset>
          <description>Alias for channel 11 READ_ADDR register</description>
          <name>CH11_AL1_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02d8</addressOffset>
          <description>Alias for channel 11 WRITE_ADDR register</description>
          <name>CH11_AL1_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02dc</addressOffset>
          <description>Alias for channel 11 TRANS_COUNT register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH11_AL1_TRANS_COUNT_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02e0</addressOffset>
          <description>Alias for channel 11 CTRL register</description>
          <name>CH11_AL2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02e4</addressOffset>
          <description>Alias for channel 11 TRANS_COUNT register</description>
          <name>CH11_AL2_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02e8</addressOffset>
          <description>Alias for channel 11 READ_ADDR register</description>
          <name>CH11_AL2_READ_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02ec</addressOffset>
          <description>Alias for channel 11 WRITE_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH11_AL2_WRITE_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02f0</addressOffset>
          <description>Alias for channel 11 CTRL register</description>
          <name>CH11_AL3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02f4</addressOffset>
          <description>Alias for channel 11 WRITE_ADDR register</description>
          <name>CH11_AL3_WRITE_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02f8</addressOffset>
          <description>Alias for channel 11 TRANS_COUNT register</description>
          <name>CH11_AL3_TRANS_COUNT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x02fc</addressOffset>
          <description>Alias for channel 11 READ_ADDR register\n
            This is a trigger register (0xc). Writing a nonzero value will\n
            reload the channel counter and start the channel.</description>
          <name>CH11_AL3_READ_ADDR_TRIG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0400</addressOffset>
          <description>Interrupt Status (raw)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n
                Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n
                This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n
                It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>INTR</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0404</addressOffset>
          <description>Interrupt Enables for IRQ 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Set bit n to pass interrupts from channel n to DMA IRQ 0.</description>
              <name>INTE0</name>
            </field>
          </fields>
          <name>INTE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0408</addressOffset>
          <description>Force Interrupts</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
              <name>INTF0</name>
            </field>
          </fields>
          <name>INTF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x040c</addressOffset>
          <description>Interrupt Status for IRQ 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n
                Channel interrupts can be cleared by writing a bit mask here.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>INTS0</name>
            </field>
          </fields>
          <name>INTS0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0414</addressOffset>
          <description>Interrupt Enables for IRQ 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Set bit n to pass interrupts from channel n to DMA IRQ 1.</description>
              <name>INTE1</name>
            </field>
          </fields>
          <name>INTE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0418</addressOffset>
          <description>Force Interrupts for IRQ 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
              <name>INTF1</name>
            </field>
          </fields>
          <name>INTF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x041c</addressOffset>
          <description>Interrupt Status (masked) for IRQ 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n
                Channel interrupts can be cleared by writing a bit mask here.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>INTS1</name>
            </field>
          </fields>
          <name>INTS1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0420</addressOffset>
          <description>Pacing (X/Y) Fractional Timer\n
            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
              <name>X</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
              <name>Y</name>
            </field>
          </fields>
          <name>TIMER0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0424</addressOffset>
          <description>Pacing (X/Y) Fractional Timer\n
            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
              <name>X</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
              <name>Y</name>
            </field>
          </fields>
          <name>TIMER1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0428</addressOffset>
          <description>Pacing (X/Y) Fractional Timer\n
            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
              <name>X</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
              <name>Y</name>
            </field>
          </fields>
          <name>TIMER2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x042c</addressOffset>
          <description>Pacing (X/Y) Fractional Timer\n
            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
              <name>X</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
              <name>Y</name>
            </field>
          </fields>
          <name>TIMER3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0430</addressOffset>
          <description>Trigger one or more channels simultaneously</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>MULTI_CHAN_TRIGGER</name>
            </field>
          </fields>
          <name>MULTI_CHAN_TRIGGER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0434</addressOffset>
          <description>Sniffer Control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
              <name>OUT_INV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
              <name>OUT_REV</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n
                Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.</description>
              <name>BSWAP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Calculate a CRC-32 (IEEE802.3 polynomial)</description>
                  <name>CRC32</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data</description>
                  <name>CRC32R</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Calculate a CRC-16-CCITT</description>
                  <name>CRC16</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Calculate a CRC-16-CCITT with bit reversed data</description>
                  <name>CRC16R</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>XOR reduction over all data. == 1 if the total 1 population count is odd.</description>
                  <name>EVEN</name>
                  <value>14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)</description>
                  <name>SUM</name>
                  <value>15</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>CALC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:1]</bitRange>
              <description>DMA channel for Sniffer to observe</description>
              <name>DMACH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable sniffer</description>
              <name>EN</name>
            </field>
          </fields>
          <name>SNIFF_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0438</addressOffset>
          <description>Data accumulator for sniff hardware\n
            Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</description>
          <name>SNIFF_DATA</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0440</addressOffset>
          <description>Debug RAF, WAF, TDF levels</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:16]</bitRange>
              <description>Current Read-Address-FIFO fill level</description>
              <name>RAF_LVL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:8]</bitRange>
              <description>Current Write-Address-FIFO fill level</description>
              <name>WAF_LVL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>Current Transfer-Data-FIFO fill level</description>
              <name>TDF_LVL</name>
            </field>
          </fields>
          <name>FIFO_LEVELS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0444</addressOffset>
          <description>Abort an in-progress transfer sequence on one or more channels</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n
                After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>CHAN_ABORT</name>
            </field>
          </fields>
          <name>CHAN_ABORT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0448</addressOffset>
          <description>The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>N_CHANNELS</name>
            </field>
          </fields>
          <name>N_CHANNELS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0800</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH0_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH0_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0804</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH0_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0840</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH1_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH1_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0844</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH1_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0880</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH2_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH2_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0884</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH2_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x08c0</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH3_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH3_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x08c4</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH3_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0900</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH4_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH4_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0904</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH4_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0940</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH5_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH5_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0944</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH5_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0980</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH6_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH6_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0984</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH6_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x09c0</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH7_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH7_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x09c4</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH7_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0a00</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH8_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH8_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0a04</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH8_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0a40</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH9_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH9_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0a44</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH9_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0a80</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH10_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH10_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0a84</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH10_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0ac0</addressOffset>
          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CH11_DBG_CTDREQ</name>
            </field>
          </fields>
          <name>CH11_DBG_CTDREQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0ac4</addressOffset>
          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
          <name>CH11_DBG_TCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0100</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x50100000</baseAddress>
      <description>DPRAM layout for USB device.</description>
      <name>USBCTRL_DPRAM</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Bytes 0-3 of the SETUP packet from the host.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>WVALUE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <name>BREQUEST</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <name>BMREQUESTTYPE</name>
            </field>
          </fields>
          <name>SETUP_PACKET_LOW</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Bytes 4-7 of the setup packet from the host.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <name>WLENGTH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>WINDEX</name>
            </field>
          </fields>
          <name>SETUP_PACKET_HIGH</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP1_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP1_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP2_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP2_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP3_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP3_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP4_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP4_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP5_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP5_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP6_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP6_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP7_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP7_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP8_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP8_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP9_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP9_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP10_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP10_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP11_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP11_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP12_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP12_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP13_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP13_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP14_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP14_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP15_IN_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>This endpoint is double buffered.</description>
              <name>DOUBLE_BUFFERED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Trigger an interrupt each time a buffer is done.</description>
              <name>INTERRUPT_PER_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:26]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Control</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Isochronous</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Bulk</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Interrupt</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>ENDPOINT_TYPE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
              <name>INTERRUPT_ON_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
              <name>BUFFER_ADDRESS</name>
            </field>
          </fields>
          <name>EP15_OUT_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP0_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP0_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP1_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP1_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP2_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP2_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP3_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP3_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP4_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP4_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP5_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP5_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP6_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP6_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP7_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00bc</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP7_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP8_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP8_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP9_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00cc</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP9_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP10_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP10_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP11_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00dc</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP11_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP12_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP12_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP13_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ec</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP13_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP14_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP14_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP15_IN_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00fc</addressOffset>
          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Buffer 1 is the last buffer of the transfer.</description>
              <name>LAST_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>The data pid of buffer 1.</description>
              <name>PID_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:27]</bitRange>
              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
                For a non Isochronous endpoint the offset is always 64 bytes.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>128</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>256</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>512</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1024</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>The length of the data in buffer 1.</description>
              <name>LENGTH_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
              <name>FULL_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Buffer 0 is the last buffer of the transfer.</description>
              <name>LAST_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>The data pid of buffer 0.</description>
              <name>PID_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Reset the buffer selector to buffer 0.</description>
              <name>RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Reply with a stall (valid for both buffers).</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
              <name>AVAILABLE_0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>The length of the data in buffer 0.</description>
              <name>LENGTH_0</name>
            </field>
          </fields>
          <name>EP15_OUT_BUFFER_CONTROL</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x50110000</baseAddress>
      <description>USB FS/LS controller device registers</description>
      <interrupt>
        <name>USBCTRL_IRQ</name>
        <value>5</value>
      </interrupt>
      <name>USBCTRL_REGS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Device address and endpoint control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Device endpoint to send data to. Only valid for HOST mode.</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Interrupt endpoint 1. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Interrupt endpoint 2. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Interrupt endpoint 3. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Interrupt endpoint 4. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP4</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Interrupt endpoint 5. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP5</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Interrupt endpoint 6. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP6</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Interrupt endpoint 7. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP7</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>Interrupt endpoint 8. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP8</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Interrupt endpoint 9. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP9</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Interrupt endpoint 10. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP10</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Interrupt endpoint 11. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP11</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Interrupt endpoint 12. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP12</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Interrupt endpoint 13. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP13</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>Interrupt endpoint 14. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP14</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Interrupt endpoint 15. Only valid for HOST mode.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
              <name>INTEP_PREAMBLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
              <name>INTEP_DIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>Endpoint number of the interrupt endpoint</description>
              <name>ENDPOINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:0]</bitRange>
              <description>Device address</description>
              <name>ADDRESS</name>
            </field>
          </fields>
          <name>ADDR_ENDP15</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Main control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Reduced timings for simulation</description>
              <name>SIM_TIMING</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Device mode = 0, Host mode = 1</description>
              <name>HOST_NDEVICE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable controller</description>
              <name>CONTROLLER_EN</name>
            </field>
          </fields>
          <name>MAIN_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[10:0]</bitRange>
              <name>COUNT</name>
            </field>
          </fields>
          <name>SOF_WR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[10:0]</bitRange>
              <name>COUNT</name>
            </field>
          </fields>
          <name>SOF_RD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>SIE control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL</description>
              <name>EP0_INT_STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>Device: EP0 single buffered = 0, double buffered = 1</description>
              <name>EP0_DOUBLE_BUF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Device: Set bit in BUFF_STATUS for every buffer completed on EP0</description>
              <name>EP0_INT_1BUF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0</description>
              <name>EP0_INT_2BUF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK</description>
              <name>EP0_INT_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>Direct bus drive enable</description>
              <name>DIRECT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Direct control of DP</description>
              <name>DIRECT_DP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>Direct control of DM</description>
              <name>DIRECT_DM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Power down bus transceiver</description>
              <name>TRANSCEIVER_PD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Device: Pull-up strength (0=1K2, 1=2k3)</description>
              <name>RPU_OPT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Device: Enable pull up resistor</description>
              <name>PULLUP_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Host: Enable pull down resistors</description>
              <name>PULLDOWN_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>Host: Reset bus</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>RESET_BUS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>RESUME</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Host: Enable VBUS</description>
              <name>VBUS_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Host: Enable keep alive packet (for low speed bus)</description>
              <name>KEEP_ALIVE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Host: Enable SOF generation (for full speed bus)</description>
              <name>SOF_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Host: Delay packet(s) until after SOF</description>
              <name>SOF_SYNC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Host: Preable enable for LS device on FS hub</description>
              <name>PREAMBLE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Host: Stop transaction</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>STOP_TRANS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Host: Receive transaction (IN to host)</description>
              <name>RECEIVE_DATA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Host: Send transaction (OUT from host)</description>
              <name>SEND_DATA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Host: Send Setup packet</description>
              <name>SEND_SETUP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Host: Start transaction</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>START_TRANS</name>
            </field>
          </fields>
          <name>SIE_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>SIE status register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Data Sequence Error.\n\n
                The device can raise a sequence error in the following conditions:\n\n
                * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n
                The host can raise a data sequence error in the following conditions:\n\n
                * An IN packet from the device has the wrong data PID</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>DATA_SEQ_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>ACK received. Raised by both host and device.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ACK_REC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>Host: STALL received</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>STALL_REC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>Host: NAK received</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>NAK_REC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <description>RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RX_TIMEOUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>RX overflow is raised by the Serial RX engine if the incoming data is too fast.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RX_OVERFLOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>Bit Stuff Error. Raised by the Serial RX engine.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BIT_STUFF_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>CRC Error. Raised by the Serial RX engine.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CRC_ERROR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>Device: bus reset received</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>BUS_RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Transaction complete.\n\n
                Raised by device if:\n\n
                * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n
                Raised by host if:\n\n
                * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>TRANS_COMPLETE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Device: Setup packet received</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>SETUP_REC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Device: connected</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>CONNECTED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Host: Device has initiated a remote resume. Device: host has initiated a resume.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RESUME</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>VBUS over current detected</description>
              <name>VBUS_OVER_CURR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>SPEED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>SUSPENDED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:2]</bitRange>
              <description>USB bus line state</description>
              <name>LINE_STATE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Device: VBUS Detected</description>
              <name>VBUS_DETECTED</name>
            </field>
          </fields>
          <name>SIE_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>interrupt endpoint control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:1]</bitRange>
              <description>Host: Enable interrupt endpoint 1 -&gt; 15</description>
              <name>INT_EP_ACTIVE</name>
            </field>
          </fields>
          <name>INT_EP_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>BUFF_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>EP15_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>EP15_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>EP14_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>EP14_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>EP13_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>EP13_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>EP12_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>EP12_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>EP11_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>EP11_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>EP10_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>EP10_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>EP9_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>EP9_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>EP8_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>EP8_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>EP7_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>EP7_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>EP6_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>EP6_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>EP5_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>EP5_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>EP4_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>EP4_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>EP3_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>EP3_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>EP2_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>EP2_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>EP1_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>EP1_IN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>BUFF_CPU_SHOULD_HANDLE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>EP15_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>EP15_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>EP14_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>EP14_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>EP13_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>EP13_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>EP12_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>EP12_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>EP11_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>EP11_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>EP10_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>EP10_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>EP9_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>EP9_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>EP8_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>EP8_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>EP7_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>EP7_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>EP6_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>EP6_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>EP5_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>EP5_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>EP4_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>EP4_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>EP3_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>EP3_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>EP2_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>EP2_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>EP1_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>EP1_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>EP_ABORT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>EP_ABORT_DONE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>EP_STALL_ARM</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[25:16]</bitRange>
              <description>NAK polling interval for a full speed device</description>
              <name>DELAY_FS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:0]</bitRange>
              <description>NAK polling interval for a low speed device</description>
              <name>DELAY_LS</name>
            </field>
          </fields>
          <name>NAK_POLL</name>
          <resetValue>0x00100010</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP15_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP14_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP13_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP12_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP11_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP10_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP9_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP8_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP7_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP6_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP5_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP4_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP3_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP2_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP1_IN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_OUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>EP0_IN</name>
            </field>
          </fields>
          <name>EP_STATUS_STALL_NAK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>Where to connect the USB controller. Should be to_phy by default.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SOFTCON</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>TO_DIGITAL_PAD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>TO_EXTPHY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>TO_PHY</name>
            </field>
          </fields>
          <name>USB_MUXING</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>OVERCURR_DETECT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>OVERCURR_DETECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>VBUS_DETECT_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>VBUS_DETECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>VBUS_EN_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>VBUS_EN</name>
            </field>
          </fields>
          <name>USB_PWR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <description>DM over voltage</description>
              <name>DM_OVV</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <description>DP over voltage</description>
              <name>DP_OVV</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <description>DM overcurrent</description>
              <name>DM_OVCN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>DP overcurrent</description>
              <name>DP_OVCN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <description>DPM pin state</description>
              <name>RX_DM</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>DPP pin state</description>
              <name>RX_DP</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Differential RX</description>
              <name>RX_DD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>TX_DIFFMODE=0: Single ended mode\n
                TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)</description>
              <name>TX_DIFFMODE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>TX_FSSLEW=0: Low speed slew rate\n
                TX_FSSLEW=1: Full speed slew rate</description>
              <name>TX_FSSLEW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>TX power down override (if override enable is set). 1 = powered down.</description>
              <name>TX_PD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>RX power down override (if override enable is set). 1 = powered down.</description>
              <name>RX_PD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Output data. TX_DIFFMODE=1, Ignored\n
                TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description>
              <name>TX_DM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n
                If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description>
              <name>TX_DP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Output enable. If TX_DIFFMODE=1, Ignored.\n
                If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description>
              <name>TX_DM_OE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n
                If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description>
              <name>TX_DP_OE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>DM pull down enable</description>
              <name>DM_PULLDN_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>DM pull up enable</description>
              <name>DM_PULLUP_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
              <name>DM_PULLUP_HISEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>DP pull down enable</description>
              <name>DP_PULLDN_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>DP pull up enable</description>
              <name>DP_PULLUP_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
              <name>DP_PULLUP_HISEL</name>
            </field>
          </fields>
          <name>USBPHY_DIRECT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Override enable for each control in usbphy_direct</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>TX_DIFFMODE_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>DM_PULLUP_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>TX_FSSLEW_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>TX_PD_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>RX_PD_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>TX_DM_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>TX_DP_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>TX_DM_OE_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>TX_DP_OE_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>DM_PULLDN_EN_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>DP_PULLDN_EN_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>DP_PULLUP_EN_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>DM_PULLUP_HISEL_OVERRIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>DP_PULLUP_HISEL_OVERRIDE_EN</name>
            </field>
          </fields>
          <name>USBPHY_DIRECT_OVERRIDE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Used to adjust trim values of USB phy pull down resistors.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[12:8]</bitRange>
              <description>Value to drive to USB PHY\n
                DM pulldown resistor trim control\n
                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
              <name>DM_PULLDN_TRIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Value to drive to USB PHY\n
                DP pulldown resistor trim control\n
                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
              <name>DP_PULLDN_TRIM</name>
            </field>
          </fields>
          <name>USBPHY_TRIM</name>
          <resetValue>0x00001f1f</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
              <name>EP_STALL_NAK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
              <name>ABORT_DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
              <name>DEV_SOF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
              <name>SETUP_REQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>DEV_RESUME_FROM_HOST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
              <name>DEV_SUSPEND</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
              <name>DEV_CONN_DIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Source: SIE_STATUS.BUS_RESET</description>
              <name>BUS_RESET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
              <name>VBUS_DETECT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Source: SIE_STATUS.STALL_REC</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Source: SIE_STATUS.CRC_ERROR</description>
              <name>ERROR_CRC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
              <name>ERROR_BIT_STUFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
              <name>ERROR_RX_OVERFLOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
              <name>ERROR_RX_TIMEOUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
              <name>ERROR_DATA_SEQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
              <name>BUFF_STATUS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
              <name>TRANS_COMPLETE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
              <name>HOST_SOF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>HOST_RESUME</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
              <name>HOST_CONN_DIS</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
              <name>EP_STALL_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
              <name>ABORT_DONE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
              <name>DEV_SOF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
              <name>SETUP_REQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>DEV_RESUME_FROM_HOST</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
              <name>DEV_SUSPEND</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
              <name>DEV_CONN_DIS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Source: SIE_STATUS.BUS_RESET</description>
              <name>BUS_RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
              <name>VBUS_DETECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Source: SIE_STATUS.STALL_REC</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Source: SIE_STATUS.CRC_ERROR</description>
              <name>ERROR_CRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
              <name>ERROR_BIT_STUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
              <name>ERROR_RX_OVERFLOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
              <name>ERROR_RX_TIMEOUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
              <name>ERROR_DATA_SEQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
              <name>BUFF_STATUS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
              <name>TRANS_COMPLETE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
              <name>HOST_SOF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>HOST_RESUME</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
              <name>HOST_CONN_DIS</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
              <name>EP_STALL_NAK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
              <name>ABORT_DONE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
              <name>DEV_SOF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
              <name>SETUP_REQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>DEV_RESUME_FROM_HOST</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
              <name>DEV_SUSPEND</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
              <name>DEV_CONN_DIS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Source: SIE_STATUS.BUS_RESET</description>
              <name>BUS_RESET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
              <name>VBUS_DETECT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Source: SIE_STATUS.STALL_REC</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <description>Source: SIE_STATUS.CRC_ERROR</description>
              <name>ERROR_CRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
              <name>ERROR_BIT_STUFF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
              <name>ERROR_RX_OVERFLOW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
              <name>ERROR_RX_TIMEOUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
              <name>ERROR_DATA_SEQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
              <name>BUFF_STATUS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
              <name>TRANS_COMPLETE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
              <name>HOST_SOF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>HOST_RESUME</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
              <name>HOST_CONN_DIS</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
              <name>EP_STALL_NAK</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
              <name>ABORT_DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
              <name>DEV_SOF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
              <name>SETUP_REQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>DEV_RESUME_FROM_HOST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
              <name>DEV_SUSPEND</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
              <name>DEV_CONN_DIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Source: SIE_STATUS.BUS_RESET</description>
              <name>BUS_RESET</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
              <name>VBUS_DETECT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <description>Source: SIE_STATUS.STALL_REC</description>
              <name>STALL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Source: SIE_STATUS.CRC_ERROR</description>
              <name>ERROR_CRC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
              <name>ERROR_BIT_STUFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
              <name>ERROR_RX_OVERFLOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
              <name>ERROR_RX_TIMEOUT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
              <name>ERROR_DATA_SEQ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
              <name>BUFF_STATUS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
              <name>TRANS_COMPLETE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
              <name>HOST_SOF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
              <name>HOST_RESUME</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
              <name>HOST_CONN_DIS</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x50200000</baseAddress>
      <description>Programmable IO block</description>
      <interrupt>
        <name>PIO0_IRQ_0</name>
        <value>7</value>
      </interrupt>
      <interrupt>
        <name>PIO0_IRQ_1</name>
        <value>8</value>
      </interrupt>
      <name>PIO0</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>PIO control register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:8]</bitRange>
              <description>Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n
                Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n
                Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>CLKDIV_RESTART</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:4]</bitRange>
              <description>Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
                Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n
                The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>SM_RESTART</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.</description>
              <name>SM_ENABLE</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>FIFO status register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[27:24]</bitRange>
              <description>State machine TX FIFO is empty</description>
              <name>TXEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:16]</bitRange>
              <description>State machine TX FIFO is full</description>
              <name>TXFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:8]</bitRange>
              <description>State machine RX FIFO is empty</description>
              <name>RXEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>State machine RX FIFO is full</description>
              <name>RXFULL</name>
            </field>
          </fields>
          <name>FSTAT</name>
          <resetValue>0x0f000f00</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>FIFO debug register</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[27:24]</bitRange>
              <description>State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>TXSTALL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:16]</bitRange>
              <description>TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>TXOVER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:8]</bitRange>
              <description>RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RXUNDER</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>RXSTALL</name>
            </field>
          </fields>
          <name>FDEBUG</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>FIFO levels</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:28]</bitRange>
              <name>RX3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:24]</bitRange>
              <name>TX3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:20]</bitRange>
              <name>RX2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:16]</bitRange>
              <name>TX2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:12]</bitRange>
              <name>RX1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:8]</bitRange>
              <name>TX1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:4]</bitRange>
              <name>RX0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <name>TX0</name>
            </field>
          </fields>
          <name>FLEVEL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x0010</addressOffset>
          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
          <name>TXF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x0014</addressOffset>
          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
          <name>TXF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x0018</addressOffset>
          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
          <name>TXF2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x001c</addressOffset>
          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
          <name>TXF3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0020</addressOffset>
          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
          <name>RXF0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0024</addressOffset>
          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
          <name>RXF1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0028</addressOffset>
          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
          <name>RXF2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x002c</addressOffset>
          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
          <name>RXF3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n
            Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>IRQ</name>
            </field>
          </fields>
          <name>IRQ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[7:0]</bitRange>
              <name>IRQ_FORCE</name>
            </field>
          </fields>
          <name>IRQ_FORCE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0038</addressOffset>
          <description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
            0 -&gt; input is synchronized (default)\n
            1 -&gt; synchronizer is bypassed\n
            If in doubt, leave this register as all zeroes.</description>
          <name>INPUT_SYNC_BYPASS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x003c</addressOffset>
          <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
          <name>DBG_PADOUT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0040</addressOffset>
          <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
          <name>DBG_PADOE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>The PIO hardware has some free parameters that may vary between chip products.\n
            These should be provided in the chip datasheet, but are also exposed here.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[21:16]</bitRange>
              <description>The size of the instruction memory, measured in units of one instruction</description>
              <name>IMEM_SIZE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:8]</bitRange>
              <description>The number of state machines this PIO instance is equipped with.</description>
              <name>SM_COUNT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:0]</bitRange>
              <description>The depth of the state machine TX/RX FIFOs, measured in words.\n
                Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n
                this depth.</description>
              <name>FIFO_DEPTH</name>
            </field>
          </fields>
          <name>DBG_CFGINFO</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Write-only access to instruction memory location 0</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM0</name>
            </field>
          </fields>
          <name>INSTR_MEM0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>Write-only access to instruction memory location 1</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM1</name>
            </field>
          </fields>
          <name>INSTR_MEM1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Write-only access to instruction memory location 2</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM2</name>
            </field>
          </fields>
          <name>INSTR_MEM2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Write-only access to instruction memory location 3</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM3</name>
            </field>
          </fields>
          <name>INSTR_MEM3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Write-only access to instruction memory location 4</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM4</name>
            </field>
          </fields>
          <name>INSTR_MEM4</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Write-only access to instruction memory location 5</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM5</name>
            </field>
          </fields>
          <name>INSTR_MEM5</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Write-only access to instruction memory location 6</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM6</name>
            </field>
          </fields>
          <name>INSTR_MEM6</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Write-only access to instruction memory location 7</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM7</name>
            </field>
          </fields>
          <name>INSTR_MEM7</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0068</addressOffset>
          <description>Write-only access to instruction memory location 8</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM8</name>
            </field>
          </fields>
          <name>INSTR_MEM8</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Write-only access to instruction memory location 9</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM9</name>
            </field>
          </fields>
          <name>INSTR_MEM9</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Write-only access to instruction memory location 10</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM10</name>
            </field>
          </fields>
          <name>INSTR_MEM10</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0074</addressOffset>
          <description>Write-only access to instruction memory location 11</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM11</name>
            </field>
          </fields>
          <name>INSTR_MEM11</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>Write-only access to instruction memory location 12</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM12</name>
            </field>
          </fields>
          <name>INSTR_MEM12</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <description>Write-only access to instruction memory location 13</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM13</name>
            </field>
          </fields>
          <name>INSTR_MEM13</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Write-only access to instruction memory location 14</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM14</name>
            </field>
          </fields>
          <name>INSTR_MEM14</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Write-only access to instruction memory location 15</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM15</name>
            </field>
          </fields>
          <name>INSTR_MEM15</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>Write-only access to instruction memory location 16</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM16</name>
            </field>
          </fields>
          <name>INSTR_MEM16</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Write-only access to instruction memory location 17</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM17</name>
            </field>
          </fields>
          <name>INSTR_MEM17</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>Write-only access to instruction memory location 18</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM18</name>
            </field>
          </fields>
          <name>INSTR_MEM18</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Write-only access to instruction memory location 19</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM19</name>
            </field>
          </fields>
          <name>INSTR_MEM19</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Write-only access to instruction memory location 20</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM20</name>
            </field>
          </fields>
          <name>INSTR_MEM20</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>Write-only access to instruction memory location 21</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM21</name>
            </field>
          </fields>
          <name>INSTR_MEM21</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>Write-only access to instruction memory location 22</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM22</name>
            </field>
          </fields>
          <name>INSTR_MEM22</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>Write-only access to instruction memory location 23</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM23</name>
            </field>
          </fields>
          <name>INSTR_MEM23</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>Write-only access to instruction memory location 24</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM24</name>
            </field>
          </fields>
          <name>INSTR_MEM24</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>Write-only access to instruction memory location 25</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM25</name>
            </field>
          </fields>
          <name>INSTR_MEM25</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>Write-only access to instruction memory location 26</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM26</name>
            </field>
          </fields>
          <name>INSTR_MEM26</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>Write-only access to instruction memory location 27</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM27</name>
            </field>
          </fields>
          <name>INSTR_MEM27</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>Write-only access to instruction memory location 28</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM28</name>
            </field>
          </fields>
          <name>INSTR_MEM28</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00bc</addressOffset>
          <description>Write-only access to instruction memory location 29</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM29</name>
            </field>
          </fields>
          <name>INSTR_MEM29</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c0</addressOffset>
          <description>Write-only access to instruction memory location 30</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM30</name>
            </field>
          </fields>
          <name>INSTR_MEM30</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c4</addressOffset>
          <description>Write-only access to instruction memory location 31</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[15:0]</bitRange>
              <name>INSTR_MEM31</name>
            </field>
          </fields>
          <name>INSTR_MEM31</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c8</addressOffset>
          <description>Clock divisor register for state machine 0\n
            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Effective frequency is sysclk/(int + frac/256).\n
                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Fractional part of clock divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>SM0_CLKDIV</name>
          <resetValue>0x00010000</resetValue>
        </register>
        <register>
          <addressOffset>0x00cc</addressOffset>
          <description>Execution/behavioural settings for state machine 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
              <name>EXEC_STALLED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
              <name>SIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
              <name>SIDE_PINDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:24]</bitRange>
              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
              <name>JMP_PIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:19]</bitRange>
              <description>Which data bit to use for inline OUT enable</description>
              <name>OUT_EN_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
                deassert the latest pin write. This can create useful masking/override behaviour\n
                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
              <name>INLINE_OUT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Continuously assert the most recent OUT/SET to the pins</description>
              <name>OUT_STICKY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:12]</bitRange>
              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
              <name>WRAP_TOP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:7]</bitRange>
              <description>After reaching wrap_top, execution is wrapped to this address.</description>
              <name>WRAP_BOTTOM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Comparison used for the MOV x, STATUS instruction.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>TXLEVEL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>RXLEVEL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STATUS_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Comparison level for the MOV x, STATUS instruction</description>
              <name>STATUS_N</name>
            </field>
          </fields>
          <name>SM0_EXECCTRL</name>
          <resetValue>0x0001f000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d0</addressOffset>
          <description>Control behaviour of the input/output shift registers for state machine 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
                TX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_RX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
                RX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_TX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:25]</bitRange>
              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
                Write 0 for value of 32.</description>
              <name>PULL_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:20]</bitRange>
              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
                Write 0 for value of 32.</description>
              <name>PUSH_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>1 = shift out of output shift register to right. 0 = to left.</description>
              <name>OUT_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
              <name>IN_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
              <name>AUTOPULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
              <name>AUTOPUSH</name>
            </field>
          </fields>
          <name>SM0_SHIFTCTRL</name>
          <resetValue>0x000c0000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d4</addressOffset>
          <description>Current instruction address of state machine 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>SM0_ADDR</name>
            </field>
          </fields>
          <name>SM0_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00d8</addressOffset>
          <description>Read to see the instruction currently addressed by state machine 0's program counter\n
            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>SM0_INSTR</name>
            </field>
          </fields>
          <name>SM0_INSTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00dc</addressOffset>
          <description>State machine pin control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:29]</bitRange>
              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
              <name>SIDESET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:26]</bitRange>
              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
              <name>SET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:20]</bitRange>
              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
              <name>OUT_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:15]</bitRange>
              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
              <name>IN_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
              <name>SIDESET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
              <name>SET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
              <name>OUT_BASE</name>
            </field>
          </fields>
          <name>SM0_PINCTRL</name>
          <resetValue>0x14000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e0</addressOffset>
          <description>Clock divisor register for state machine 1\n
            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Effective frequency is sysclk/(int + frac/256).\n
                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Fractional part of clock divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>SM1_CLKDIV</name>
          <resetValue>0x00010000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e4</addressOffset>
          <description>Execution/behavioural settings for state machine 1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
              <name>EXEC_STALLED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
              <name>SIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
              <name>SIDE_PINDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:24]</bitRange>
              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
              <name>JMP_PIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:19]</bitRange>
              <description>Which data bit to use for inline OUT enable</description>
              <name>OUT_EN_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
                deassert the latest pin write. This can create useful masking/override behaviour\n
                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
              <name>INLINE_OUT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Continuously assert the most recent OUT/SET to the pins</description>
              <name>OUT_STICKY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:12]</bitRange>
              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
              <name>WRAP_TOP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:7]</bitRange>
              <description>After reaching wrap_top, execution is wrapped to this address.</description>
              <name>WRAP_BOTTOM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Comparison used for the MOV x, STATUS instruction.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>TXLEVEL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>RXLEVEL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STATUS_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Comparison level for the MOV x, STATUS instruction</description>
              <name>STATUS_N</name>
            </field>
          </fields>
          <name>SM1_EXECCTRL</name>
          <resetValue>0x0001f000</resetValue>
        </register>
        <register>
          <addressOffset>0x00e8</addressOffset>
          <description>Control behaviour of the input/output shift registers for state machine 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
                TX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_RX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
                RX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_TX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:25]</bitRange>
              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
                Write 0 for value of 32.</description>
              <name>PULL_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:20]</bitRange>
              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
                Write 0 for value of 32.</description>
              <name>PUSH_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>1 = shift out of output shift register to right. 0 = to left.</description>
              <name>OUT_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
              <name>IN_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
              <name>AUTOPULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
              <name>AUTOPUSH</name>
            </field>
          </fields>
          <name>SM1_SHIFTCTRL</name>
          <resetValue>0x000c0000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ec</addressOffset>
          <description>Current instruction address of state machine 1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>SM1_ADDR</name>
            </field>
          </fields>
          <name>SM1_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>Read to see the instruction currently addressed by state machine 1's program counter\n
            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>SM1_INSTR</name>
            </field>
          </fields>
          <name>SM1_INSTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>State machine pin control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:29]</bitRange>
              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
              <name>SIDESET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:26]</bitRange>
              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
              <name>SET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:20]</bitRange>
              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
              <name>OUT_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:15]</bitRange>
              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
              <name>IN_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
              <name>SIDESET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
              <name>SET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
              <name>OUT_BASE</name>
            </field>
          </fields>
          <name>SM1_PINCTRL</name>
          <resetValue>0x14000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>Clock divisor register for state machine 2\n
            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Effective frequency is sysclk/(int + frac/256).\n
                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Fractional part of clock divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>SM2_CLKDIV</name>
          <resetValue>0x00010000</resetValue>
        </register>
        <register>
          <addressOffset>0x00fc</addressOffset>
          <description>Execution/behavioural settings for state machine 2</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
              <name>EXEC_STALLED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
              <name>SIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
              <name>SIDE_PINDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:24]</bitRange>
              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
              <name>JMP_PIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:19]</bitRange>
              <description>Which data bit to use for inline OUT enable</description>
              <name>OUT_EN_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
                deassert the latest pin write. This can create useful masking/override behaviour\n
                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
              <name>INLINE_OUT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Continuously assert the most recent OUT/SET to the pins</description>
              <name>OUT_STICKY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:12]</bitRange>
              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
              <name>WRAP_TOP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:7]</bitRange>
              <description>After reaching wrap_top, execution is wrapped to this address.</description>
              <name>WRAP_BOTTOM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Comparison used for the MOV x, STATUS instruction.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>TXLEVEL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>RXLEVEL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STATUS_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Comparison level for the MOV x, STATUS instruction</description>
              <name>STATUS_N</name>
            </field>
          </fields>
          <name>SM2_EXECCTRL</name>
          <resetValue>0x0001f000</resetValue>
        </register>
        <register>
          <addressOffset>0x0100</addressOffset>
          <description>Control behaviour of the input/output shift registers for state machine 2</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
                TX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_RX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
                RX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_TX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:25]</bitRange>
              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
                Write 0 for value of 32.</description>
              <name>PULL_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:20]</bitRange>
              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
                Write 0 for value of 32.</description>
              <name>PUSH_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>1 = shift out of output shift register to right. 0 = to left.</description>
              <name>OUT_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
              <name>IN_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
              <name>AUTOPULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
              <name>AUTOPUSH</name>
            </field>
          </fields>
          <name>SM2_SHIFTCTRL</name>
          <resetValue>0x000c0000</resetValue>
        </register>
        <register>
          <addressOffset>0x0104</addressOffset>
          <description>Current instruction address of state machine 2</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>SM2_ADDR</name>
            </field>
          </fields>
          <name>SM2_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0108</addressOffset>
          <description>Read to see the instruction currently addressed by state machine 2's program counter\n
            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>SM2_INSTR</name>
            </field>
          </fields>
          <name>SM2_INSTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x010c</addressOffset>
          <description>State machine pin control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:29]</bitRange>
              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
              <name>SIDESET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:26]</bitRange>
              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
              <name>SET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:20]</bitRange>
              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
              <name>OUT_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:15]</bitRange>
              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
              <name>IN_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
              <name>SIDESET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
              <name>SET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
              <name>OUT_BASE</name>
            </field>
          </fields>
          <name>SM2_PINCTRL</name>
          <resetValue>0x14000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0110</addressOffset>
          <description>Clock divisor register for state machine 3\n
            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Effective frequency is sysclk/(int + frac/256).\n
                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Fractional part of clock divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>SM3_CLKDIV</name>
          <resetValue>0x00010000</resetValue>
        </register>
        <register>
          <addressOffset>0x0114</addressOffset>
          <description>Execution/behavioural settings for state machine 3</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
              <name>EXEC_STALLED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
              <name>SIDE_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
              <name>SIDE_PINDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:24]</bitRange>
              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
              <name>JMP_PIN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:19]</bitRange>
              <description>Which data bit to use for inline OUT enable</description>
              <name>OUT_EN_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
                deassert the latest pin write. This can create useful masking/override behaviour\n
                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
              <name>INLINE_OUT_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Continuously assert the most recent OUT/SET to the pins</description>
              <name>OUT_STICKY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:12]</bitRange>
              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
              <name>WRAP_TOP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:7]</bitRange>
              <description>After reaching wrap_top, execution is wrapped to this address.</description>
              <name>WRAP_BOTTOM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Comparison used for the MOV x, STATUS instruction.</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>TXLEVEL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
                  <name>RXLEVEL</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>STATUS_SEL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Comparison level for the MOV x, STATUS instruction</description>
              <name>STATUS_N</name>
            </field>
          </fields>
          <name>SM3_EXECCTRL</name>
          <resetValue>0x0001f000</resetValue>
        </register>
        <register>
          <addressOffset>0x0118</addressOffset>
          <description>Control behaviour of the input/output shift registers for state machine 3</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
                TX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_RX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
                RX FIFO is disabled as a result (always reads as both full and empty).\n
                FIFOs are flushed when this bit is changed.</description>
              <name>FJOIN_TX</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:25]</bitRange>
              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
                Write 0 for value of 32.</description>
              <name>PULL_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:20]</bitRange>
              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
                Write 0 for value of 32.</description>
              <name>PUSH_THRESH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <description>1 = shift out of output shift register to right. 0 = to left.</description>
              <name>OUT_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
              <name>IN_SHIFTDIR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
              <name>AUTOPULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
              <name>AUTOPUSH</name>
            </field>
          </fields>
          <name>SM3_SHIFTCTRL</name>
          <resetValue>0x000c0000</resetValue>
        </register>
        <register>
          <addressOffset>0x011c</addressOffset>
          <description>Current instruction address of state machine 3</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>SM3_ADDR</name>
            </field>
          </fields>
          <name>SM3_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0120</addressOffset>
          <description>Read to see the instruction currently addressed by state machine 3's program counter\n
            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <name>SM3_INSTR</name>
            </field>
          </fields>
          <name>SM3_INSTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0124</addressOffset>
          <description>State machine pin control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:29]</bitRange>
              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
              <name>SIDESET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:26]</bitRange>
              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
              <name>SET_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:20]</bitRange>
              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
              <name>OUT_COUNT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:15]</bitRange>
              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
              <name>IN_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
              <name>SIDESET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
              <name>SET_BASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
              <name>OUT_BASE</name>
            </field>
          </fields>
          <name>SM3_PINCTRL</name>
          <resetValue>0x14000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0128</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x012c</addressOffset>
          <description>Interrupt Enable for irq0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ0_INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0130</addressOffset>
          <description>Interrupt Force for irq0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ0_INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0134</addressOffset>
          <description>Interrupt status after masking &amp; forcing for irq0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ0_INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0138</addressOffset>
          <description>Interrupt Enable for irq1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ1_INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x013c</addressOffset>
          <description>Interrupt Force for irq1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ1_INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0140</addressOffset>
          <description>Interrupt status after masking &amp; forcing for irq1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>SM3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>SM2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>SM1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>SM0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>SM3_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>SM2_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>SM1_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>SM0_TXNFULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>SM3_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>SM2_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>SM1_RXNEMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>SM0_RXNEMPTY</name>
            </field>
          </fields>
          <name>IRQ1_INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral derivedFrom="PIO0">
      <baseAddress>0x50300000</baseAddress>
      <interrupt>
        <name>PIO1_IRQ_0</name>
        <value>9</value>
      </interrupt>
      <interrupt>
        <name>PIO1_IRQ_1</name>
        <value>10</value>
      </interrupt>
      <name>PIO1</name>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0200</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0xd0000000</baseAddress>
      <description>Single-cycle IO block\n
        Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description>
      <interrupt>
        <name>SIO_IRQ_PROC0</name>
        <value>15</value>
      </interrupt>
      <interrupt>
        <name>SIO_IRQ_PROC1</name>
        <value>16</value>
      </interrupt>
      <name>SIO</name>
      <registers>
        <register>
          <access>read-only</access>
          <addressOffset>0x0000</addressOffset>
          <description>Processor core identifier\n
            Value is 0 when read from processor core 0, and 1 when read from processor core 1.</description>
          <name>CPUID</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Input value for GPIO pins</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Input value for GPIO0...29</description>
              <name>GPIO_IN</name>
            </field>
          </fields>
          <name>GPIO_IN</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Input value for QSPI pins</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3</description>
              <name>GPIO_HI_IN</name>
            </field>
          </fields>
          <name>GPIO_HI_IN</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>GPIO output value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:0]</bitRange>
              <description>Set output level (1/0 -&gt; high/low) for GPIO0...29.\n
                Reading back gives the last value written, NOT the input value from the pins.\n
                If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n
                the result is as though the write from core 0 took place first,\n
                and the write from core 1 was then applied to that intermediate result.</description>
              <name>GPIO_OUT</name>
            </field>
          </fields>
          <name>GPIO_OUT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>GPIO output value set</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
              <name>GPIO_OUT_SET</name>
            </field>
          </fields>
          <name>GPIO_OUT_SET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>GPIO output value clear</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
              <name>GPIO_OUT_CLR</name>
            </field>
          </fields>
          <name>GPIO_OUT_CLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>GPIO output value XOR</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
              <name>GPIO_OUT_XOR</name>
            </field>
          </fields>
          <name>GPIO_OUT_XOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>GPIO output enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:0]</bitRange>
              <description>Set output enable (1/0 -&gt; output/input) for GPIO0...29.\n
                Reading back gives the last value written.\n
                If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n
                the result is as though the write from core 0 took place first,\n
                and the write from core 1 was then applied to that intermediate result.</description>
              <name>GPIO_OE</name>
            </field>
          </fields>
          <name>GPIO_OE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>GPIO output enable set</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
              <name>GPIO_OE_SET</name>
            </field>
          </fields>
          <name>GPIO_OE_SET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>GPIO output enable clear</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
              <name>GPIO_OE_CLR</name>
            </field>
          </fields>
          <name>GPIO_OE_CLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>GPIO output enable XOR</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[29:0]</bitRange>
              <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
              <name>GPIO_OE_XOR</name>
            </field>
          </fields>
          <name>GPIO_OE_XOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>QSPI output value</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>Set output level (1/0 -&gt; high/low) for QSPI IO0...5.\n
                Reading back gives the last value written, NOT the input value from the pins.\n
                If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n
                the result is as though the write from core 0 took place first,\n
                and the write from core 1 was then applied to that intermediate result.</description>
              <name>GPIO_HI_OUT</name>
            </field>
          </fields>
          <name>GPIO_HI_OUT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>QSPI output value set</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
              <name>GPIO_HI_OUT_SET</name>
            </field>
          </fields>
          <name>GPIO_HI_OUT_SET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>QSPI output value clear</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
              <name>GPIO_HI_OUT_CLR</name>
            </field>
          </fields>
          <name>GPIO_HI_OUT_CLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>QSPI output value XOR</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
              <name>GPIO_HI_OUT_XOR</name>
            </field>
          </fields>
          <name>GPIO_HI_OUT_XOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>QSPI output enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <description>Set output enable (1/0 -&gt; output/input) for QSPI IO0...5.\n
                Reading back gives the last value written.\n
                If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n
                the result is as though the write from core 0 took place first,\n
                and the write from core 1 was then applied to that intermediate result.</description>
              <name>GPIO_HI_OE</name>
            </field>
          </fields>
          <name>GPIO_HI_OE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>QSPI output enable set</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
              <name>GPIO_HI_OE_SET</name>
            </field>
          </fields>
          <name>GPIO_HI_OE_SET</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>QSPI output enable clear</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
              <name>GPIO_HI_OE_CLR</name>
            </field>
          </fields>
          <name>GPIO_HI_OE_CLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>QSPI output enable XOR</description>
          <fields>
            <field>
              <access>write-only</access>
              <bitRange>[5:0]</bitRange>
              <description>Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
              <name>GPIO_HI_OE_XOR</name>
            </field>
          </fields>
          <name>GPIO_HI_OE_XOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>Status register for inter-core FIFOs (mailboxes).\n
            There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep.\n
            Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX).\n
            Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX).\n
            The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>ROE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</description>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
              <name>WOF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</description>
              <name>RDY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)</description>
              <name>VLD</name>
            </field>
          </fields>
          <name>FIFO_ST</name>
          <resetValue>0x00000002</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x0054</addressOffset>
          <description>Write access to this core's TX FIFO</description>
          <name>FIFO_WR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0058</addressOffset>
          <description>Read access to this core's RX FIFO</description>
          <name>FIFO_RD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x005c</addressOffset>
          <description>Spinlock state\n
            A bitmap containing the state of all 32 spinlocks (1=locked).\n
            Mainly intended for debugging.</description>
          <name>SPINLOCK_ST</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0060</addressOffset>
          <description>Divider unsigned dividend\n
            Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n
            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
            UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n
            unsigned calculation, and the S alias starts a signed calculation.</description>
          <name>DIV_UDIVIDEND</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0064</addressOffset>
          <description>Divider unsigned divisor\n
            Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n
            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
            UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n
            unsigned calculation, and the S alias starts a signed calculation.</description>
          <name>DIV_UDIVISOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0068</addressOffset>
          <description>Divider signed dividend\n
            The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</description>
          <name>DIV_SDIVIDEND</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x006c</addressOffset>
          <description>Divider signed divisor\n
            The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</description>
          <name>DIV_SDIVISOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0070</addressOffset>
          <description>Divider result quotient\n
            The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n
            For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n
            This register can be written to directly, for context save/restore purposes. This halts any\n
            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n
            Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n
            REMAINDER, QUOTIENT if CSR_DIRTY is used.</description>
          <name>DIV_QUOTIENT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0074</addressOffset>
          <description>Divider result remainder\n
            The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n
            For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n
            This register can be written to directly, for context save/restore purposes. This halts any\n
            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</description>
          <name>DIV_REMAINDER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <description>Control and status register for divider.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n
                Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n
                If the flag is used in this way, it's recommended to either read QUOTIENT only,\n
                or REMAINDER and then QUOTIENT, to prevent data loss on context switch.</description>
              <name>DIRTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Reads as 0 when a calculation is in progress, 1 otherwise.\n
                Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n
                matter if one is already in progress.\n
                Writing to a result register will immediately terminate any in-progress calculation\n
                and set the READY and DIRTY flags.</description>
              <name>READY</name>
            </field>
          </fields>
          <name>DIV_CSR</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0080</addressOffset>
          <description>Read/write access to accumulator 0</description>
          <name>INTERP0_ACCUM0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0084</addressOffset>
          <description>Read/write access to accumulator 1</description>
          <name>INTERP0_ACCUM1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0088</addressOffset>
          <description>Read/write access to BASE0 register.</description>
          <name>INTERP0_BASE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x008c</addressOffset>
          <description>Read/write access to BASE1 register.</description>
          <name>INTERP0_BASE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0090</addressOffset>
          <description>Read/write access to BASE2 register.</description>
          <name>INTERP0_BASE2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0094</addressOffset>
          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP0_POP_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0098</addressOffset>
          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP0_POP_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x009c</addressOffset>
          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP0_POP_FULL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00a0</addressOffset>
          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
          <name>INTERP0_PEEK_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00a4</addressOffset>
          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
          <name>INTERP0_PEEK_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00a8</addressOffset>
          <description>Read FULL result, without altering any internal state (PEEK).</description>
          <name>INTERP0_PEEK_FULL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>Control register for lane 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <description>Set if either OVERF0 or OVERF1 is set.</description>
              <name>OVERF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
              <name>OVERF1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
              <name>OVERF0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <description>Only present on INTERP0 on each core. If BLEND mode is enabled:\n
                - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n
                by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n
                0 and 255/256ths)\n
                - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n
                - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n
                LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.</description>
              <name>BLEND</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:19]</bitRange>
              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
                of pointers into flash or SRAM.</description>
              <name>FORCE_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
              <name>ADD_RAW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
              <name>CROSS_RESULT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
              <name>CROSS_INPUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
              <name>SIGNED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
              <name>MASK_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
              <name>MASK_LSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Logical right-shift applied to accumulator before masking</description>
              <name>SHIFT</name>
            </field>
          </fields>
          <name>INTERP0_CTRL_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>Control register for lane 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:19]</bitRange>
              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
                of pointers into flash or SRAM.</description>
              <name>FORCE_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
              <name>ADD_RAW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
              <name>CROSS_RESULT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
              <name>CROSS_INPUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
              <name>SIGNED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
              <name>MASK_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
              <name>MASK_LSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Logical right-shift applied to accumulator before masking</description>
              <name>SHIFT</name>
            </field>
          </fields>
          <name>INTERP0_CTRL_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>Values written here are atomically added to ACCUM0\n
            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <name>INTERP0_ACCUM0_ADD</name>
            </field>
          </fields>
          <name>INTERP0_ACCUM0_ADD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>Values written here are atomically added to ACCUM1\n
            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <name>INTERP0_ACCUM1_ADD</name>
            </field>
          </fields>
          <name>INTERP0_ACCUM1_ADD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x00bc</addressOffset>
          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
          <name>INTERP0_BASE_1AND0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c0</addressOffset>
          <description>Read/write access to accumulator 0</description>
          <name>INTERP1_ACCUM0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c4</addressOffset>
          <description>Read/write access to accumulator 1</description>
          <name>INTERP1_ACCUM1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00c8</addressOffset>
          <description>Read/write access to BASE0 register.</description>
          <name>INTERP1_BASE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00cc</addressOffset>
          <description>Read/write access to BASE1 register.</description>
          <name>INTERP1_BASE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x00d0</addressOffset>
          <description>Read/write access to BASE2 register.</description>
          <name>INTERP1_BASE2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00d4</addressOffset>
          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP1_POP_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00d8</addressOffset>
          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP1_POP_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00dc</addressOffset>
          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
          <name>INTERP1_POP_FULL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00e0</addressOffset>
          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
          <name>INTERP1_PEEK_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00e4</addressOffset>
          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
          <name>INTERP1_PEEK_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x00e8</addressOffset>
          <description>Read FULL result, without altering any internal state (PEEK).</description>
          <name>INTERP1_PEEK_FULL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00ec</addressOffset>
          <description>Control register for lane 0</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <description>Set if either OVERF0 or OVERF1 is set.</description>
              <name>OVERF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
              <name>OVERF1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
              <name>OVERF0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <description>Only present on INTERP1 on each core. If CLAMP mode is enabled:\n
                - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n
                BASE0 and an upper bound of BASE1.\n
                - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED</description>
              <name>CLAMP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:19]</bitRange>
              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
                of pointers into flash or SRAM.</description>
              <name>FORCE_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
              <name>ADD_RAW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
              <name>CROSS_RESULT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
              <name>CROSS_INPUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
              <name>SIGNED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
              <name>MASK_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
              <name>MASK_LSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Logical right-shift applied to accumulator before masking</description>
              <name>SHIFT</name>
            </field>
          </fields>
          <name>INTERP1_CTRL_LANE0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>Control register for lane 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:19]</bitRange>
              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
                of pointers into flash or SRAM.</description>
              <name>FORCE_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
              <name>ADD_RAW</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
              <name>CROSS_RESULT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
              <name>CROSS_INPUT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
              <name>SIGNED</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:10]</bitRange>
              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
              <name>MASK_MSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:5]</bitRange>
              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
              <name>MASK_LSB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:0]</bitRange>
              <description>Logical right-shift applied to accumulator before masking</description>
              <name>SHIFT</name>
            </field>
          </fields>
          <name>INTERP1_CTRL_LANE1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>Values written here are atomically added to ACCUM0\n
            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <name>INTERP1_ACCUM0_ADD</name>
            </field>
          </fields>
          <name>INTERP1_ACCUM0_ADD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>Values written here are atomically added to ACCUM1\n
            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <name>INTERP1_ACCUM1_ADD</name>
            </field>
          </fields>
          <name>INTERP1_ACCUM1_ADD</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>write-only</access>
          <addressOffset>0x00fc</addressOffset>
          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
          <name>INTERP1_BASE_1AND0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0100</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0104</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0108</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x010c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0110</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK4</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0114</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK5</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0118</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK6</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x011c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK7</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0120</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK8</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0124</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK9</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0128</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK10</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x012c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK11</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0130</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK12</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0134</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK13</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0138</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK14</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x013c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK15</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0140</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK16</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0144</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK17</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0148</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK18</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x014c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK19</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0150</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK20</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0154</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK21</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0158</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK22</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x015c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK23</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0160</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK24</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0164</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK25</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0168</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK26</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x016c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK27</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0170</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK28</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0174</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK29</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0178</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK30</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x017c</addressOffset>
          <description>Reading from a spinlock address will:\n
            - Return 0 if lock is already locked\n
            - Otherwise return nonzero, and simultaneously claim the lock\n\n
            Writing (any value) releases the lock.\n
            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
            The value returned on success is 0x1 &lt;&lt; lock number.</description>
          <name>SPINLOCK31</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x10000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0xe0000000</baseAddress>
      <name>PPB</name>
      <registers>
        <register>
          <addressOffset>0xe010</addressOffset>
          <description>Use the SysTick Control and Status Register to enable the SysTick features.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.</description>
              <name>COUNTFLAG</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n
                Selects the SysTick timer clock source:\n
                0 = External reference clock.\n
                1 = Processor clock.</description>
              <name>CLKSOURCE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Enables SysTick exception request:\n
                0 = Counting down to zero does not assert the SysTick exception request.\n
                1 = Counting down to zero to asserts the SysTick exception request.</description>
              <name>TICKINT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enable SysTick counter:\n
                0 = Counter disabled.\n
                1 = Counter enabled.</description>
              <name>ENABLE</name>
            </field>
          </fields>
          <name>SYST_CSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe014</addressOffset>
          <description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n
            To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
              <name>RELOAD</name>
            </field>
          </fields>
          <name>SYST_RVR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe018</addressOffset>
          <description>Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[23:0]</bitRange>
              <description>Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
              <name>CURRENT</name>
            </field>
          </fields>
          <name>SYST_CVR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe01c</addressOffset>
          <description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <description>If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.</description>
              <name>NOREF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <description>If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).</description>
              <name>SKEW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:0]</bitRange>
              <description>An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.</description>
              <name>TENMS</name>
            </field>
          </fields>
          <name>SYST_CALIB</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe100</addressOffset>
          <description>Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n
            If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>Interrupt set-enable bits.\n
                Write:\n
                0 = No effect.\n
                1 = Enable interrupt.\n
                Read:\n
                0 = Interrupt disabled.\n
                1 = Interrupt enabled.</description>
              <name>SETENA</name>
            </field>
          </fields>
          <name>NVIC_ISER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe180</addressOffset>
          <description>Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>Interrupt clear-enable bits.\n
                Write:\n
                0 = No effect.\n
                1 = Disable interrupt.\n
                Read:\n
                0 = Interrupt disabled.\n
                1 = Interrupt enabled.</description>
              <name>CLRENA</name>
            </field>
          </fields>
          <name>NVIC_ICER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe200</addressOffset>
          <description>The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>Interrupt set-pending bits.\n
                Write:\n
                0 = No effect.\n
                1 = Changes interrupt state to pending.\n
                Read:\n
                0 = Interrupt is not pending.\n
                1 = Interrupt is pending.\n
                Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n
                An interrupt that is pending has no effect.\n
                A disabled interrupt sets the state of that interrupt to pending.</description>
              <name>SETPEND</name>
            </field>
          </fields>
          <name>NVIC_ISPR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe280</addressOffset>
          <description>Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>Interrupt clear-pending bits.\n
                Write:\n
                0 = No effect.\n
                1 = Removes pending state and interrupt.\n
                Read:\n
                0 = Interrupt is not pending.\n
                1 = Interrupt is pending.</description>
              <name>CLRPEND</name>
            </field>
          </fields>
          <name>NVIC_ICPR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe400</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n
            Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n
            These registers are only word-accessible</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 3</description>
              <name>IP_3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 2</description>
              <name>IP_2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 1</description>
              <name>IP_1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 0</description>
              <name>IP_0</name>
            </field>
          </fields>
          <name>NVIC_IPR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe404</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 7</description>
              <name>IP_7</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 6</description>
              <name>IP_6</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 5</description>
              <name>IP_5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 4</description>
              <name>IP_4</name>
            </field>
          </fields>
          <name>NVIC_IPR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe408</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 11</description>
              <name>IP_11</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 10</description>
              <name>IP_10</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 9</description>
              <name>IP_9</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 8</description>
              <name>IP_8</name>
            </field>
          </fields>
          <name>NVIC_IPR2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe40c</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 15</description>
              <name>IP_15</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 14</description>
              <name>IP_14</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 13</description>
              <name>IP_13</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 12</description>
              <name>IP_12</name>
            </field>
          </fields>
          <name>NVIC_IPR3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe410</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 19</description>
              <name>IP_19</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 18</description>
              <name>IP_18</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 17</description>
              <name>IP_17</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 16</description>
              <name>IP_16</name>
            </field>
          </fields>
          <name>NVIC_IPR4</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe414</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 23</description>
              <name>IP_23</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 22</description>
              <name>IP_22</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 21</description>
              <name>IP_21</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 20</description>
              <name>IP_20</name>
            </field>
          </fields>
          <name>NVIC_IPR5</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe418</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 27</description>
              <name>IP_27</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 26</description>
              <name>IP_26</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 25</description>
              <name>IP_25</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 24</description>
              <name>IP_24</name>
            </field>
          </fields>
          <name>NVIC_IPR6</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xe41c</addressOffset>
          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of interrupt 31</description>
              <name>IP_31</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of interrupt 30</description>
              <name>IP_30</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:14]</bitRange>
              <description>Priority of interrupt 29</description>
              <name>IP_29</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:6]</bitRange>
              <description>Priority of interrupt 28</description>
              <name>IP_28</name>
            </field>
          </fields>
          <name>NVIC_IPR7</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed00</addressOffset>
          <description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:24]</bitRange>
              <description>Implementor code: 0x41 = ARM</description>
              <name>IMPLEMENTER</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:20]</bitRange>
              <description>Major revision number n in the rnpm revision status:\n
                0x0 = Revision 0.</description>
              <name>VARIANT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:16]</bitRange>
              <description>Constant that defines the architecture of the processor:\n
                0xC = ARMv6-M architecture.</description>
              <name>ARCHITECTURE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:4]</bitRange>
              <description>Number of processor within family: 0xC60 = Cortex-M0+</description>
              <name>PARTNO</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:0]</bitRange>
              <description>Minor revision number m in the rnpm revision status:\n
                0x1 = Patch 1.</description>
              <name>REVISION</name>
            </field>
          </fields>
          <name>CPUID</name>
          <resetValue>0x410cc601</resetValue>
        </register>
        <register>
          <addressOffset>0xed04</addressOffset>
          <description>Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <description>Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n
                NMI set-pending bit.\n
                Write:\n
                0 = No effect.\n
                1 = Changes NMI exception state to pending.\n
                Read:\n
                0 = NMI exception is not pending.\n
                1 = NMI exception is pending.\n
                Because NMI is the highest-priority exception, normally the processor enters the NMI\n
                exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n
                this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n
                NMI signal is reasserted while the processor is executing that handler.</description>
              <name>NMIPENDSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <description>PendSV set-pending bit.\n
                Write:\n
                0 = No effect.\n
                1 = Changes PendSV exception state to pending.\n
                Read:\n
                0 = PendSV exception is not pending.\n
                1 = PendSV exception is pending.\n
                Writing 1 to this bit is the only way to set the PendSV exception state to pending.</description>
              <name>PENDSVSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <description>PendSV clear-pending bit.\n
                Write:\n
                0 = No effect.\n
                1 = Removes the pending state from the PendSV exception.</description>
              <name>PENDSVCLR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <description>SysTick exception set-pending bit.\n
                Write:\n
                0 = No effect.\n
                1 = Changes SysTick exception state to pending.\n
                Read:\n
                0 = SysTick exception is not pending.\n
                1 = SysTick exception is pending.</description>
              <name>PENDSTSET</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <description>SysTick exception clear-pending bit.\n
                Write:\n
                0 = No effect.\n
                1 = Removes the pending state from the SysTick exception.\n
                This bit is WO. On a register read its value is Unknown.</description>
              <name>PENDSTCLR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <description>The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
              <name>ISRPREEMPT</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <description>External interrupt pending flag</description>
              <name>ISRPENDING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:12]</bitRange>
              <description>Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.</description>
              <name>VECTPENDING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:0]</bitRange>
              <description>Active exception number field. Reset clears the VECTACTIVE field.</description>
              <name>VECTACTIVE</name>
            </field>
          </fields>
          <name>ICSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed08</addressOffset>
          <description>The VTOR holds the vector table offset address.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Bits [31:8] of the indicate the vector table offset address.</description>
              <name>TBLOFF</name>
            </field>
          </fields>
          <name>VTOR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed0c</addressOffset>
          <description>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>Register key:\n
                Reads as Unknown\n
                On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</description>
              <name>VECTKEY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <description>Data endianness implemented:\n
                0 = Little-endian.</description>
              <name>ENDIANESS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description>
              <name>SYSRESETREQ</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</description>
              <name>VECTCLRACTIVE</name>
            </field>
          </fields>
          <name>AIRCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed10</addressOffset>
          <description>System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Send Event on Pending bit:\n
                0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n
                1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n
                When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n
                processor is not waiting for an event, the event is registered and affects the next WFE.\n
                The processor also wakes up on execution of an SEV instruction or an external event.</description>
              <name>SEVONPEND</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Controls whether the processor uses sleep or deep sleep as its low power mode:\n
                0 = Sleep.\n
                1 = Deep sleep.</description>
              <name>SLEEPDEEP</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n
                0 = Do not sleep when returning to Thread mode.\n
                1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n
                Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
              <name>SLEEPONEXIT</name>
            </field>
          </fields>
          <name>SCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed14</addressOffset>
          <description>The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <description>Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.</description>
              <name>STKALIGN</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Always reads as one, indicates that all unaligned accesses generate a HardFault.</description>
              <name>UNALIGN_TRP</name>
            </field>
          </fields>
          <name>CCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed1c</addressOffset>
          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of system handler 11, SVCall</description>
              <name>PRI_11</name>
            </field>
          </fields>
          <name>SHPR2</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed20</addressOffset>
          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:30]</bitRange>
              <description>Priority of system handler 15, SysTick</description>
              <name>PRI_15</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:22]</bitRange>
              <description>Priority of system handler 14, PendSV</description>
              <name>PRI_14</name>
            </field>
          </fields>
          <name>SHPR3</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed24</addressOffset>
          <description>Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <description>Reads as 1 if SVCall is Pending.  Write 1 to set pending SVCall, write 0 to clear pending SVCall.</description>
              <name>SVCALLPENDED</name>
            </field>
          </fields>
          <name>SHCSR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed90</addressOffset>
          <description>Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[23:16]</bitRange>
              <description>Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.</description>
              <name>IREGION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:8]</bitRange>
              <description>Number of regions supported by the MPU.</description>
              <name>DREGION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.</description>
              <name>SEPARATE</name>
            </field>
          </fields>
          <name>MPU_TYPE</name>
          <resetValue>0x00000800</resetValue>
        </register>
        <register>
          <addressOffset>0xed94</addressOffset>
          <description>Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n
                0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n
                covered by any enabled region causes a fault.\n
                1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n
                When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.</description>
              <name>PRIVDEFENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n
                When the MPU is enabled:\n
                0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n
                1 = the MPU is enabled during HardFault and NMI handlers.</description>
              <name>HFNMIENA</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n
                0 = MPU disabled.\n
                1 = MPU enabled.</description>
              <name>ENABLE</name>
            </field>
          </fields>
          <name>MPU_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed98</addressOffset>
          <description>Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n
                The MPU supports 8 memory regions, so the permitted values of this field are 0-7.</description>
              <name>REGION</name>
            </field>
          </fields>
          <name>MPU_RNR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xed9c</addressOffset>
          <description>Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Base address of the region.</description>
              <name>ADDR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n
                Write:\n
                0 = MPU_RNR not changed, and the processor:\n
                Updates the base address for the region specified in the MPU_RNR.\n
                Ignores the value of the REGION field.\n
                1 = The processor:\n
                Updates the value of the MPU_RNR to the value of the REGION field.\n
                Updates the base address for the region specified in the REGION field.\n
                Always reads as zero.</description>
              <name>VALID</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.</description>
              <name>REGION</name>
            </field>
          </fields>
          <name>MPU_RBAR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0xeda0</addressOffset>
          <description>Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:16]</bitRange>
              <description>The MPU Region Attribute field. Use to define the region attribute control.\n
                28 = XN: Instruction access disable bit:\n
                0 = Instruction fetches enabled.\n
                1 = Instruction fetches disabled.\n
                26:24 = AP: Access permission field\n
                18 = S: Shareable bit\n
                17 = C: Cacheable bit\n
                16 = B: Bufferable bit</description>
              <name>ATTRS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:8]</bitRange>
              <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.</description>
              <name>SRD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:1]</bitRange>
              <description>Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes</description>
              <name>SIZE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Enables the region.</description>
              <name>ENABLE</name>
            </field>
          </fields>
          <name>MPU_RASR</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
  </peripherals>
</device>