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Update README.md
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Kevin Santo Cappuccio
GitHub
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@ -287,7 +287,7 @@ Here's the schematic of just the crosspoints, the Nano header, and the breadboar
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If you look closely, you'll see that there generally 2 connections (I'm calling these 2 connections **Lanes** between each breadboard chip, except for the chip that is across from it on the breadboard. And every breadboard chip has one connection to each of the special function chips. The pins on the Nano header has a connection to 2 special function chips (interleaved to make it easier to connect continuous pairs of pins to the breadboard).
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Here's the high level outline of what NetsToChipConnections.cpp is doing
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Here's the high level outline of what [NetsToChipConnections.cpp](src/NetsToChipConnections.cpp) is doing
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- Sorts all the paths by Net
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This sort of sets priority, lower net numbers (so all the special function nets) will be picked first and are more likely to have direct connections chosen
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@ -312,10 +312,308 @@ At this point, any paths that have a simple direct connection should be done, no
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- Resolve uncommitted hops, anything set as -2 gets a random unconnected pin assigned to it at the very end so it doesn't take up connection space
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There's a lot more subltlety to this but if I go into any more detail you might as well just read the code itself. It will all be in the file NetsToChipConnections.cpp, and if you're running it on a Jumperless or just an RP2040, you can set the Chip Connections and Chip Connections Alt debug flags and it will show you everything it's doing in a somewhat nicely formatted way. There are comments in the code but there are a lot of nested array things that can get pretty confusing, if you need help understanding what's going on in a particular function, let me know and I'd be happy to walk you through it.
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There's a lot more subtlety to this but if I go into any more detail you might as well just read the code itself. It will all be in the file [NetsToChipConnections.cpp](src/NetsToChipConnections.cpp) , and if you're running it on a Jumperless or just an RP2040, you can set the Chip Connections and Chip Connections Alt debug flags and it will show you everything it's doing in a somewhat nicely formatted way. There are comments in the code but there are a lot of nested array things that can get pretty confusing, if you need help understanding what's going on in a particular function, let me know and I'd be happy to walk you through it.
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Here's the output with the debug flags on (with some redundant bits removed because it's really long)
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```
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sorting paths by net
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number of nets: 20
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path[0] net: 1
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path[1] net: 8
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path[2] net: 9
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path[3] net: 10
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path[4] net: 11
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path[5] net: 12
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path[6] net: 13
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path[7] net: 14
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path[8] net: 15
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path[9] net: 16
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path[10] net: 17
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path[11] net: 18
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path[12] net: 19
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number unique of nets: 26
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pathIndex: 13
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numberOfPaths: 13
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0 [24,GND,Net 1], 1 [D4,14,Net 8], 2 [10,36,Net 9], 3 [D6,40,Net 10],
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4 [D7,39,Net 11], 5 [D8,38,Net 12], 6 [D9,6,Net 13], 7 [D10,7,Net 14],
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8 [D11,9,Net 15], 9 [D12,8,Net 16], 10 [D3,25,Net 17], 11 [D2,23,Net 18],
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12 [D1,45,Net 19],
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finding start and end chips
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path[0]
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nodes [24-100]
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finding chips for nodes: 24-GND
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node: 1
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chip: D
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node: 2
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special function candidate chips: I J L
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Path 0 type: BB to SF
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Node 1: 24 Node 2: 100
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Chip 1: 3 Chip 2: -1
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path[1]
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nodes [74-14]
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finding chips for nodes: D4-14
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node: 1
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nano candidate chips: J K
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node: 2
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chip: B
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Path 1 type: BB to NANO
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Node 1: 14 Node 2: 74
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Chip 1: 1 Chip 2: -1
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... [removed for space]
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path[11]
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nodes [72-23]
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finding chips for nodes: D2-23
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node: 1
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nano candidate chips: J K
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node: 2
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chip: D
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Path 11 type: BB to NANO
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Node 1: 23 Node 2: 72
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Chip 1: 3 Chip 2: -1
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path[12]
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nodes [71-45]
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finding chips for nodes: D1-45
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node: 1
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nano chip: I
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node: 2
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chip: F
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Path 12 type: BB to NANO
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Node 1: 45 Node 2: 71
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Chip 1: 5 Chip 2: 8
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paths with candidates:
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0,1,3,4,5,6,7,8,9,10,11,
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resolving candidates
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chips least to most crowded:
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C: 0
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G: 0
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H: 0
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J: 0
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K: 0
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L: 0
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I: 1
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E: 2
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A: 3
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B: 3
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D: 3
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F: 3
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sf connections: I1
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sf connections: J0
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sf connections: K0
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sf connections: L0
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C: 0
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G: 0
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H: 0
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J: 0
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K: 0
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L: 0
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I: 1
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E: 2
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A: 3
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B: 3
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D: 3
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F: 3
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path[0] chip from D to chip J chosen
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sf connections: I1
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sf connections: J1
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sf connections: K0
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sf connections: L0
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C: 0
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G: 0
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H: 0
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K: 0
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L: 0
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I: 1
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J: 1
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E: 2
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A: 3
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B: 3
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D: 3
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F: 3
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path[1] chip from B to chip K chosen
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... [removed for space]
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sf connections: I4
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sf connections: J4
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sf connections: K3
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sf connections: L0
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C: 0
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G: 0
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H: 0
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L: 0
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E: 2
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A: 3
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B: 3
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D: 3
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F: 3
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K: 3
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I: 4
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J: 4
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path[11] chip from D to chip K chosen
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path[0] net: 1 24 to GND chip[0]: D x[0]: 7 y[0]: 2 chip[1]: J x[1]: 15 y[1]: 3 1 1
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path[1] net: 8 14 to D4 chip[0]: B x[0]: 11 y[0]: 6 chip[1]: K x[1]: 6 y[1]: 1 8 8
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path[2] net: 9 10 to 36 chip[0]: B x[0]: 8 y[0]: 2 chip[1]: E x[1]: 2 y[1]: 5 9 9
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path[3] net: 10 40 to D6 chip[0]: F x[0]: 11 y[0]: 2 chip[1]: J x[1]: 6 y[1]: 5 10 10
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path[4] net: 11 39 to D7 chip[0]: F x[0]: 10 y[0]: 1 chip[1]: I x[1]: 7 y[1]: 5 11 11
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path[5] net: 12 38 to D8 chip[0]: E x[0]: 1 y[0]: 7 chip[1]: K x[1]: 10 y[1]: 4 12 12
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path[6] net: 13 6 to D9 chip[0]: A x[0]: 0 y[0]: 5 chip[1]: I x[1]: 9 y[1]: 0 13 13
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path[7] net: 14 7 to D10 chip[0]: A x[0]: 1 y[0]: 6 chip[1]: J x[1]: 9 y[1]: 0 14 14
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path[8] net: 15 9 to D11 no direct path, setting altPathNeeded flag (BBtoSF)
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path[9] net: 16 8 to D12 no direct path, setting altPathNeeded flag (BBtoSF)
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path[10] net: 17 25 to D3 chip[0]: D x[0]: 6 y[0]: 3 chip[1]: I x[1]: 3 y[1]: 3 17 17
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path[11] net: 18 23 to D2 chip[0]: D x[0]: 15 y[0]: 1 chip[1]: K x[1]: 4 y[1]: 3 18 18
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path[12] net: 19 45 to D1 no direct path, setting altPathNeeded flag (BBtoSF)
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alt paths
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BBtoSF path: 8
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bb: A sfChip: K xMapBB: 0 yMapSF: 0 xStatus: 13
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bb: B sfChip: K xMapBB: -1 yMapSF: 1 xStatus: 65
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bb: C sfChip: K xMapBB: 4 yMapSF: 2 xStatus: -1
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bb: C sfChip: K xMapBB: 4 yMapSF: 2 xStatus: -1
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xMapL0c0: 4 xMapL1c0: 2 xMapL1c1: 5 xMapL0c1: 3
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8 chip[0]: B x[0]: 4 y[0]: 1 chip[1]: K x[1]: 13 y[1]: 2 15 -1
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Found Path!
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BBtoSF path: 9
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bb: A sfChip: J xMapBB: -1 yMapSF: 0 xStatus: 65
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bb: B sfChip: J xMapBB: 2 yMapSF: 1 xStatus: -1
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bb: B sfChip: J xMapBB: 2 yMapSF: 1 xStatus: -1
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xMapL0c0: 2 xMapL1c0: 0 xMapL1c1: 3 xMapL0c1: 1
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9 chip[0]: A x[0]: 2 y[0]: 7 chip[1]: J x[1]: 10 y[1]: 1 16 -1
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Found Path!
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BBtoSF path: 12
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bb: A sfChip: I xMapBB: 0 yMapSF: 0 xStatus: 13
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bb: B sfChip: I xMapBB: 2 yMapSF: 1 xStatus: 16
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bb: C sfChip: I xMapBB: 4 yMapSF: 2 xStatus: -1
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bb: C sfChip: I xMapBB: 4 yMapSF: 2 xStatus: 15
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xMapL0c0: 4 xMapL1c0: 10 xMapL1c1: 5 xMapL0c1: 11
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12 chip[0]: F x[0]: 4 y[0]: 7 chip[1]: I x[1]: 1 y[1]: 2 19 -1
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Found Path!
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resolving uncommitted hops
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path net node1 type chip0 x0 y0 node2 type chip1 x1 y1 altPath sameChp pathType chipL chip2 x2 y2 x3 y3
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0 1 24 0 D 7 2 GND 2 J 15 3 0 0 BB to SF 0
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1 8 14 0 B 11 6 D4 1 K 6 1 0 0 BB to NANO 0
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2 9 10 0 B 8 2 36 0 E 2 5 0 0 BB to BB 0
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3 10 40 0 F 11 2 D6 1 J 6 5 0 0 BB to NANO 0
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4 11 39 0 F 10 1 D7 1 I 7 5 0 0 BB to NANO 0
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5 12 38 0 E 1 7 D8 1 K 10 4 0 0 BB to NANO 0
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6 13 6 0 A 0 5 D9 1 I 9 0 0 0 BB to NANO 0
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7 14 7 0 A 1 6 D10 1 J 9 0 0 0 BB to NANO 0
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8 15 9 0 B 4 1 D11 1 K 13 2 0 1 BB to NANO 0 C 2 -2 13 -1
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9 16 8 0 A 2 7 D12 1 J 10 1 0 1 BB to NANO 0 B 0 -2 3 -1
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10 17 25 0 D 6 3 D3 1 I 3 3 0 0 BB to NANO 0
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11 18 23 0 D 15 1 D2 1 K 4 3 0 0 BB to NANO 0
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12 19 45 0 F 4 7 D1 1 I 1 2 0 1 BB to NANO 0 C 10 -2 4 -1
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path net node1 type chip0 x0 y0 node2 type chip1 x1 y1 altPath sameChp pathType chipL chip2 x2 y2 x3 y3
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taken connections (-1 is free)
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chip 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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A 13 14 16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 14 16
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B 16 -1 16 -1 15 -1 -1 -1 9 -1 -1 8 -1 -1 -1 -1 -1 15 9 -1 -1 -1 8 -1
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C -1 -1 15 -1 19 -1 -1 -1 -1 -1 19 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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D -1 -1 -1 -1 -1 -1 17 1 -1 -1 -1 -1 -1 -1 -1 18 -1 18 1 17 -1 -1 -1 -1
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E -1 12 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 -1 12
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F -1 -1 -1 -1 19 -1 -1 -1 -1 -1 11 10 -1 -1 -1 -1 -1 11 10 -1 -1 -1 -1 19
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G -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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H -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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chip 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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I -1 19 -1 17 -1 -1 -1 11 15 13 -1 -1 -1 -1 -1 1 13 -1 19 17 -1 11 -1 -1
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J -1 -1 18 -1 8 -1 10 -1 12 14 16 -1 -1 -1 -1 1 14 16 -1 1 -1 10 -1 -1
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K -1 -1 -1 -1 18 17 8 -1 10 11 12 13 14 15 16 -1 -1 8 15 18 12 -1 -1 -1
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L -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1
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8 same chips: @, @, @, @, @, @, C, C,
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9 same chips: @, @, @, @, @, @, B, B,
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12 same chips: @, @, @, @, @, @, C, C,
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final paths
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path net node1 type chip0 x0 y0 node2 type chip1 x1 y1 altPath sameChp pathType chipL chip2 x2 y2 x3 y3
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0 1 24 0 D 7 2 GND 2 J 15 3 0 0 BB to SF 0
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1 8 14 0 B 11 6 D4 1 K 6 1 0 0 BB to NANO 0
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2 9 10 0 B 8 2 36 0 E 2 5 0 0 BB to BB 0
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3 10 40 0 F 11 2 D6 1 J 6 5 0 0 BB to NANO 0
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4 11 39 0 F 10 1 D7 1 I 7 5 0 0 BB to NANO 0
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5 12 38 0 E 1 7 D8 1 K 10 4 0 0 BB to NANO 0
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6 13 6 0 A 0 5 D9 1 I 9 0 0 0 BB to NANO 0
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7 14 7 0 A 1 6 D10 1 J 9 0 0 0 BB to NANO 0
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8 15 9 0 B 4 1 D11 1 K 13 2 0 1 BB to NANO 0 C 2 0 13 0
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9 16 8 0 A 2 7 D12 1 J 10 1 0 1 BB to NANO 0 B 0 0 3 0
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10 17 25 0 D 6 3 D3 1 I 3 3 0 0 BB to NANO 0
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11 18 23 0 D 15 1 D2 1 K 4 3 0 0 BB to NANO 0
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12 19 45 0 F 4 7 D1 1 I 1 2 0 1 BB to NANO 0 C 10 1 4 1
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path net node1 type chip0 x0 y0 node2 type chip1 x1 y1 altPath sameChp pathType chipL chip2 x2 y2 x3 y3
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```
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