mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-12 18:21:07 +01:00
40 lines
1.1 KiB
C#
40 lines
1.1 KiB
C#
|
using ChocolArm64.Instructions;
|
||
|
using ChocolArm64.State;
|
||
|
using System;
|
||
|
|
||
|
namespace ChocolArm64.Decoders
|
||
|
{
|
||
|
class OpCode64 : IOpCode64
|
||
|
{
|
||
|
public long Position { get; private set; }
|
||
|
public int RawOpCode { get; private set; }
|
||
|
|
||
|
public InstEmitter Emitter { get; protected set; }
|
||
|
public InstInterpreter Interpreter { get; protected set; }
|
||
|
public RegisterSize RegisterSize { get; protected set; }
|
||
|
|
||
|
public OpCode64(Inst inst, long position, int opCode)
|
||
|
{
|
||
|
Position = position;
|
||
|
RawOpCode = opCode;
|
||
|
|
||
|
RegisterSize = RegisterSize.Int64;
|
||
|
|
||
|
Emitter = inst.Emitter;
|
||
|
Interpreter = inst.Interpreter;
|
||
|
}
|
||
|
|
||
|
public int GetBitsCount()
|
||
|
{
|
||
|
switch (RegisterSize)
|
||
|
{
|
||
|
case RegisterSize.Int32: return 32;
|
||
|
case RegisterSize.Int64: return 64;
|
||
|
case RegisterSize.Simd64: return 64;
|
||
|
case RegisterSize.Simd128: return 128;
|
||
|
}
|
||
|
|
||
|
throw new InvalidOperationException();
|
||
|
}
|
||
|
}
|
||
|
}
|