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misc: chore: Use explicit types in CPU project

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This commit is contained in:
Evan Husted 2025-01-25 14:04:43 -06:00
parent a97fd4beb1
commit 5099548856
18 changed files with 40 additions and 40 deletions
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14
src/Ryujinx.Cpu/AddressTable.cs
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@ -49,7 +49,7 @@ namespace ARMeilleure.Common
public TableSparseBlock(ulong size, Action<IntPtr> ensureMapped, PageInitDelegate pageInit)
{
var block = new SparseMemoryBlock(size, pageInit, null);
SparseMemoryBlock block = new SparseMemoryBlock(size, pageInit, null);
_trackingEvent = (ulong address, ulong size, bool write) =>
{
@ -146,7 +146,7 @@ namespace ARMeilleure.Common
Levels = levels;
Mask = 0;
foreach (var level in Levels)
foreach (AddressTableLevel level in Levels)
{
Mask |= level.Mask;
}
@ -363,7 +363,7 @@ namespace ARMeilleure.Common
/// <returns>The new sparse block that was added</returns>
private TableSparseBlock ReserveNewSparseBlock()
{
var block = new TableSparseBlock(_sparseBlockSize, EnsureMapped, InitLeafPage);
TableSparseBlock block = new TableSparseBlock(_sparseBlockSize, EnsureMapped, InitLeafPage);
_sparseReserved.Add(block);
_sparseReservedOffset = 0;
@ -381,7 +381,7 @@ namespace ARMeilleure.Common
/// <returns>Allocated block</returns>
private IntPtr Allocate<T>(int length, T fill, bool leaf) where T : unmanaged
{
var size = sizeof(T) * length;
int size = sizeof(T) * length;
AddressTablePage page;
@ -413,10 +413,10 @@ namespace ARMeilleure.Common
}
else
{
var address = (IntPtr)NativeAllocator.Instance.Allocate((uint)size);
IntPtr address = (IntPtr)NativeAllocator.Instance.Allocate((uint)size);
page = new AddressTablePage(false, address);
var span = new Span<T>((void*)page.Address, length);
Span<T> span = new Span<T>((void*)page.Address, length);
span.Fill(fill);
}
@ -445,7 +445,7 @@ namespace ARMeilleure.Common
{
if (!_disposed)
{
foreach (var page in _pages)
foreach (AddressTablePage page in _pages)
{
if (!page.IsSparse)
{

2
src/Ryujinx.Cpu/AppleHv/HvAddressSpace.cs
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@ -29,7 +29,7 @@ namespace Ryujinx.Cpu.AppleHv
public HvAddressSpace(MemoryBlock backingMemory, ulong asSize)
{
(_asBase, var ipaAllocator) = HvVm.CreateAddressSpace(backingMemory);
(_asBase, HvIpaAllocator ipaAllocator) = HvVm.CreateAddressSpace(backingMemory);
_backingSize = backingMemory.Size;
_userRange = new HvAddressSpaceRange(ipaAllocator);

2
src/Ryujinx.Cpu/AppleHv/HvMemoryBlockAllocator.cs
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@ -45,7 +45,7 @@ namespace Ryujinx.Cpu.AppleHv
public HvMemoryBlockAllocation Allocate(ulong size, ulong alignment)
{
var allocation = Allocate(size, alignment, CreateBlock);
Allocation allocation = Allocate(size, alignment, CreateBlock);
return new HvMemoryBlockAllocation(this, allocation.Block, allocation.Offset, allocation.Size);
}

6
src/Ryujinx.Cpu/AppleHv/HvMemoryManager.cs
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@ -233,13 +233,13 @@ namespace Ryujinx.Cpu.AppleHv
yield break;
}
var guestRegions = GetPhysicalRegionsImpl(va, size);
IEnumerable<MemoryRange> guestRegions = GetPhysicalRegionsImpl(va, size);
if (guestRegions == null)
{
yield break;
}
foreach (var guestRegion in guestRegions)
foreach (MemoryRange guestRegion in guestRegions)
{
nint pointer = _backingMemory.GetPointer(guestRegion.Address, guestRegion.Size);
yield return new HostMemoryRange((nuint)(ulong)pointer, guestRegion.Size);
@ -254,7 +254,7 @@ namespace Ryujinx.Cpu.AppleHv
yield break;
}
foreach (var physicalRegion in GetPhysicalRegionsImpl(va, size))
foreach (MemoryRange physicalRegion in GetPhysicalRegionsImpl(va, size))
{
yield return physicalRegion;
}

2
src/Ryujinx.Cpu/AppleHv/HvVcpu.cs
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@ -41,7 +41,7 @@ namespace Ryujinx.Cpu.AppleHv
{
// Calculate our time delta in ticks based on the current clock frequency.
int result = TimeApi.mach_timebase_info(out var timeBaseInfo);
int result = TimeApi.mach_timebase_info(out MachTimebaseInfo timeBaseInfo);
Debug.Assert(result == 0);

2
src/Ryujinx.Cpu/AppleHv/HvVm.cs
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@ -39,7 +39,7 @@ namespace Ryujinx.Cpu.AppleHv
baseAddress = ipaAllocator.Allocate(block.Size, AsIpaAlignment);
}
var rwx = HvMemoryFlags.Read | HvMemoryFlags.Write | HvMemoryFlags.Exec;
HvMemoryFlags rwx = HvMemoryFlags.Read | HvMemoryFlags.Write | HvMemoryFlags.Exec;
HvApi.hv_vm_map((ulong)block.Pointer, baseAddress, block.Size, rwx).ThrowOnError();

2
src/Ryujinx.Cpu/Jit/HostTracked/AddressSpacePartition.cs
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@ -127,7 +127,7 @@ namespace Ryujinx.Cpu.Jit.HostTracked
Debug.Assert(leftSize > 0);
Debug.Assert(rightSize > 0);
(var leftAllocation, PrivateAllocation) = PrivateAllocation.Split(leftSize);
(PrivateMemoryAllocation leftAllocation, PrivateAllocation) = PrivateAllocation.Split(leftSize);
PrivateMapping left = new(Address, leftSize, leftAllocation);

6
src/Ryujinx.Cpu/Jit/MemoryManager.cs
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@ -253,13 +253,13 @@ namespace Ryujinx.Cpu.Jit
yield break;
}
var guestRegions = GetPhysicalRegionsImpl(va, size);
IEnumerable<MemoryRange> guestRegions = GetPhysicalRegionsImpl(va, size);
if (guestRegions == null)
{
yield break;
}
foreach (var guestRegion in guestRegions)
foreach (MemoryRange guestRegion in guestRegions)
{
nint pointer = _backingMemory.GetPointer(guestRegion.Address, guestRegion.Size);
yield return new HostMemoryRange((nuint)(ulong)pointer, guestRegion.Size);
@ -274,7 +274,7 @@ namespace Ryujinx.Cpu.Jit
yield break;
}
foreach (var physicalRegion in GetPhysicalRegionsImpl(va, size))
foreach (MemoryRange physicalRegion in GetPhysicalRegionsImpl(va, size))
{
yield return physicalRegion;
}

2
src/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
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@ -340,7 +340,7 @@ namespace Ryujinx.Cpu.Jit
{
int pages = GetPagesCount(va, (uint)size, out va);
var regions = new List<MemoryRange>();
List<MemoryRange> regions = new List<MemoryRange>();
ulong regionStart = GetPhysicalAddressChecked(va);
ulong regionSize = PageSize;

4
src/Ryujinx.Cpu/Jit/MemoryManagerHostTracked.cs
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@ -240,7 +240,7 @@ namespace Ryujinx.Cpu.Jit
if (TryGetVirtualContiguous(va, data.Length, out MemoryBlock memoryBlock, out ulong offset))
{
var target = memoryBlock.GetSpan(offset, data.Length);
Span<byte> target = memoryBlock.GetSpan(offset, data.Length);
bool changed = !data.SequenceEqual(target);
@ -443,7 +443,7 @@ namespace Ryujinx.Cpu.Jit
return null;
}
var regions = new List<HostMemoryRange>();
List<HostMemoryRange> regions = new List<HostMemoryRange>();
ulong endVa = va + size;
try

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitFlow.cs
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@ -205,7 +205,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
for (int i = 0; i < funcTable.Levels.Length; i++)
{
var level = funcTable.Levels[i];
AddressTableLevel level = funcTable.Levels[i];
asm.Ubfx(indexReg, guestAddress, level.Index, level.Length);
asm.Lsl(indexReg, indexReg, Const(3));

2
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs
View File

@ -370,7 +370,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
for (int i = 0; i < funcTable.Levels.Length; i++)
{
var level = funcTable.Levels[i];
AddressTableLevel level = funcTable.Levels[i];
asm.Ubfx(indexReg, guestAddress, level.Index, level.Length);
asm.Lsl(indexReg, indexReg, Const(3));

2
src/Ryujinx.Cpu/LightningJit/Cache/NoWxCache.cs
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@ -190,7 +190,7 @@ namespace Ryujinx.Cpu.LightningJit.Cache
private bool TryGetThreadLocalFunction(ulong guestAddress, out nint funcPtr)
{
if ((_threadLocalCache ??= new()).TryGetValue(guestAddress, out var entry))
if ((_threadLocalCache ??= new()).TryGetValue(guestAddress, out ThreadLocalCacheEntry entry))
{
if (entry.IncrementUseCount() >= MinCallsForPad)
{

10
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
View File

@ -41,7 +41,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int targetIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.TargetIndex = targetIndex;
state.HasTarget = true;
@ -68,7 +68,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -94,7 +94,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -113,7 +113,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -342,7 +342,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
public readonly void Cset(Operand rd, ArmCondition condition)
{
var zr = new Operand(ZrRegister, RegisterType.Integer, rd.Type);
Operand zr = new Operand(ZrRegister, RegisterType.Integer, rd.Type);
Csinc(rd, zr, zr, (ArmCondition)((int)condition ^ 1));
}

4
src/Ryujinx.Cpu/LightningJit/Translator.cs
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@ -163,14 +163,14 @@ namespace Ryujinx.Cpu.LightningJit
{
List<TranslatedFunction> functions = Functions.AsList();
foreach (var func in functions)
foreach (TranslatedFunction func in functions)
{
JitCache.Unmap(func.FuncPointer);
}
Functions.Clear();
while (_oldFuncs.TryDequeue(out var kv))
while (_oldFuncs.TryDequeue(out KeyValuePair<ulong, TranslatedFunction> kv))
{
JitCache.Unmap(kv.Value.FuncPointer);
}

2
src/Ryujinx.Cpu/LightningJit/TranslatorStubs.cs
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@ -174,7 +174,7 @@ namespace Ryujinx.Cpu.LightningJit
for (int i = 0; i < _functionTable.Levels.Length; i++)
{
ref var level = ref _functionTable.Levels[i];
ref AddressTableLevel level = ref _functionTable.Levels[i];
asm.Mov(mask, level.Mask >> level.Index);
asm.And(index, mask, guestAddress, ArmShiftType.Lsr, level.Index);

14
src/Ryujinx.Cpu/PrivateMemoryAllocator.cs
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@ -48,7 +48,7 @@ namespace Ryujinx.Cpu
{
for (int i = 0; i < _freeRanges.Count; i++)
{
var range = _freeRanges[i];
Range range = _freeRanges[i];
ulong alignedOffset = BitUtils.AlignUp(range.Offset, alignment);
ulong sizeDelta = alignedOffset - range.Offset;
@ -84,7 +84,7 @@ namespace Ryujinx.Cpu
private void InsertFreeRange(ulong offset, ulong size)
{
var range = new Range(offset, size);
Range range = new Range(offset, size);
int index = _freeRanges.BinarySearch(range);
if (index < 0)
{
@ -97,7 +97,7 @@ namespace Ryujinx.Cpu
private void InsertFreeRangeComingled(ulong offset, ulong size)
{
ulong endOffset = offset + size;
var range = new Range(offset, size);
Range range = new Range(offset, size);
int index = _freeRanges.BinarySearch(range);
if (index < 0)
{
@ -149,7 +149,7 @@ namespace Ryujinx.Cpu
public PrivateMemoryAllocation Allocate(ulong size, ulong alignment)
{
var allocation = Allocate(size, alignment, CreateBlock);
Allocation allocation = Allocate(size, alignment, CreateBlock);
return new PrivateMemoryAllocation(this, allocation.Block, allocation.Offset, allocation.Size);
}
@ -200,7 +200,7 @@ namespace Ryujinx.Cpu
for (int i = 0; i < _blocks.Count; i++)
{
var block = _blocks[i];
T block = _blocks[i];
if (block.Size >= size)
{
@ -214,8 +214,8 @@ namespace Ryujinx.Cpu
ulong blockAlignedSize = BitUtils.AlignUp(size, _blockAlignment);
var memory = new MemoryBlock(blockAlignedSize, _allocationFlags);
var newBlock = createBlock(memory, blockAlignedSize);
MemoryBlock memory = new MemoryBlock(blockAlignedSize, _allocationFlags);
T newBlock = createBlock(memory, blockAlignedSize);
InsertBlock(newBlock);

2
src/Ryujinx.Cpu/Signal/NativeSignalHandler.cs
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@ -98,7 +98,7 @@ namespace Ryujinx.Cpu.Signal
_signalHandlerPtr = customSignalHandlerFactory(UnixSignalHandlerRegistration.GetSegfaultExceptionHandler().sa_handler, _signalHandlerPtr);
}
var old = UnixSignalHandlerRegistration.RegisterExceptionHandler(_signalHandlerPtr);
UnixSignalHandlerRegistration.SigAction old = UnixSignalHandlerRegistration.RegisterExceptionHandler(_signalHandlerPtr);
config.UnixOldSigaction = (nuint)(ulong)old.sa_handler;
config.UnixOldSigaction3Arg = old.sa_flags & 4;