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https://github.com/GreemDev/Ryujinx.git
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Implement VMAD shader instruction and improve InvocationInfo and ISBERD handling (#3251)
* Implement VMAD shader instruction and improve InvocationInfo and ISBERD handling * Shader cache version bump * Fix typo
This commit is contained in:
parent
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commit
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@ -40,7 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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/// <summary>
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/// <summary>
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/// Version of the codegen (to be changed when codegen or guest format change).
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/// Version of the codegen (to be changed when codegen or guest format change).
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/// </summary>
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/// </summary>
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private const ulong ShaderCodeGenVersion = 3184;
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private const ulong ShaderCodeGenVersion = 3251;
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// Progress reporting helpers
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// Progress reporting helpers
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private volatile int _shaderCount;
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private volatile int _shaderCount;
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@ -250,9 +250,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
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: "gl_SubgroupInvocationID";
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: "gl_SubgroupInvocationID";
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}
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}
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// TODO: There must be a better way to handle this...
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if (config.Stage == ShaderStage.Fragment)
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if (config.Stage == ShaderStage.Fragment)
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{
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{
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// TODO: There must be a better way to handle this...
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switch (value)
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switch (value)
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{
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{
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case AttributeConsts.PositionX: return $"(gl_FragCoord.x / {DefaultNames.SupportBlockRenderScaleName}[0])";
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case AttributeConsts.PositionX: return $"(gl_FragCoord.x / {DefaultNames.SupportBlockRenderScaleName}[0])";
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@ -5144,6 +5144,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public bool PredInv => (_opcode & 0x80000) != 0;
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public bool PredInv => (_opcode & 0x80000) != 0;
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public int Imm16 => (int)((_opcode >> 20) & 0xFFFF);
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public bool WriteCC => (_opcode & 0x800000000000) != 0;
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public bool WriteCC => (_opcode & 0x800000000000) != 0;
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public AvgMode AvgMode => (AvgMode)((_opcode >> 56) & 0x3);
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public AvgMode AvgMode => (AvgMode)((_opcode >> 56) & 0x3);
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public bool DFormat => (_opcode & 0x40000000000000) != 0;
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public bool DFormat => (_opcode & 0x40000000000000) != 0;
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@ -5164,6 +5165,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public int SrcC => (int)((_opcode >> 39) & 0xFF);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public int Pred => (int)((_opcode >> 16) & 0x7);
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public bool PredInv => (_opcode & 0x80000) != 0;
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public bool PredInv => (_opcode & 0x80000) != 0;
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public int Imm16 => (int)((_opcode >> 20) & 0xFFFF);
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public bool WriteCC => (_opcode & 0x800000000000) != 0;
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public bool WriteCC => (_opcode & 0x800000000000) != 0;
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public VectorSelect ASelect => (VectorSelect)((int)((_opcode >> 45) & 0x8) | (int)((_opcode >> 36) & 0x7));
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public VectorSelect ASelect => (VectorSelect)((int)((_opcode >> 45) & 0x8) | (int)((_opcode >> 36) & 0x7));
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public VectorSelect BSelect => (VectorSelect)((int)((_opcode >> 46) & 0x8) | (int)((_opcode >> 28) & 0x7));
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public VectorSelect BSelect => (VectorSelect)((int)((_opcode >> 46) & 0x8) | (int)((_opcode >> 28) & 0x7));
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@ -13,16 +13,28 @@ namespace Ryujinx.Graphics.Shader
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{
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{
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public static string ToGlslString(this InputTopology topology)
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public static string ToGlslString(this InputTopology topology)
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{
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{
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switch (topology)
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return topology switch
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{
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{
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case InputTopology.Points: return "points";
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InputTopology.Points => "points",
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case InputTopology.Lines: return "lines";
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InputTopology.Lines => "lines",
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case InputTopology.LinesAdjacency: return "lines_adjacency";
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InputTopology.LinesAdjacency => "lines_adjacency",
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case InputTopology.Triangles: return "triangles";
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InputTopology.Triangles => "triangles",
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case InputTopology.TrianglesAdjacency: return "triangles_adjacency";
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InputTopology.TrianglesAdjacency => "triangles_adjacency",
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_ => "points"
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};
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}
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}
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return "points";
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public static int ToInputVertices(this InputTopology topology)
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{
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return topology switch
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{
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InputTopology.Points => 1,
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InputTopology.Lines or
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InputTopology.LinesAdjacency => 2,
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InputTopology.Triangles or
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InputTopology.TrianglesAdjacency => 3,
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_ => 1
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};
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}
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}
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}
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}
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}
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}
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@ -73,6 +73,26 @@ namespace Ryujinx.Graphics.Shader.Instructions
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};
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};
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}
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}
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public static Operand Extend(EmitterContext context, Operand src, VectorSelect type)
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{
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return type switch
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{
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VectorSelect.U8B0 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(0)), 8),
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VectorSelect.U8B1 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(8)), 8),
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VectorSelect.U8B2 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(16)), 8),
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VectorSelect.U8B3 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
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VectorSelect.U16H0 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
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VectorSelect.U16H1 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
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VectorSelect.S8B0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 8),
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VectorSelect.S8B1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(8)), 8),
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VectorSelect.S8B2 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 8),
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VectorSelect.S8B3 => SignExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
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VectorSelect.S16H0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
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VectorSelect.S16H1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
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_ => src
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};
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}
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public static void SetZnFlags(EmitterContext context, Operand dest, bool setCC, bool extended = false)
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public static void SetZnFlags(EmitterContext context, Operand dest, bool setCC, bool extended = false)
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{
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{
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if (!setCC)
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if (!setCC)
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@ -118,6 +138,15 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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}
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}
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}
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public static (Operand, Operand) NegateLong(EmitterContext context, Operand low, Operand high)
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{
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low = context.BitwiseNot(low);
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high = context.BitwiseNot(high);
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low = AddWithCarry(context, low, Const(1), out Operand carryOut);
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high = context.IAdd(high, carryOut);
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return (low, high);
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}
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public static Operand AddWithCarry(EmitterContext context, Operand lhs, Operand rhs, out Operand carryOut)
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public static Operand AddWithCarry(EmitterContext context, Operand lhs, Operand rhs, out Operand carryOut)
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{
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{
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Operand result = context.IAdd(lhs, rhs);
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Operand result = context.IAdd(lhs, rhs);
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@ -168,10 +168,11 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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{
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InstIsberd op = context.GetOp<InstIsberd>();
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InstIsberd op = context.GetOp<InstIsberd>();
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// This instruction performs a load from ISBE memory,
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// This instruction performs a load from ISBE (Internal Stage Buffer Entry) memory.
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// however it seems to be only used to get some vertex
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// Here, we just propagate the offset, as the result from this instruction is usually
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// input data, so we instead propagate the offset so that
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// used with ALD to perform vertex load on geometry or tessellation shaders.
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// it can be used on the attribute load.
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// The offset is calculated as (PrimitiveIndex * VerticesPerPrimitive) + VertexIndex.
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// Since we hardcode PrimitiveIndex to zero, then the offset will be just VertexIndex.
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context.Copy(GetDest(op.Dest), GetSrcReg(context, op.SrcA));
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context.Copy(GetDest(op.Dest), GetSrcReg(context, op.SrcA));
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}
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}
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@ -94,31 +94,19 @@ namespace Ryujinx.Graphics.Shader.Instructions
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case SReg.InvocationInfo:
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case SReg.InvocationInfo:
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if (context.Config.Stage != ShaderStage.Compute && context.Config.Stage != ShaderStage.Fragment)
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if (context.Config.Stage != ShaderStage.Compute && context.Config.Stage != ShaderStage.Fragment)
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{
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{
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Operand primitiveId = Attribute(AttributeConsts.PrimitiveId);
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// Note: Lowest 8-bits seems to contain some primitive index,
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Operand patchVerticesIn;
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// but it seems to be NVIDIA implementation specific as it's only used
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// to calculate ISBE offsets, so we can just keep it as zero.
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if (context.Config.Stage == ShaderStage.TessellationEvaluation)
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if (context.Config.Stage == ShaderStage.TessellationControl ||
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context.Config.Stage == ShaderStage.TessellationEvaluation)
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{
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{
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patchVerticesIn = context.ShiftLeft(Attribute(AttributeConsts.PatchVerticesIn), Const(16));
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src = context.ShiftLeft(Attribute(AttributeConsts.PatchVerticesIn), Const(16));
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}
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}
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else
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else
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{
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{
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InputTopology inputTopology = context.Config.GpuAccessor.QueryPrimitiveTopology();
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src = Const(context.Config.GpuAccessor.QueryPrimitiveTopology().ToInputVertices() << 16);
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int inputVertices = inputTopology switch
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{
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InputTopology.Points => 1,
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InputTopology.Lines or
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InputTopology.LinesAdjacency => 2,
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InputTopology.Triangles or
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InputTopology.TrianglesAdjacency => 3,
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_ => 1
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};
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patchVerticesIn = Const(inputVertices << 16);
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}
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}
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src = context.BitwiseOr(primitiveId, patchVerticesIn);
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}
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}
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else
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else
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{
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{
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@ -1,7 +1,9 @@
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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{
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@ -11,8 +13,106 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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{
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InstVmad op = context.GetOp<InstVmad>();
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InstVmad op = context.GetOp<InstVmad>();
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// TODO: Implement properly.
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bool aSigned = (op.ASelect & VectorSelect.S8B0) != 0;
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context.Copy(GetDest(op.Dest), GetSrcReg(context, op.SrcC));
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bool bSigned = (op.BSelect & VectorSelect.S8B0) != 0;
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Operand srcA = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcC = context.INegate(GetSrcReg(context, op.SrcC), op.AvgMode == AvgMode.NegB);
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Operand srcB;
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if (op.BVideo)
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{
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srcB = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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}
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else
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{
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int imm = op.Imm16;
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if (bSigned)
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{
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imm = (imm << 16) >> 16;
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}
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srcB = Const(imm);
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}
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Operand productLow = context.IMultiply(srcA, srcB);
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Operand productHigh;
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if (aSigned == bSigned)
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{
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productHigh = aSigned
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? context.MultiplyHighS32(srcA, srcB)
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: context.MultiplyHighU32(srcA, srcB);
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}
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else
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{
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Operand temp = aSigned
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? context.IMultiply(srcB, context.ShiftRightS32(srcA, Const(31)))
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: context.IMultiply(srcA, context.ShiftRightS32(srcB, Const(31)));
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productHigh = context.IAdd(temp, context.MultiplyHighU32(srcA, srcB));
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}
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if (op.AvgMode == AvgMode.NegA)
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{
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(productLow, productHigh) = InstEmitAluHelper.NegateLong(context, productLow, productHigh);
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}
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Operand resLow = InstEmitAluHelper.AddWithCarry(context, productLow, srcC, out Operand sumCarry);
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Operand resHigh = context.IAdd(productHigh, sumCarry);
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if (op.AvgMode == AvgMode.PlusOne)
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{
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resLow = InstEmitAluHelper.AddWithCarry(context, resLow, Const(1), out Operand poCarry);
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resHigh = context.IAdd(resHigh, poCarry);
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}
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bool resSigned = op.ASelect == VectorSelect.S32 ||
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op.BSelect == VectorSelect.S32 ||
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op.AvgMode == AvgMode.NegB ||
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op.AvgMode == AvgMode.NegA;
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int shift = op.VideoScale switch
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{
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VideoScale.Shr7 => 7,
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VideoScale.Shr15 => 15,
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_ => 0
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};
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if (shift != 0)
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{
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// Low = (Low >> Shift) | (High << (32 - Shift))
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// High >>= Shift
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resLow = context.ShiftRightU32(resLow, Const(shift));
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resLow = context.BitwiseOr(resLow, context.ShiftLeft(resHigh, Const(32 - shift)));
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resHigh = resSigned
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? context.ShiftRightS32(resHigh, Const(shift))
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: context.ShiftRightU32(resHigh, Const(shift));
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}
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Operand res = resLow;
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if (op.Sat)
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{
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Operand sign = context.ShiftRightS32(resHigh, Const(31));
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if (resSigned)
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{
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Operand overflow = context.ICompareNotEqual(resHigh, context.ShiftRightS32(resLow, Const(31)));
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Operand clampValue = context.ConditionalSelect(sign, Const(int.MinValue), Const(int.MaxValue));
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res = context.ConditionalSelect(overflow, clampValue, resLow);
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}
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else
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{
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Operand overflow = context.ICompareNotEqual(resHigh, Const(0));
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res = context.ConditionalSelect(overflow, context.BitwiseNot(sign), resLow);
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}
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}
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context.Copy(GetDest(op.Dest), res);
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// TODO: CC.
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}
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}
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}
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}
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}
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}
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{
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{
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InstVmnmx op = context.GetOp<InstVmnmx>();
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InstVmnmx op = context.GetOp<InstVmnmx>();
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Operand srcA = Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcA = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcC = GetSrcReg(context, op.SrcC);
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Operand srcC = GetSrcReg(context, op.SrcC);
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Operand srcB;
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Operand srcB;
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if (op.BVideo)
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if (op.BVideo)
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{
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{
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srcB = Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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srcB = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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}
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}
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else
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else
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{
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{
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@ -124,13 +123,12 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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{
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InstVsetp op = context.GetOp<InstVsetp>();
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InstVsetp op = context.GetOp<InstVsetp>();
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Operand srcA = Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcA = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcB;
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Operand srcB;
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if (op.BVideo)
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if (op.BVideo)
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{
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{
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srcB = Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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srcB = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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}
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}
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else
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else
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{
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{
|
||||||
@ -181,25 +179,5 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||||||
context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
|
context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
|
||||||
context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
|
context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static Operand Extend(EmitterContext context, Operand src, VectorSelect type)
|
|
||||||
{
|
|
||||||
return type switch
|
|
||||||
{
|
|
||||||
VectorSelect.U8B0 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(0)), 8),
|
|
||||||
VectorSelect.U8B1 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(8)), 8),
|
|
||||||
VectorSelect.U8B2 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(16)), 8),
|
|
||||||
VectorSelect.U8B3 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
|
|
||||||
VectorSelect.U16H0 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
|
|
||||||
VectorSelect.U16H1 => ZeroExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
|
|
||||||
VectorSelect.S8B0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 8),
|
|
||||||
VectorSelect.S8B1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(8)), 8),
|
|
||||||
VectorSelect.S8B2 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 8),
|
|
||||||
VectorSelect.S8B3 => SignExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
|
|
||||||
VectorSelect.S16H0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
|
|
||||||
VectorSelect.S16H1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
|
|
||||||
_ => src
|
|
||||||
};
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
Loading…
Reference in New Issue
Block a user