12 Commits

Author	SHA1	Message	Date
gdkchan	161193e113	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	7c314eadcf	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	7ed1153062	Add SHRN instruction, and fix ADDV	2018-02-14 02:43:21 -03:00
gdkchan	7d11a146c0	Generate CIL for SCVTF (vector), add undefined encodings for some instructions	2018-02-12 00:37:20 -03:00
gdkchan	9f612682e0	Add BRK on the opcode table	2018-02-10 12:16:48 -03:00
gdkchan	ccc9ce1908	Move a few more SIMD instructions to emit CIL directly instead of a method call	2018-02-09 17:14:47 -03:00
gdkchan	6a3aa6cd88	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00
gdkchan	d0954564cd	Add ADC and SBC instructions	2018-02-07 20:46:36 -03:00
gdkchan	79f028e410	Add FMADD and FMSUB instructions	2018-02-07 20:07:16 -03:00
gdkchan	768b573772	Add FMOV (scalar, register) and FCMPE instructions	2018-02-07 19:43:52 -03:00
gdkchan	d77d691381	Implement SSHL instruction, fix exception on FMAX/FMIN, and use a better exception message for undefined/unimplemented instructions	2018-02-07 09:38:43 -03:00
gdkchan	b7e1d9930d	aloha	2018-02-04 20:08:20 -03:00