mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-02 21:47:18 +01:00
17620d18db
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection
Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.
* ARMeilleure: Add initial support for EVEX instruction encoding
Does not implement rounding, or exception controls.
* ARMeilleure: Add `X86Vpternlogd`
Accelerates the vector-`Not` instruction.
* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}
* ARMeilleure: Add check for `XCR0` flags
Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.
* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting
* ARMeilleure: Move XCR0 procedure to GetXcr0Eax
* ARMeilleure: Add `XCR0` to `FeatureInfo` structure
* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly
Avoids an additional allocation
* ARMeilleure: Formatting fixes
* ARMeilleure: Fix EVEX encoding src2 register index
> Just like in VEX prefix, vvvv is provided in inverted form.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`
Passes unit tests, verified instruction utilization
* ARMeilleure: Fix EVEX register operand designations
Operand 2 was being sourced improperly.
EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm
This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`
* ARMeilleure: PTC version bump
* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail
* ARMeilleure: Update EVEX encoding comment capitalization
632 lines
13 KiB
C#
632 lines
13 KiB
C#
namespace ARMeilleure.IntermediateRepresentation
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{
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enum Intrinsic : ushort
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{
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// X86 (SSE and AVX)
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X86Addpd,
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X86Addps,
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X86Addsd,
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X86Addss,
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X86Aesdec,
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X86Aesdeclast,
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X86Aesenc,
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X86Aesenclast,
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X86Aesimc,
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X86Andnpd,
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X86Andnps,
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X86Andpd,
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X86Andps,
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X86Blendvpd,
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X86Blendvps,
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X86Cmppd,
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X86Cmpps,
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X86Cmpsd,
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X86Cmpss,
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X86Comisdeq,
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X86Comisdge,
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X86Comisdlt,
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X86Comisseq,
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X86Comissge,
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X86Comisslt,
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X86Crc32,
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X86Crc32_16,
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X86Crc32_8,
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X86Cvtdq2pd,
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X86Cvtdq2ps,
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X86Cvtpd2dq,
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X86Cvtpd2ps,
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X86Cvtps2dq,
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X86Cvtps2pd,
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X86Cvtsd2si,
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X86Cvtsd2ss,
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X86Cvtsi2sd,
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X86Cvtsi2si,
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X86Cvtsi2ss,
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X86Cvtss2sd,
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X86Cvtss2si,
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X86Divpd,
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X86Divps,
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X86Divsd,
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X86Divss,
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X86Gf2p8affineqb,
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X86Haddpd,
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X86Haddps,
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X86Insertps,
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X86Maxpd,
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X86Maxps,
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X86Maxsd,
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X86Maxss,
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X86Minpd,
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X86Minps,
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X86Minsd,
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X86Minss,
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X86Movhlps,
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X86Movlhps,
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X86Movss,
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X86Mulpd,
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X86Mulps,
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X86Mulsd,
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X86Mulss,
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X86Mxcsrmb,
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X86Mxcsrub,
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X86Paddb,
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X86Paddd,
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X86Paddq,
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X86Paddw,
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X86Palignr,
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X86Pand,
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X86Pandn,
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X86Pavgb,
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X86Pavgw,
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X86Pblendvb,
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X86Pclmulqdq,
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X86Pcmpeqb,
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X86Pcmpeqd,
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X86Pcmpeqq,
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X86Pcmpeqw,
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X86Pcmpgtb,
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X86Pcmpgtd,
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X86Pcmpgtq,
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X86Pcmpgtw,
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X86Pmaxsb,
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X86Pmaxsd,
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X86Pmaxsw,
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X86Pmaxub,
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X86Pmaxud,
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X86Pmaxuw,
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X86Pminsb,
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X86Pminsd,
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X86Pminsw,
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X86Pminub,
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X86Pminud,
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X86Pminuw,
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X86Pmovsxbw,
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X86Pmovsxdq,
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X86Pmovsxwd,
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X86Pmovzxbw,
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X86Pmovzxdq,
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X86Pmovzxwd,
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X86Pmulld,
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X86Pmullw,
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X86Popcnt,
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X86Por,
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X86Pshufb,
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X86Pshufd,
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X86Pslld,
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X86Pslldq,
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X86Psllq,
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X86Psllw,
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X86Psrad,
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X86Psraw,
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X86Psrld,
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X86Psrlq,
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X86Psrldq,
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X86Psrlw,
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X86Psubb,
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X86Psubd,
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X86Psubq,
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X86Psubw,
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X86Punpckhbw,
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X86Punpckhdq,
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X86Punpckhqdq,
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X86Punpckhwd,
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X86Punpcklbw,
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X86Punpckldq,
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X86Punpcklqdq,
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X86Punpcklwd,
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X86Pxor,
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X86Rcpps,
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X86Rcpss,
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X86Roundpd,
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X86Roundps,
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X86Roundsd,
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X86Roundss,
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X86Rsqrtps,
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X86Rsqrtss,
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X86Sha256Msg1,
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X86Sha256Msg2,
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X86Sha256Rnds2,
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X86Shufpd,
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X86Shufps,
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X86Sqrtpd,
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X86Sqrtps,
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X86Sqrtsd,
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X86Sqrtss,
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X86Subpd,
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X86Subps,
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X86Subsd,
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X86Subss,
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X86Unpckhpd,
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X86Unpckhps,
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X86Unpcklpd,
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X86Unpcklps,
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X86Vcvtph2ps,
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X86Vcvtps2ph,
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X86Vfmadd231ps,
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X86Vfmadd231sd,
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X86Vfmadd231ss,
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X86Vfmsub231sd,
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X86Vfmsub231ss,
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X86Vfnmadd231ps,
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X86Vfnmadd231sd,
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X86Vfnmadd231ss,
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X86Vfnmsub231sd,
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X86Vfnmsub231ss,
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X86Vpternlogd,
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X86Xorpd,
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X86Xorps,
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// Arm64 (FP and Advanced SIMD)
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Arm64AbsS,
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Arm64AbsV,
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Arm64AddhnV,
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Arm64AddpS,
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Arm64AddpV,
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Arm64AddvV,
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Arm64AddS,
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Arm64AddV,
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Arm64AesdV,
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Arm64AeseV,
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Arm64AesimcV,
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Arm64AesmcV,
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Arm64AndV,
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Arm64BicVi,
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Arm64BicV,
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Arm64BifV,
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Arm64BitV,
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Arm64BslV,
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Arm64ClsV,
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Arm64ClzV,
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Arm64CmeqS,
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Arm64CmeqV,
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Arm64CmeqSz,
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Arm64CmeqVz,
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Arm64CmgeS,
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Arm64CmgeV,
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Arm64CmgeSz,
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Arm64CmgeVz,
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Arm64CmgtS,
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Arm64CmgtV,
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Arm64CmgtSz,
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Arm64CmgtVz,
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Arm64CmhiS,
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Arm64CmhiV,
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Arm64CmhsS,
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Arm64CmhsV,
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Arm64CmleSz,
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Arm64CmleVz,
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Arm64CmltSz,
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Arm64CmltVz,
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Arm64CmtstS,
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Arm64CmtstV,
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Arm64CntV,
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Arm64DupSe,
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Arm64DupVe,
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Arm64DupGp,
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Arm64EorV,
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Arm64ExtV,
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Arm64FabdS,
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Arm64FabdV,
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Arm64FabsV,
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Arm64FabsS,
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Arm64FacgeS,
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Arm64FacgeV,
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Arm64FacgtS,
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Arm64FacgtV,
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Arm64FaddpS,
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Arm64FaddpV,
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Arm64FaddV,
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Arm64FaddS,
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Arm64FccmpeS,
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Arm64FccmpS,
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Arm64FcmeqS,
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Arm64FcmeqV,
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Arm64FcmeqSz,
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Arm64FcmeqVz,
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Arm64FcmgeS,
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Arm64FcmgeV,
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Arm64FcmgeSz,
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Arm64FcmgeVz,
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Arm64FcmgtS,
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Arm64FcmgtV,
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Arm64FcmgtSz,
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Arm64FcmgtVz,
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Arm64FcmleSz,
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Arm64FcmleVz,
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Arm64FcmltSz,
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Arm64FcmltVz,
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Arm64FcmpeS,
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Arm64FcmpS,
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Arm64FcselS,
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Arm64FcvtasS,
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Arm64FcvtasV,
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Arm64FcvtasGp,
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Arm64FcvtauS,
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Arm64FcvtauV,
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Arm64FcvtauGp,
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Arm64FcvtlV,
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Arm64FcvtmsS,
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Arm64FcvtmsV,
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Arm64FcvtmsGp,
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Arm64FcvtmuS,
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Arm64FcvtmuV,
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Arm64FcvtmuGp,
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Arm64FcvtnsS,
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Arm64FcvtnsV,
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Arm64FcvtnsGp,
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Arm64FcvtnuS,
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Arm64FcvtnuV,
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Arm64FcvtnuGp,
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Arm64FcvtnV,
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Arm64FcvtpsS,
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Arm64FcvtpsV,
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Arm64FcvtpsGp,
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Arm64FcvtpuS,
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Arm64FcvtpuV,
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Arm64FcvtpuGp,
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Arm64FcvtxnS,
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Arm64FcvtxnV,
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Arm64FcvtzsSFixed,
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Arm64FcvtzsVFixed,
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Arm64FcvtzsS,
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Arm64FcvtzsV,
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Arm64FcvtzsGpFixed,
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Arm64FcvtzsGp,
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Arm64FcvtzuSFixed,
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Arm64FcvtzuVFixed,
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Arm64FcvtzuS,
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Arm64FcvtzuV,
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Arm64FcvtzuGpFixed,
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Arm64FcvtzuGp,
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Arm64FcvtS,
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Arm64FdivV,
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Arm64FdivS,
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Arm64FmaddS,
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Arm64FmaxnmpS,
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Arm64FmaxnmpV,
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Arm64FmaxnmvV,
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Arm64FmaxnmV,
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Arm64FmaxnmS,
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Arm64FmaxpS,
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Arm64FmaxpV,
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Arm64FmaxvV,
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Arm64FmaxV,
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Arm64FmaxS,
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Arm64FminnmpS,
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Arm64FminnmpV,
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Arm64FminnmvV,
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Arm64FminnmV,
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Arm64FminnmS,
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Arm64FminpS,
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Arm64FminpV,
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Arm64FminvV,
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Arm64FminV,
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Arm64FminS,
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Arm64FmlaSe,
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Arm64FmlaVe,
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Arm64FmlaV,
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Arm64FmlsSe,
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Arm64FmlsVe,
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Arm64FmlsV,
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Arm64FmovVi,
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Arm64FmovS,
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Arm64FmovGp,
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Arm64FmovSi,
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Arm64FmsubS,
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Arm64FmulxSe,
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Arm64FmulxVe,
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Arm64FmulxS,
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Arm64FmulxV,
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Arm64FmulSe,
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Arm64FmulVe,
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Arm64FmulV,
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Arm64FmulS,
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Arm64FnegV,
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Arm64FnegS,
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Arm64FnmaddS,
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Arm64FnmsubS,
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Arm64FnmulS,
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Arm64FrecpeS,
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Arm64FrecpeV,
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Arm64FrecpsS,
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Arm64FrecpsV,
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Arm64FrecpxS,
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Arm64FrintaV,
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Arm64FrintaS,
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Arm64FrintiV,
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Arm64FrintiS,
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Arm64FrintmV,
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Arm64FrintmS,
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Arm64FrintnV,
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Arm64FrintnS,
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Arm64FrintpV,
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Arm64FrintpS,
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Arm64FrintxV,
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Arm64FrintxS,
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Arm64FrintzV,
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Arm64FrintzS,
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Arm64FrsqrteS,
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Arm64FrsqrteV,
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Arm64FrsqrtsS,
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Arm64FrsqrtsV,
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Arm64FsqrtV,
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Arm64FsqrtS,
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Arm64FsubV,
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Arm64FsubS,
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Arm64InsVe,
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Arm64InsGp,
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Arm64Ld1rV,
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Arm64Ld1Vms,
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Arm64Ld1Vss,
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Arm64Ld2rV,
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Arm64Ld2Vms,
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Arm64Ld2Vss,
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Arm64Ld3rV,
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Arm64Ld3Vms,
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Arm64Ld3Vss,
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Arm64Ld4rV,
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Arm64Ld4Vms,
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Arm64Ld4Vss,
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Arm64MlaVe,
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Arm64MlaV,
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Arm64MlsVe,
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Arm64MlsV,
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Arm64MoviV,
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Arm64MrsFpsr,
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Arm64MsrFpsr,
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Arm64MulVe,
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Arm64MulV,
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Arm64MvniV,
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Arm64NegS,
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Arm64NegV,
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Arm64NotV,
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Arm64OrnV,
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Arm64OrrVi,
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Arm64OrrV,
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Arm64PmullV,
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Arm64PmulV,
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Arm64RaddhnV,
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Arm64RbitV,
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Arm64Rev16V,
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Arm64Rev32V,
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Arm64Rev64V,
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Arm64RshrnV,
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Arm64RsubhnV,
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Arm64SabalV,
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Arm64SabaV,
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Arm64SabdlV,
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Arm64SabdV,
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Arm64SadalpV,
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Arm64SaddlpV,
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Arm64SaddlvV,
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Arm64SaddlV,
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Arm64SaddwV,
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Arm64ScvtfSFixed,
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Arm64ScvtfVFixed,
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Arm64ScvtfS,
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Arm64ScvtfV,
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Arm64ScvtfGpFixed,
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Arm64ScvtfGp,
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Arm64Sha1cV,
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Arm64Sha1hV,
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Arm64Sha1mV,
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Arm64Sha1pV,
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Arm64Sha1su0V,
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Arm64Sha1su1V,
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Arm64Sha256h2V,
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Arm64Sha256hV,
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Arm64Sha256su0V,
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Arm64Sha256su1V,
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Arm64ShaddV,
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Arm64ShllV,
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Arm64ShlS,
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Arm64ShlV,
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Arm64ShrnV,
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Arm64ShsubV,
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Arm64SliS,
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Arm64SliV,
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Arm64SmaxpV,
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Arm64SmaxvV,
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Arm64SmaxV,
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Arm64SminpV,
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Arm64SminvV,
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Arm64SminV,
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Arm64SmlalVe,
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Arm64SmlalV,
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Arm64SmlslVe,
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Arm64SmlslV,
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Arm64SmovV,
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Arm64SmullVe,
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Arm64SmullV,
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Arm64SqabsS,
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Arm64SqabsV,
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Arm64SqaddS,
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Arm64SqaddV,
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Arm64SqdmlalSe,
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Arm64SqdmlalVe,
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Arm64SqdmlalS,
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Arm64SqdmlalV,
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Arm64SqdmlslSe,
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Arm64SqdmlslVe,
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Arm64SqdmlslS,
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Arm64SqdmlslV,
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Arm64SqdmulhSe,
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Arm64SqdmulhVe,
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Arm64SqdmulhS,
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Arm64SqdmulhV,
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Arm64SqdmullSe,
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Arm64SqdmullVe,
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Arm64SqdmullS,
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Arm64SqdmullV,
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Arm64SqnegS,
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Arm64SqnegV,
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Arm64SqrdmulhSe,
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Arm64SqrdmulhVe,
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Arm64SqrdmulhS,
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Arm64SqrdmulhV,
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Arm64SqrshlS,
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Arm64SqrshlV,
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Arm64SqrshrnS,
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Arm64SqrshrnV,
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Arm64SqrshrunS,
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Arm64SqrshrunV,
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Arm64SqshluS,
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Arm64SqshluV,
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Arm64SqshlSi,
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Arm64SqshlVi,
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Arm64SqshlS,
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Arm64SqshlV,
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Arm64SqshrnS,
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Arm64SqshrnV,
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Arm64SqshrunS,
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Arm64SqshrunV,
|
|
Arm64SqsubS,
|
|
Arm64SqsubV,
|
|
Arm64SqxtnS,
|
|
Arm64SqxtnV,
|
|
Arm64SqxtunS,
|
|
Arm64SqxtunV,
|
|
Arm64SrhaddV,
|
|
Arm64SriS,
|
|
Arm64SriV,
|
|
Arm64SrshlS,
|
|
Arm64SrshlV,
|
|
Arm64SrshrS,
|
|
Arm64SrshrV,
|
|
Arm64SrsraS,
|
|
Arm64SrsraV,
|
|
Arm64SshllV,
|
|
Arm64SshlS,
|
|
Arm64SshlV,
|
|
Arm64SshrS,
|
|
Arm64SshrV,
|
|
Arm64SsraS,
|
|
Arm64SsraV,
|
|
Arm64SsublV,
|
|
Arm64SsubwV,
|
|
Arm64St1Vms,
|
|
Arm64St1Vss,
|
|
Arm64St2Vms,
|
|
Arm64St2Vss,
|
|
Arm64St3Vms,
|
|
Arm64St3Vss,
|
|
Arm64St4Vms,
|
|
Arm64St4Vss,
|
|
Arm64SubhnV,
|
|
Arm64SubS,
|
|
Arm64SubV,
|
|
Arm64SuqaddS,
|
|
Arm64SuqaddV,
|
|
Arm64TblV,
|
|
Arm64TbxV,
|
|
Arm64Trn1V,
|
|
Arm64Trn2V,
|
|
Arm64UabalV,
|
|
Arm64UabaV,
|
|
Arm64UabdlV,
|
|
Arm64UabdV,
|
|
Arm64UadalpV,
|
|
Arm64UaddlpV,
|
|
Arm64UaddlvV,
|
|
Arm64UaddlV,
|
|
Arm64UaddwV,
|
|
Arm64UcvtfSFixed,
|
|
Arm64UcvtfVFixed,
|
|
Arm64UcvtfS,
|
|
Arm64UcvtfV,
|
|
Arm64UcvtfGpFixed,
|
|
Arm64UcvtfGp,
|
|
Arm64UhaddV,
|
|
Arm64UhsubV,
|
|
Arm64UmaxpV,
|
|
Arm64UmaxvV,
|
|
Arm64UmaxV,
|
|
Arm64UminpV,
|
|
Arm64UminvV,
|
|
Arm64UminV,
|
|
Arm64UmlalVe,
|
|
Arm64UmlalV,
|
|
Arm64UmlslVe,
|
|
Arm64UmlslV,
|
|
Arm64UmovV,
|
|
Arm64UmullVe,
|
|
Arm64UmullV,
|
|
Arm64UqaddS,
|
|
Arm64UqaddV,
|
|
Arm64UqrshlS,
|
|
Arm64UqrshlV,
|
|
Arm64UqrshrnS,
|
|
Arm64UqrshrnV,
|
|
Arm64UqshlSi,
|
|
Arm64UqshlVi,
|
|
Arm64UqshlS,
|
|
Arm64UqshlV,
|
|
Arm64UqshrnS,
|
|
Arm64UqshrnV,
|
|
Arm64UqsubS,
|
|
Arm64UqsubV,
|
|
Arm64UqxtnS,
|
|
Arm64UqxtnV,
|
|
Arm64UrecpeV,
|
|
Arm64UrhaddV,
|
|
Arm64UrshlS,
|
|
Arm64UrshlV,
|
|
Arm64UrshrS,
|
|
Arm64UrshrV,
|
|
Arm64UrsqrteV,
|
|
Arm64UrsraS,
|
|
Arm64UrsraV,
|
|
Arm64UshllV,
|
|
Arm64UshlS,
|
|
Arm64UshlV,
|
|
Arm64UshrS,
|
|
Arm64UshrV,
|
|
Arm64UsqaddS,
|
|
Arm64UsqaddV,
|
|
Arm64UsraS,
|
|
Arm64UsraV,
|
|
Arm64UsublV,
|
|
Arm64UsubwV,
|
|
Arm64Uzp1V,
|
|
Arm64Uzp2V,
|
|
Arm64XtnV,
|
|
Arm64Zip1V,
|
|
Arm64Zip2V,
|
|
|
|
Arm64VTypeShift = 13,
|
|
Arm64VTypeMask = 1 << Arm64VTypeShift,
|
|
Arm64V64 = 0 << Arm64VTypeShift,
|
|
Arm64V128 = 1 << Arm64VTypeShift,
|
|
|
|
Arm64VSizeShift = 14,
|
|
Arm64VSizeMask = 3 << Arm64VSizeShift,
|
|
Arm64VFloat = 0 << Arm64VSizeShift,
|
|
Arm64VDouble = 1 << Arm64VSizeShift,
|
|
Arm64VByte = 0 << Arm64VSizeShift,
|
|
Arm64VHWord = 1 << Arm64VSizeShift,
|
|
Arm64VWord = 2 << Arm64VSizeShift,
|
|
Arm64VDWord = 3 << Arm64VSizeShift
|
|
}
|
|
} |