mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-12-18 12:55:54 +01:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
130 lines
3.5 KiB
C#
130 lines
3.5 KiB
C#
using System;
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using System.Diagnostics;
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namespace ARMeilleure.State
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{
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public class ExecutionContext : IExecutionContext
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{
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private const int MinCountForCheck = 40000;
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private NativeContext _nativeContext;
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internal IntPtr NativeContextPtr => _nativeContext.BasePtr;
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private bool _interrupted;
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private static Stopwatch _tickCounter;
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private static double _hostTickFreq;
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public uint CtrEl0 => 0x8444c004;
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public uint DczidEl0 => 0x00000004;
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public ulong CntfrqEl0 { get; set; }
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public ulong CntpctEl0
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{
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get
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{
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double ticks = _tickCounter.ElapsedTicks * _hostTickFreq;
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return (ulong)(ticks * CntfrqEl0);
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}
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}
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public long TpidrEl0 { get; set; }
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public long Tpidr { get; set; }
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public FPCR Fpcr { get; set; }
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public FPSR Fpsr { get; set; }
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public bool IsAarch32 { get; set; }
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internal ExecutionMode ExecutionMode
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{
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get
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{
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if (IsAarch32)
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{
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return GetPstateFlag(PState.TFlag)
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? ExecutionMode.Aarch32Thumb
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: ExecutionMode.Aarch32Arm;
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}
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else
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{
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return ExecutionMode.Aarch64;
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}
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}
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}
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public bool Running { get; set; }
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public event EventHandler<EventArgs> Interrupt;
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public event EventHandler<InstExceptionEventArgs> Break;
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public event EventHandler<InstExceptionEventArgs> SupervisorCall;
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public event EventHandler<InstUndefinedEventArgs> Undefined;
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static ExecutionContext()
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{
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_hostTickFreq = 1.0 / Stopwatch.Frequency;
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_tickCounter = new Stopwatch();
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_tickCounter.Start();
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}
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public ExecutionContext()
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{
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_nativeContext = new NativeContext();
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Running = true;
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_nativeContext.SetCounter(MinCountForCheck);
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}
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public ulong GetX(int index) => _nativeContext.GetX(index);
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public void SetX(int index, ulong value) => _nativeContext.SetX(index, value);
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public V128 GetV(int index) => _nativeContext.GetV(index);
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public void SetV(int index, V128 value) => _nativeContext.SetV(index, value);
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public bool GetPstateFlag(PState flag) => _nativeContext.GetPstateFlag(flag);
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public void SetPstateFlag(PState flag, bool value) => _nativeContext.SetPstateFlag(flag, value);
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internal void CheckInterrupt()
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{
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if (_interrupted)
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{
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_interrupted = false;
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Interrupt?.Invoke(this, EventArgs.Empty);
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}
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_nativeContext.SetCounter(MinCountForCheck);
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}
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public void RequestInterrupt()
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{
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_interrupted = true;
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}
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internal void OnBreak(ulong address, int imm)
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{
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Break?.Invoke(this, new InstExceptionEventArgs(address, imm));
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}
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internal void OnSupervisorCall(ulong address, int imm)
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{
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SupervisorCall?.Invoke(this, new InstExceptionEventArgs(address, imm));
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}
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internal void OnUndefined(ulong address, int opCode)
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{
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Undefined?.Invoke(this, new InstUndefinedEventArgs(address, opCode));
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}
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public void Dispose()
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{
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_nativeContext.Dispose();
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}
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}
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} |