mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-11-24 02:00:11 +01:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
98 lines
3.1 KiB
C#
98 lines
3.1 KiB
C#
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCodeSimdImm : OpCode, IOpCodeSimd
|
|
{
|
|
public int Rd { get; private set; }
|
|
public long Immediate { get; private set; }
|
|
public int Size { get; private set; }
|
|
|
|
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
Rd = opCode & 0x1f;
|
|
|
|
int cMode = (opCode >> 12) & 0xf;
|
|
int op = (opCode >> 29) & 0x1;
|
|
|
|
int modeLow = cMode & 1;
|
|
int modeHigh = cMode >> 1;
|
|
|
|
long imm;
|
|
|
|
imm = ((uint)opCode >> 5) & 0x1f;
|
|
imm |= ((uint)opCode >> 11) & 0xe0;
|
|
|
|
if (modeHigh == 0b111)
|
|
{
|
|
Size = modeLow != 0 ? op : 3;
|
|
|
|
switch (op | (modeLow << 1))
|
|
{
|
|
case 0:
|
|
// 64-bits Immediate.
|
|
// Transform abcd efgh into abcd efgh abcd efgh ...
|
|
imm = (long)((ulong)imm * 0x0101010101010101);
|
|
break;
|
|
|
|
case 1:
|
|
// 64-bits Immediate.
|
|
// Transform abcd efgh into aaaa aaaa bbbb bbbb ...
|
|
imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
|
|
imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
|
|
imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
|
|
|
|
imm = (long)((ulong)imm * 0x8040201008040201);
|
|
imm = (long)((ulong)imm & 0x8080808080808080);
|
|
|
|
imm |= imm >> 4;
|
|
imm |= imm >> 2;
|
|
imm |= imm >> 1;
|
|
break;
|
|
|
|
case 2:
|
|
case 3:
|
|
// Floating point Immediate.
|
|
imm = DecoderHelper.DecodeImm8Float(imm, Size);
|
|
break;
|
|
}
|
|
}
|
|
else if ((modeHigh & 0b110) == 0b100)
|
|
{
|
|
// 16-bits shifted Immediate.
|
|
Size = 1; imm <<= (modeHigh & 1) << 3;
|
|
}
|
|
else if ((modeHigh & 0b100) == 0b000)
|
|
{
|
|
// 32-bits shifted Immediate.
|
|
Size = 2; imm <<= modeHigh << 3;
|
|
}
|
|
else if ((modeHigh & 0b111) == 0b110)
|
|
{
|
|
// 32-bits shifted Immediate (fill with ones).
|
|
Size = 2; imm = ShlOnes(imm, 8 << modeLow);
|
|
}
|
|
else
|
|
{
|
|
// 8 bits without shift.
|
|
Size = 0;
|
|
}
|
|
|
|
Immediate = imm;
|
|
|
|
RegisterSize = ((opCode >> 30) & 1) != 0
|
|
? RegisterSize.Simd128
|
|
: RegisterSize.Simd64;
|
|
}
|
|
|
|
private static long ShlOnes(long value, int shift)
|
|
{
|
|
if (shift != 0)
|
|
{
|
|
return value << shift | (long)(ulong.MaxValue >> (64 - shift));
|
|
}
|
|
else
|
|
{
|
|
return value;
|
|
}
|
|
}
|
|
}
|
|
} |