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36ec1bc6c0
Ryujinx-uplift/ARMeilleure/Translation
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FICTURE7 36ec1bc6c0
Relax block ordering constraints (#1535) 
* Relax block ordering constraints

Before `block.Next` had to follow `block.ListNext`, now it does not.
Instead `CodeGenerator` will now emit the necessary jump instructions
to ensure control flow.

This makes control flow and block order modifications easier. It also
eliminates some simple cases of redundant branches.

* Set PPTC version
2020-09-12 12:32:53 -03:00
..
PTC Relax block ordering constraints (#1535) 2020-09-12 12:32:53 -03:00
ArmEmitterContext.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
Compiler.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
CompilerContext.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
CompilerOptions.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
ControlFlowGraph.cs Relax block ordering constraints (#1535) 2020-09-12 12:32:53 -03:00
DelegateHelper.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
DelegateInfo.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
Delegates.cs CPU: This PR fixes Fpscr, among other things. (#1433) 2020-08-08 17:18:51 +02:00
DirectCallStubs.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
Dominance.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
EmitterContext.cs Relax block ordering constraints (#1535) 2020-09-12 12:32:53 -03:00
GuestFunction.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
JitCache.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
JitCacheEntry.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
JitUnwindWindows.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
JumpTable.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
RegisterToLocal.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
RegisterUsage.cs Relax block ordering constraints (#1535) 2020-09-12 12:32:53 -03:00
RejitRequest.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
SsaConstruction.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00
SsaDeconstruction.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
TranslatedFunction.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
Translator.cs Relax block ordering constraints (#1535) 2020-09-12 12:32:53 -03:00