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https://github.com/GreemDev/Ryujinx.git
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c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
37 lines
1.1 KiB
C#
37 lines
1.1 KiB
C#
using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32Mem : OpCode32, IOpCode32Mem
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{
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public int Rt { get; private set; }
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public int Rn { get; private set; }
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public int Imm { get; protected set; }
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public bool Index { get; private set; }
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public bool Add { get; private set; }
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public bool WBack { get; private set; }
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public bool Unprivileged { get; private set; }
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public bool IsLoad { get; private set; }
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public OpCode32Mem(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rt = (opCode >> 12) & 0xf;
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Rn = (opCode >> 16) & 0xf;
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bool isLoad = (opCode & (1 << 20)) != 0;
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bool w = (opCode & (1 << 21)) != 0;
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bool u = (opCode & (1 << 23)) != 0;
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bool p = (opCode & (1 << 24)) != 0;
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Index = p;
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Add = u;
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WBack = !p || w;
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Unprivileged = !p && w;
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IsLoad = isLoad || inst.Emitter == InstEmit32.Ldrd;
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}
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}
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} |