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Ryujinx-uplift/Ryujinx/Cpu/Decoder
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gdkchan 6a3aa6cd88 Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
2018-02-09 00:26:20 -03:00
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ABlock.cs
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2018-02-04 20:08:20 -03:00
ACond.cs
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ADataOp.cs
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ADecoder.cs
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ADecoderHelper.cs
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AIntType.cs
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AOpCode.cs
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AOpCodeAdr.cs
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AOpCodeAlu.cs
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AOpCodeAluImm.cs
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AOpCodeAluRs.cs
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AOpCodeAluRx.cs
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AOpCodeBfm.cs
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AOpCodeBImm.cs
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AOpCodeBImmAl.cs
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AOpCodeBImmCmp.cs
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AOpCodeBImmCond.cs
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AOpCodeBImmTest.cs
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AOpCodeBReg.cs
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AOpCodeCcmp.cs
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AOpCodeCcmpImm.cs
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AOpCodeCcmpReg.cs
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AOpCodeCsel.cs
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AOpCodeException.cs
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AOpCodeMem.cs
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AOpCodeMemEx.cs
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AOpCodeMemImm.cs
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AOpCodeMemLit.cs
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AOpCodeMemPair.cs
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AOpCodeMemReg.cs
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AOpCodeMov.cs
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AOpCodeMul.cs
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AOpCodeSimd.cs
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AOpCodeSimdCvt.cs
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AOpCodeSimdFcond.cs
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AOpCodeSimdFmov.cs
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AOpCodeSimdImm.cs
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AOpCodeSimdIns.cs
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AOpCodeSimdMemImm.cs
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AOpCodeSimdMemLit.cs
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2018-02-04 20:08:20 -03:00
AOpCodeSimdMemMs.cs
Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
2018-02-09 00:26:20 -03:00
AOpCodeSimdMemPair.cs
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2018-02-04 20:08:20 -03:00
AOpCodeSimdMemReg.cs
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2018-02-04 20:08:20 -03:00
AOpCodeSimdMemSs.cs
Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
2018-02-09 00:26:20 -03:00
AOpCodeSimdReg.cs
Add FMADD and FMSUB instructions
2018-02-07 20:07:16 -03:00
AOpCodeSimdRegElem.cs
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AOpCodeSimdShImm.cs
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AOpCodeSimdTbl.cs
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AOpCodeSystem.cs
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AShiftType.cs
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IAOpCode.cs
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IAOpCodeAlu.cs
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2018-02-04 20:08:20 -03:00
IAOpCodeAluImm.cs
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2018-02-04 20:08:20 -03:00
IAOpCodeAluRs.cs
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2018-02-04 20:08:20 -03:00
IAOpCodeAluRx.cs
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IAOpCodeCond.cs
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2018-02-04 20:08:20 -03:00
IAOpCodeLit.cs
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2018-02-04 20:08:20 -03:00
IAOpCodeSimd.cs
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2018-02-04 20:08:20 -03:00