mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-11-17 23:07:08 +01:00
884b4e5fd3
* Initial non 2D textures support - Shaders still need to be changed - Some types aren't yet implemented * Start implementing texture instructions suffixes Fix wrong texture type with cube and TEXS Also support array textures in TEX and TEX.B Clean up TEX and TEXS coords managment Fix TEXS.LL with non-2d textures Implement TEX.AOFFI Get the right arguments for TEX, TEXS and TLDS Also, store suffix operands in appropriate values to support multiple suffix combinaisons * Support depth in read/writeTexture Also support WrapR and detect mipmap * Proper cube map textures support + fix TEXS.LZ * Implement depth compare * some code clean up * Implement CubeMap textures in OGLTexture.Create * Implement TLD4 and TLD4S * Add Texture 1D support * updates comments * fix some code style issues * Fix some nits + rename some things to be less confusing * Remove GetSuffix local functions * AOFFI => AOffI * TextureType => GalTextureTarget * finish renaming TextureType to TextureTarget * Disable LL, LZ and LB support in the decompiler This needs more work at the GL level (GLSL implementation should be right) * Revert "Disable LL, LZ and LB support in the decompiler" This reverts commit 64536c3d9f673645faff3152838d1413c3203395. * Fix TEXS ARRAY_2D index * ImageFormat depth should be 1 for all image format * Fix shader build issues with sampler1DShadow and texture * Fix DC & AOFFI combinaison with TEX/TEXS * Support AOFFI with TLD4 and TLD4S * Fix shader compilation error for TLD4.AOFFI with no DC * Fix binding isuses on the 2d copy engine TODO: support 2d array copy * Support 2D array copy operation in the 2D engine This make every copy right in the GPU side. Thie CPU copy probably needs to be updated * Implement GetGpuSize + fix somes issues with 2d engine copies TODO: mipmap level in it * Don't throw an exception in the layer handling * Fix because of rebase * Reject 2d layers of non textures in 2d copy engine * Add 3D textures and mipmap support on BlockLinearSwizzle * Fix naming on new BitUtils methods * gpu cache: Make sure to invalidate textures that doesn't have the same target * Add the concept of layer count for array instead of using depth Also cleanup GetGpuSize as Swizzle can compute the size with mipmap * Support multi layer with mip map in ReadTexture * Add more check for cache invalidation & remove cubemap and cubemap array code for now Also fix compressed 2d array * Fix texelFetchOffset shader build error * Start looking into cube map again Also add some way to log write in register in engines * fix write register log levles * Remove debug logs in WriteRegister * Disable AOFFI support on non NVIDIA drivers * Fix code align
313 lines
9.0 KiB
C#
313 lines
9.0 KiB
C#
using System;
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namespace Ryujinx.Graphics.Gal.Shader
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{
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static partial class ShaderDecode
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{
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private static int Read(this long OpCode, int Position, int Mask)
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{
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return (int)(OpCode >> Position) & Mask;
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}
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private static bool Read(this long OpCode, int Position)
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{
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return ((OpCode >> Position) & 1) != 0;
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}
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private static int Branch(this long OpCode)
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{
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return ((int)(OpCode >> 20) << 8) >> 8;
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}
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private static bool HasArray(this long OpCode)
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{
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return OpCode.Read(0x1c);
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}
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private static ShaderIrOperAbuf[] Abuf20(this long OpCode)
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{
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int Abuf = OpCode.Read(20, 0x3ff);
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int Size = OpCode.Read(47, 3);
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ShaderIrOperGpr Vertex = OpCode.Gpr39();
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ShaderIrOperAbuf[] Opers = new ShaderIrOperAbuf[Size + 1];
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for (int Index = 0; Index <= Size; Index++)
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{
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Opers[Index] = new ShaderIrOperAbuf(Abuf + Index * 4, Vertex);
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}
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return Opers;
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}
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private static ShaderIrOperAbuf Abuf28(this long OpCode)
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{
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int Abuf = OpCode.Read(28, 0x3ff);
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return new ShaderIrOperAbuf(Abuf, OpCode.Gpr39());
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}
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private static ShaderIrOperCbuf Cbuf34(this long OpCode)
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{
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return new ShaderIrOperCbuf(
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OpCode.Read(34, 0x1f),
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OpCode.Read(20, 0x3fff));
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}
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private static ShaderIrOperGpr Gpr8(this long OpCode)
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{
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return new ShaderIrOperGpr(OpCode.Read(8, 0xff));
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}
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private static ShaderIrOperGpr Gpr20(this long OpCode)
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{
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return new ShaderIrOperGpr(OpCode.Read(20, 0xff));
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}
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private static ShaderIrOperGpr Gpr39(this long OpCode)
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{
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return new ShaderIrOperGpr(OpCode.Read(39, 0xff));
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}
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private static ShaderIrOperGpr Gpr0(this long OpCode)
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{
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return new ShaderIrOperGpr(OpCode.Read(0, 0xff));
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}
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private static ShaderIrOperGpr Gpr28(this long OpCode)
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{
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return new ShaderIrOperGpr(OpCode.Read(28, 0xff));
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}
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private static ShaderIrOperGpr[] GprHalfVec8(this long OpCode)
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{
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return GetGprHalfVec2(OpCode.Read(8, 0xff), OpCode.Read(47, 3));
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}
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private static ShaderIrOperGpr[] GprHalfVec20(this long OpCode)
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{
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return GetGprHalfVec2(OpCode.Read(20, 0xff), OpCode.Read(28, 3));
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}
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private static ShaderIrOperGpr[] GetGprHalfVec2(int Gpr, int Mask)
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{
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if (Mask == 1)
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{
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//This value is used for FP32, the whole 32-bits register
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//is used as each element on the vector.
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return new ShaderIrOperGpr[]
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{
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new ShaderIrOperGpr(Gpr),
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new ShaderIrOperGpr(Gpr)
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};
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}
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ShaderIrOperGpr Low = new ShaderIrOperGpr(Gpr, 0);
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ShaderIrOperGpr High = new ShaderIrOperGpr(Gpr, 1);
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return new ShaderIrOperGpr[]
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{
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(Mask & 1) != 0 ? High : Low,
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(Mask & 2) != 0 ? High : Low
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};
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}
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private static ShaderIrOperGpr GprHalf0(this long OpCode, int HalfPart)
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{
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return new ShaderIrOperGpr(OpCode.Read(0, 0xff), HalfPart);
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}
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private static ShaderIrOperGpr GprHalf28(this long OpCode, int HalfPart)
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{
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return new ShaderIrOperGpr(OpCode.Read(28, 0xff), HalfPart);
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}
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private static ShaderIrOperImm Imm5_39(this long OpCode)
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{
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return new ShaderIrOperImm(OpCode.Read(39, 0x1f));
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}
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private static ShaderIrOperImm Imm13_36(this long OpCode)
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{
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return new ShaderIrOperImm(OpCode.Read(36, 0x1fff));
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}
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private static ShaderIrOperImm Imm32_20(this long OpCode)
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{
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return new ShaderIrOperImm((int)(OpCode >> 20));
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}
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private static ShaderIrOperImmf Immf32_20(this long OpCode)
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{
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return new ShaderIrOperImmf(BitConverter.Int32BitsToSingle((int)(OpCode >> 20)));
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}
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private static ShaderIrOperImm ImmU16_20(this long OpCode)
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{
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return new ShaderIrOperImm(OpCode.Read(20, 0xffff));
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}
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private static ShaderIrOperImm Imm19_20(this long OpCode)
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{
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int Value = OpCode.Read(20, 0x7ffff);
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bool Neg = OpCode.Read(56);
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if (Neg)
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{
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Value = -Value;
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}
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return new ShaderIrOperImm(Value);
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}
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private static ShaderIrOperImmf Immf19_20(this long OpCode)
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{
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uint Imm = (uint)(OpCode >> 20) & 0x7ffff;
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bool Neg = OpCode.Read(56);
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Imm <<= 12;
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if (Neg)
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{
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Imm |= 0x80000000;
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}
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float Value = BitConverter.Int32BitsToSingle((int)Imm);
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return new ShaderIrOperImmf(Value);
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}
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private static ShaderIrOperPred Pred0(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(0, 7));
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}
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private static ShaderIrOperPred Pred3(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(3, 7));
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}
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private static ShaderIrOperPred Pred12(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(12, 7));
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}
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private static ShaderIrOperPred Pred29(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(29, 7));
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}
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private static ShaderIrNode Pred39N(this long OpCode)
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{
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ShaderIrNode Node = OpCode.Pred39();
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if (OpCode.Read(42))
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{
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Node = new ShaderIrOp(ShaderIrInst.Bnot, Node);
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}
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return Node;
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}
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private static ShaderIrOperPred Pred39(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(39, 7));
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}
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private static ShaderIrOperPred Pred48(this long OpCode)
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{
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return new ShaderIrOperPred(OpCode.Read(48, 7));
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}
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private static ShaderIrInst Cmp(this long OpCode)
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{
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switch (OpCode.Read(49, 7))
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{
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case 1: return ShaderIrInst.Clt;
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case 2: return ShaderIrInst.Ceq;
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case 3: return ShaderIrInst.Cle;
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case 4: return ShaderIrInst.Cgt;
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case 5: return ShaderIrInst.Cne;
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case 6: return ShaderIrInst.Cge;
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}
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throw new ArgumentException(nameof(OpCode));
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}
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private static ShaderIrInst CmpF(this long OpCode)
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{
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switch (OpCode.Read(48, 0xf))
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{
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case 0x1: return ShaderIrInst.Fclt;
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case 0x2: return ShaderIrInst.Fceq;
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case 0x3: return ShaderIrInst.Fcle;
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case 0x4: return ShaderIrInst.Fcgt;
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case 0x5: return ShaderIrInst.Fcne;
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case 0x6: return ShaderIrInst.Fcge;
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case 0x7: return ShaderIrInst.Fcnum;
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case 0x8: return ShaderIrInst.Fcnan;
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case 0x9: return ShaderIrInst.Fcltu;
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case 0xa: return ShaderIrInst.Fcequ;
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case 0xb: return ShaderIrInst.Fcleu;
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case 0xc: return ShaderIrInst.Fcgtu;
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case 0xd: return ShaderIrInst.Fcneu;
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case 0xe: return ShaderIrInst.Fcgeu;
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}
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throw new ArgumentException(nameof(OpCode));
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}
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private static ShaderIrInst BLop45(this long OpCode)
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{
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switch (OpCode.Read(45, 3))
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{
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case 0: return ShaderIrInst.Band;
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case 1: return ShaderIrInst.Bor;
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case 2: return ShaderIrInst.Bxor;
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}
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throw new ArgumentException(nameof(OpCode));
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}
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private static ShaderIrInst BLop24(this long OpCode)
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{
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switch (OpCode.Read(24, 3))
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{
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case 0: return ShaderIrInst.Band;
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case 1: return ShaderIrInst.Bor;
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case 2: return ShaderIrInst.Bxor;
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}
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throw new ArgumentException(nameof(OpCode));
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}
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private static ShaderIrNode PredNode(this long OpCode, ShaderIrNode Node)
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{
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ShaderIrOperPred Pred = OpCode.PredNode();
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if (Pred.Index != ShaderIrOperPred.UnusedIndex)
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{
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bool Inv = OpCode.Read(19);
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Node = new ShaderIrCond(Pred, Node, Inv);
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}
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return Node;
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}
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private static ShaderIrOperPred PredNode(this long OpCode)
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{
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int Pred = OpCode.Read(16, 0xf);
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if (Pred != 0xf)
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{
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Pred &= 7;
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}
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return new ShaderIrOperPred(Pred);
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}
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}
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} |