mirror of
https://github.com/GreemDev/Ryujinx.git
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22b2cb39af
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
68 lines
2.1 KiB
C#
68 lines
2.1 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Sdiv(ArmEmitterContext context) => EmitDiv(context, unsigned: false);
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public static void Udiv(ArmEmitterContext context) => EmitDiv(context, unsigned: true);
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private static void EmitDiv(ArmEmitterContext context, bool unsigned)
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{
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OpCodeAluBinary op = (OpCodeAluBinary)context.CurrOp;
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// If Rm == 0, Rd = 0 (division by zero).
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Operand n = GetIntOrZR(context, op.Rn);
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Operand m = GetIntOrZR(context, op.Rm);
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Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0));
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Operand lblBadDiv = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBadDiv, divisorIsZero);
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if (!unsigned)
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{
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// If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
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bool is32Bits = op.RegisterSize == RegisterSize.Int32;
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Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue);
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Operand minus1 = is32Bits ? Const(-1) : Const(-1L);
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Operand nIsIntMin = context.ICompareEqual(n, intMin);
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Operand mIsMinus1 = context.ICompareEqual(m, minus1);
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Operand lblGoodDiv = Label();
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context.BranchIfFalse(lblGoodDiv, context.BitwiseAnd(nIsIntMin, mIsMinus1));
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SetAluDOrZR(context, intMin);
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context.Branch(lblEnd);
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context.MarkLabel(lblGoodDiv);
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}
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Operand d = unsigned
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? context.DivideUI(n, m)
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: context.Divide (n, m);
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SetAluDOrZR(context, d);
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context.Branch(lblEnd);
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context.MarkLabel(lblBadDiv);
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SetAluDOrZR(context, Const(op.GetOperandType(), 0));
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context.MarkLabel(lblEnd);
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}
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}
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}
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