merry bd9ac0fdaa T32: Implement B, B.cond, BL, BLX (#3155) ... * Decoders: Make IsThumb a function of OpCode32 * OpCode32: Fix GetPc * T32: Implement B, B.cond, BL, BLX * rm usings		2022-03-04 23:05:08 +01:00
..
CpuTest32.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
CpuTest.cs	Add multi-level function table (#2228)	2021-05-29 18:06:28 -03:00
CpuTestAlu32.cs	ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)	2022-02-08 10:46:42 +01:00
CpuTestAlu.cs	Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)	2019-06-12 09:03:31 -03:00
CpuTestAluBinary32.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
CpuTestAluBinary.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
CpuTestAluImm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestAluRs32.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
CpuTestAluRs.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestAluRx.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestBf32.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00
CpuTestBfm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCcmpImm.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCcmpReg.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestCsel.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestMisc32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestMisc.cs	Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)	2020-07-13 21:08:47 +10:00
CpuTestMov.cs	Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)	2019-06-12 09:03:31 -03:00
CpuTestMul32.cs	Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)	2020-03-01 07:51:55 +11:00
CpuTestMul.cs	Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)	2018-11-01 01:22:09 -03:00
CpuTestSimd32.cs	Implement VCNT instruction (#1963)	2021-02-22 16:26:13 +01:00
CpuTestSimd.cs	CPU - Implement FCVTMS (Vector) (#2937)	2022-01-04 16:45:28 -03:00
CpuTestSimdCrypto32.cs	Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)	2020-03-14 10:29:58 +11:00
CpuTestSimdCrypto.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdCvt32.cs	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
CpuTestSimdCvt.cs	Implement FCVTNS (Scalar GP) (#2953)	2022-01-19 22:21:44 -03:00
CpuTestSimdExt.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdFcond.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdFmov.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdImm.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdIns.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdLogical32.cs	Implement VORN (register) Arm32 instruction (#2396)	2021-06-23 23:21:23 +02:00
CpuTestSimdMemory32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestSimdMov32.cs	Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)	2020-06-24 10:43:44 +10:00
CpuTestSimdReg32.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
CpuTestSimdReg.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
CpuTestSimdRegElem32.cs	Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)	2020-03-11 11:49:27 +11:00
CpuTestSimdRegElem.cs	Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)	2021-03-25 23:33:32 +01:00
CpuTestSimdRegElemF.cs	Add a new JIT compiler for CPU code (#693)	2019-08-08 21:56:22 +03:00
CpuTestSimdShImm32.cs	CPU: This PR fixes Fpscr, among other things. (#1433)	2020-08-08 17:18:51 +02:00
CpuTestSimdShImm.cs	CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)	2020-08-31 20:48:21 -03:00
CpuTestSimdTbl.cs	Add Tbx Inst. (fast & slow paths), with Tests. (#782)	2019-10-04 11:43:20 -03:00
CpuTestSystem.cs	Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)	2019-11-14 13:08:07 +11:00
CpuTestT32Alu.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
CpuTestT32Flow.cs	T32: Implement B, B.cond, BL, BLX (#3155)	2022-03-04 23:05:08 +01:00
CpuTestThumb.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
PrecomputedThumbTestCase.cs	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00