mirror of
https://github.com/GreemDev/Ryujinx.git
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10c74182ba
* Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
191 lines
7.8 KiB
C#
191 lines
7.8 KiB
C#
#define SimdRegElem
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdRegElem")]
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public sealed class CpuTestSimdRegElem : CpuTest
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{
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#if SimdRegElem
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
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{
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return new uint[]
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{
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0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
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0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
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0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
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};
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}
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private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
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{
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return new uint[]
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{
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0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
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0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
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0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
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};
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}
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private static uint[] _SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_()
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{
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return new uint[]
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{
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0x0F402000u, // SMLAL V0.4S, V0.4H, V0.H[0]
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0x0F406000u, // SMLSL V0.4S, V0.4H, V0.H[0]
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0x0F40A000u, // SMULL V0.4S, V0.4H, V0.H[0]
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0x2F402000u, // UMLAL V0.4S, V0.4H, V0.H[0]
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0x2F406000u, // UMLSL V0.4S, V0.4H, V0.H[0]
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0x2F40A000u // UMULL V0.4S, V0.4H, V0.H[0]
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};
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}
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private static uint[] _SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_()
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{
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return new uint[]
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{
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0x0F802000u, // SMLAL V0.2D, V0.2S, V0.S[0]
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0x0F806000u, // SMLSL V0.2D, V0.2S, V0.S[0]
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0x0F80A000u, // SMULL V0.2D, V0.2S, V0.S[0]
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0x2F802000u, // UMLAL V0.2D, V0.2S, V0.S[0]
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0x2F806000u, // UMLSL V0.2D, V0.2S, V0.S[0]
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0x2F80A000u // UMULL V0.2D, V0.2S, V0.S[0]
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};
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntIndex = 2;
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint h = (index >> 2) & 1;
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uint l = (index >> 1) & 1;
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uint m = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (m << 20) | (h << 11);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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Vector128<float> v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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Vector128<float> v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
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{
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uint h = (index >> 2) & 1;
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uint l = (index >> 1) & 1;
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uint m = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (m << 20) | (h << 11);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
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Vector128<float> v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
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Vector128<float> v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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