mirror of
https://github.com/GreemDev/Ryujinx.git
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e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
123 lines
3.2 KiB
C#
123 lines
3.2 KiB
C#
using ChocolArm64.State;
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using System;
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using System.Collections.Generic;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics;
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namespace ChocolArm64.Translation
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{
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class ILMethodBuilder
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{
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private const int RegsCount = 32;
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private const int RegsMask = RegsCount - 1;
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public RegisterUsage RegUsage { get; private set; }
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public ILGenerator Generator { get; private set; }
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private Dictionary<Register, int> _locals;
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private ILBlock[] _ilBlocks;
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private string _subName;
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public bool IsAarch64 { get; }
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public bool IsSubComplete { get; }
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private int _localsCount;
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public ILMethodBuilder(
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ILBlock[] ilBlocks,
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string subName,
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bool isAarch64,
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bool isSubComplete = false)
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{
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_ilBlocks = ilBlocks;
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_subName = subName;
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IsAarch64 = isAarch64;
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IsSubComplete = isSubComplete;
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}
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public TranslatedSub GetSubroutine(TranslationTier tier, bool isWorthOptimizing)
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{
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RegUsage = new RegisterUsage();
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RegUsage.BuildUses(_ilBlocks[0]);
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DynamicMethod method = new DynamicMethod(_subName, typeof(long), TranslatedSub.FixedArgTypes);
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long intNiRegsMask = RegUsage.GetIntNotInputs(_ilBlocks[0]);
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long vecNiRegsMask = RegUsage.GetVecNotInputs(_ilBlocks[0]);
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TranslatedSub subroutine = new TranslatedSub(
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method,
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intNiRegsMask,
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vecNiRegsMask,
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tier,
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isWorthOptimizing);
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_locals = new Dictionary<Register, int>();
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_localsCount = 0;
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Generator = method.GetILGenerator();
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foreach (ILBlock ilBlock in _ilBlocks)
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{
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ilBlock.Emit(this);
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}
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subroutine.PrepareMethod();
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return subroutine;
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}
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public int GetLocalIndex(Register reg)
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{
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if (!_locals.TryGetValue(reg, out int index))
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{
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Generator.DeclareLocal(GetFieldType(reg.Type));
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index = _localsCount++;
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_locals.Add(reg, index);
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}
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return index;
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}
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private static Type GetFieldType(RegisterType regType)
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{
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switch (regType)
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{
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case RegisterType.Flag: return typeof(bool);
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case RegisterType.Int: return typeof(ulong);
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case RegisterType.Vector: return typeof(Vector128<float>);
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}
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throw new ArgumentException(nameof(regType));
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}
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public static Register GetRegFromBit(int bit, RegisterType baseType)
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{
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if (bit < RegsCount)
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{
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return new Register(bit, baseType);
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}
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else if (baseType == RegisterType.Int)
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{
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return new Register(bit & RegsMask, RegisterType.Flag);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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public static bool IsRegIndex(int index)
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{
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return (uint)index < RegsCount;
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}
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}
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} |