mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-11-16 14:33:17 +01:00
1bef70c068
* Update CountLeadingZeros(). * Remove obsolete Tests. * Follow-up. * Follow-up. * Follow-up. * Add Mla_V, Mls_V & Mul_V Tests. * Update PackageReferences. * Remove EmitLd/Stvectmp2(). * Remove Dup. Nits. * Remove EmitLd/Stvectmp2() & Dup; nits. * Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn(). * Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits. * Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt.. Remove Tmp stuff; remove Dup. Nits. * Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt.. Remove EmitLd/Stvectmp2(), remove Dup. Nits. * Nits. * Nits. * Nit. * Add "Part" opt.. Nit. * Nit. * Nit. * Add Cmhi_V & Cmhs_V Sse opt..
735 lines
22 KiB
C#
735 lines
22 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Fcvt_S(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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if (op.Size == 1 && op.Opc == 0)
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{
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//Double -> Single.
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Type[] typesCvt = new Type[] { typeof(Vector128<float>), typeof(Vector128<double>) };
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleZero));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertScalarToVector128Single), typesCvt));
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context.EmitStvec(op.Rd);
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}
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else if (op.Size == 0 && op.Opc == 1)
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{
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//Single -> Double.
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Type[] typesCvt = new Type[] { typeof(Vector128<double>), typeof(Vector128<float>) };
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorDoubleZero));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertScalarToVector128Double), typesCvt));
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context.EmitStvec(op.Rd);
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}
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else
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{
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//Invalid encoding.
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throw new InvalidOperationException();
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}
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}
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else
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{
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EmitVectorExtractF(context, op.Rn, 0, op.Size);
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EmitFloatCast(context, op.Opc);
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EmitScalarSetF(context, op.Rd, op.Opc);
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}
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}
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public static void Fcvtas_Gp(ILEmitterCtx context)
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{
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EmitFcvt_s_Gp(context, () => EmitRoundMathCall(context, MidpointRounding.AwayFromZero));
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}
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public static void Fcvtau_Gp(ILEmitterCtx context)
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{
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EmitFcvt_u_Gp(context, () => EmitRoundMathCall(context, MidpointRounding.AwayFromZero));
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}
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public static void Fcvtl_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (Optimizations.UseSse2 && sizeF == 1)
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{
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Type[] typesCvt = new Type[] { typeof(Vector128<float>) };
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context.EmitLdvec(op.Rn);
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.MoveHighToLow)));
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}
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertToVector128Double), typesCvt));
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context.EmitStvec(op.Rd);
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}
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else
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{
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int elems = 4 >> sizeF;
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
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for (int index = 0; index < elems; index++)
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{
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if (sizeF == 0)
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{
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EmitVectorExtractZx(context, op.Rn, part + index, 1);
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context.Emit(OpCodes.Conv_U2);
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitCall(typeof(SoftFloat16_32), nameof(SoftFloat16_32.FPConvert));
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}
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else /* if (sizeF == 1) */
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{
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EmitVectorExtractF(context, op.Rn, part + index, 0);
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context.Emit(OpCodes.Conv_R8);
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}
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EmitVectorInsertTmpF(context, index, sizeF);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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}
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}
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public static void Fcvtms_Gp(ILEmitterCtx context)
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{
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EmitFcvt_s_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Floor)));
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}
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public static void Fcvtmu_Gp(ILEmitterCtx context)
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{
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EmitFcvt_u_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Floor)));
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}
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public static void Fcvtn_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (Optimizations.UseSse2 && sizeF == 1)
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{
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Type[] typesCvt = new Type[] { typeof(Vector128<double>) };
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string nameMov = op.RegisterSize == RegisterSize.Simd128
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? nameof(Sse.MoveLowToHigh)
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: nameof(Sse.MoveHighToLow);
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context.EmitLdvec(op.Rd);
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleZero));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.MoveLowToHigh)));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertToVector128Single), typesCvt));
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context.Emit(OpCodes.Dup);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.MoveLowToHigh)));
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context.EmitCall(typeof(Sse).GetMethod(nameMov));
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context.EmitStvec(op.Rd);
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}
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else
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{
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int elems = 4 >> sizeF;
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
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if (part != 0)
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{
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context.EmitLdvec(op.Rd);
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context.EmitStvectmp();
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}
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractF(context, op.Rn, index, sizeF);
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if (sizeF == 0)
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{
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitCall(typeof(SoftFloat32_16), nameof(SoftFloat32_16.FPConvert));
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context.Emit(OpCodes.Conv_U8);
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EmitVectorInsertTmp(context, part + index, 1);
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}
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else /* if (sizeF == 1) */
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{
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context.Emit(OpCodes.Conv_R4);
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EmitVectorInsertTmpF(context, part + index, 0);
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}
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (part == 0)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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public static void Fcvtns_S(ILEmitterCtx context)
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{
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EmitFcvtn(context, signed: true, scalar: true);
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}
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public static void Fcvtns_V(ILEmitterCtx context)
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{
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EmitFcvtn(context, signed: true, scalar: false);
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}
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public static void Fcvtnu_S(ILEmitterCtx context)
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{
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EmitFcvtn(context, signed: false, scalar: true);
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}
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public static void Fcvtnu_V(ILEmitterCtx context)
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{
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EmitFcvtn(context, signed: false, scalar: false);
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}
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public static void Fcvtps_Gp(ILEmitterCtx context)
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{
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EmitFcvt_s_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Ceiling)));
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}
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public static void Fcvtpu_Gp(ILEmitterCtx context)
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{
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EmitFcvt_u_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Ceiling)));
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}
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public static void Fcvtzs_Gp(ILEmitterCtx context)
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{
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EmitFcvt_s_Gp(context, () => { });
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}
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public static void Fcvtzs_Gp_Fixed(ILEmitterCtx context)
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{
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EmitFcvtzs_Gp_Fixed(context);
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}
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public static void Fcvtzs_S(ILEmitterCtx context)
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{
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EmitFcvtz(context, signed: true, scalar: true);
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}
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public static void Fcvtzs_V(ILEmitterCtx context)
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{
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EmitFcvtz(context, signed: true, scalar: false);
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}
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public static void Fcvtzu_Gp(ILEmitterCtx context)
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{
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EmitFcvt_u_Gp(context, () => { });
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}
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public static void Fcvtzu_Gp_Fixed(ILEmitterCtx context)
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{
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EmitFcvtzu_Gp_Fixed(context);
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}
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public static void Fcvtzu_S(ILEmitterCtx context)
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{
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EmitFcvtz(context, signed: false, scalar: true);
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}
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public static void Fcvtzu_V(ILEmitterCtx context)
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{
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EmitFcvtz(context, signed: false, scalar: false);
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}
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public static void Scvtf_Gp(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U4);
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}
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EmitFloatCast(context, op.Size);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Scvtf_Gp_Fixed(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_I4);
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}
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EmitFloatCast(context, op.Size);
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EmitI2fFBitsMul(context, op.Size, op.FBits);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Scvtf_S(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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EmitVectorExtractSx(context, op.Rn, 0, op.Size + 2);
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EmitFloatCast(context, op.Size);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Scvtf_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (Optimizations.UseSse2 && sizeF == 0)
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{
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Type[] typesCvt = new Type[] { typeof(Vector128<int>) };
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertToVector128Single), typesCvt));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorCvtf(context, signed: true);
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}
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}
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public static void Ucvtf_Gp(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U4);
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}
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context.Emit(OpCodes.Conv_R_Un);
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EmitFloatCast(context, op.Size);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Ucvtf_Gp_Fixed(ILEmitterCtx context)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U4);
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}
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context.Emit(OpCodes.Conv_R_Un);
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EmitFloatCast(context, op.Size);
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EmitI2fFBitsMul(context, op.Size, op.FBits);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Ucvtf_S(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2);
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context.Emit(OpCodes.Conv_R_Un);
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EmitFloatCast(context, op.Size);
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EmitScalarSetF(context, op.Rd, op.Size);
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}
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public static void Ucvtf_V(ILEmitterCtx context)
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{
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EmitVectorCvtf(context, signed: false);
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}
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private static void EmitFcvtn(ILEmitterCtx context, bool signed, bool scalar)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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int sizeI = sizeF + 2;
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int bytes = op.GetBitsCount() >> 3;
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int elems = !scalar ? bytes >> sizeI : 1;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractF(context, op.Rn, index, sizeF);
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EmitRoundMathCall(context, MidpointRounding.ToEven);
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if (sizeF == 0)
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{
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VectorHelper.EmitCall(context, signed
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? nameof(VectorHelper.SatF32ToS32)
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: nameof(VectorHelper.SatF32ToU32));
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context.Emit(OpCodes.Conv_U8);
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}
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else /* if (sizeF == 1) */
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{
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VectorHelper.EmitCall(context, signed
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? nameof(VectorHelper.SatF64ToS64)
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: nameof(VectorHelper.SatF64ToU64));
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}
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if (scalar)
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{
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EmitVectorZeroAll(context, op.Rd);
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}
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EmitVectorInsert(context, op.Rd, index, sizeI);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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private static void EmitFcvtz(ILEmitterCtx context, bool signed, bool scalar)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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int sizeI = sizeF + 2;
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int fBits = GetFBits(context);
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int bytes = op.GetBitsCount() >> 3;
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int elems = !scalar ? bytes >> sizeI : 1;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractF(context, op.Rn, index, sizeF);
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EmitF2iFBitsMul(context, sizeF, fBits);
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if (sizeF == 0)
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{
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VectorHelper.EmitCall(context, signed
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? nameof(VectorHelper.SatF32ToS32)
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: nameof(VectorHelper.SatF32ToU32));
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context.Emit(OpCodes.Conv_U8);
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}
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else /* if (sizeF == 1) */
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{
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VectorHelper.EmitCall(context, signed
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? nameof(VectorHelper.SatF64ToS64)
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: nameof(VectorHelper.SatF64ToU64));
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}
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if (scalar)
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{
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EmitVectorZeroAll(context, op.Rd);
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}
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EmitVectorInsert(context, op.Rd, index, sizeI);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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private static void EmitFcvt_s_Gp(ILEmitterCtx context, Action emit)
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{
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EmitFcvt___Gp(context, emit, true);
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}
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private static void EmitFcvt_u_Gp(ILEmitterCtx context, Action emit)
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{
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EmitFcvt___Gp(context, emit, false);
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}
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private static void EmitFcvt___Gp(ILEmitterCtx context, Action emit, bool signed)
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{
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OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
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EmitVectorExtractF(context, op.Rn, 0, op.Size);
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emit();
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if (signed)
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{
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EmitScalarFcvts(context, op.Size, 0);
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}
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else
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{
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EmitScalarFcvtu(context, op.Size, 0);
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}
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
{
|
|
context.Emit(OpCodes.Conv_U8);
|
|
}
|
|
|
|
context.EmitStintzr(op.Rd);
|
|
}
|
|
|
|
private static void EmitFcvtzs_Gp_Fixed(ILEmitterCtx context)
|
|
{
|
|
EmitFcvtz__Gp_Fixed(context, true);
|
|
}
|
|
|
|
private static void EmitFcvtzu_Gp_Fixed(ILEmitterCtx context)
|
|
{
|
|
EmitFcvtz__Gp_Fixed(context, false);
|
|
}
|
|
|
|
private static void EmitFcvtz__Gp_Fixed(ILEmitterCtx context, bool signed)
|
|
{
|
|
OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
|
|
|
|
EmitVectorExtractF(context, op.Rn, 0, op.Size);
|
|
|
|
if (signed)
|
|
{
|
|
EmitScalarFcvts(context, op.Size, op.FBits);
|
|
}
|
|
else
|
|
{
|
|
EmitScalarFcvtu(context, op.Size, op.FBits);
|
|
}
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
{
|
|
context.Emit(OpCodes.Conv_U8);
|
|
}
|
|
|
|
context.EmitStintzr(op.Rd);
|
|
}
|
|
|
|
private static void EmitVectorCvtf(ILEmitterCtx context, bool signed)
|
|
{
|
|
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
|
|
|
|
int sizeF = op.Size & 1;
|
|
int sizeI = sizeF + 2;
|
|
|
|
int fBits = GetFBits(context);
|
|
|
|
int bytes = op.GetBitsCount() >> 3;
|
|
int elems = bytes >> sizeI;
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
EmitVectorExtract(context, op.Rn, index, sizeI, signed);
|
|
|
|
if (!signed)
|
|
{
|
|
context.Emit(OpCodes.Conv_R_Un);
|
|
}
|
|
|
|
EmitFloatCast(context, sizeF);
|
|
|
|
EmitI2fFBitsMul(context, sizeF, fBits);
|
|
|
|
EmitVectorInsertF(context, op.Rd, index, sizeF);
|
|
}
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
EmitVectorZeroUpper(context, op.Rd);
|
|
}
|
|
}
|
|
|
|
private static int GetFBits(ILEmitterCtx context)
|
|
{
|
|
if (context.CurrOp is OpCodeSimdShImm64 op)
|
|
{
|
|
return GetImmShr(op);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
private static void EmitFloatCast(ILEmitterCtx context, int size)
|
|
{
|
|
if (size == 0)
|
|
{
|
|
context.Emit(OpCodes.Conv_R4);
|
|
}
|
|
else if (size == 1)
|
|
{
|
|
context.Emit(OpCodes.Conv_R8);
|
|
}
|
|
else
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
}
|
|
|
|
private static void EmitScalarFcvts(ILEmitterCtx context, int size, int fBits)
|
|
{
|
|
if (size < 0 || size > 1)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
EmitF2iFBitsMul(context, size, fBits);
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
{
|
|
if (size == 0)
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToS32));
|
|
}
|
|
else /* if (size == 1) */
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToS32));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (size == 0)
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToS64));
|
|
}
|
|
else /* if (size == 1) */
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToS64));
|
|
}
|
|
}
|
|
}
|
|
|
|
private static void EmitScalarFcvtu(ILEmitterCtx context, int size, int fBits)
|
|
{
|
|
if (size < 0 || size > 1)
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
EmitF2iFBitsMul(context, size, fBits);
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
{
|
|
if (size == 0)
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToU32));
|
|
}
|
|
else /* if (size == 1) */
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToU32));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (size == 0)
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToU64));
|
|
}
|
|
else /* if (size == 1) */
|
|
{
|
|
VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToU64));
|
|
}
|
|
}
|
|
}
|
|
|
|
private static void EmitF2iFBitsMul(ILEmitterCtx context, int size, int fBits)
|
|
{
|
|
if (fBits != 0)
|
|
{
|
|
if (size == 0)
|
|
{
|
|
context.EmitLdc_R4(MathF.Pow(2f, fBits));
|
|
}
|
|
else if (size == 1)
|
|
{
|
|
context.EmitLdc_R8(Math.Pow(2d, fBits));
|
|
}
|
|
else
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
context.Emit(OpCodes.Mul);
|
|
}
|
|
}
|
|
|
|
private static void EmitI2fFBitsMul(ILEmitterCtx context, int size, int fBits)
|
|
{
|
|
if (fBits != 0)
|
|
{
|
|
if (size == 0)
|
|
{
|
|
context.EmitLdc_R4(1f / MathF.Pow(2f, fBits));
|
|
}
|
|
else if (size == 1)
|
|
{
|
|
context.EmitLdc_R8(1d / Math.Pow(2d, fBits));
|
|
}
|
|
else
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
context.Emit(OpCodes.Mul);
|
|
}
|
|
}
|
|
}
|
|
}
|