mirror of
https://github.com/GreemDev/Ryujinx.git
synced 2024-11-28 11:50:50 +01:00
98e05ee4b7
* Decoders: Add InITBlock argument
* OpCodeTable: Minor cleanup
* OpCodeTable: Remove existing thumb instruction implementations
* OpCodeTable: Prepare for thumb instructions
* OpCodeTables: Improve thumb fast lookup
* Tests: Prepare for thumb tests
* T16: Implement BX
* T16: Implement LSL/LSR/ASR (imm)
* T16: Implement ADDS, SUBS (reg)
* T16: Implement ADDS, SUBS (3-bit immediate)
* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)
* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
* T16: Implement ADD, CMP, MOV (high reg)
* T16: Implement BLX (reg)
* T16: Implement LDR (literal)
* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)
* T16: Implement {LDR,STR}{,B,H} (immediate)
* T16: Implement LDR/STR (SP)
* T16: Implement ADR
* T16: Implement Add to SP (immediate)
* T16: Implement ADD/SUB (SP)
* T16: Implement SXTH, SXTB, UXTH, UTXB
* T16: Implement CBZ, CBNZ
* T16: Implement PUSH, POP
* T16: Implement REV, REV16, REVSH
* T16: Implement NOP
* T16: Implement LDM, STM
* T16: Implement SVC
* T16: Implement B (conditional)
* T16: Implement B (unconditional)
* T16: Implement IT
* fixup! T16: Implement ADD/SUB (SP)
* fixup! T16: Implement Add to SP (immediate)
* fixup! T16: Implement IT
* CpuTestThumb: Add randomized tests
* Remove inITBlock argument
* Address nits
* Use index to handle IfThenBlockState
* Reduce line noise
* fixup
* nit
656 lines
10 KiB
C#
656 lines
10 KiB
C#
namespace ARMeilleure.Instructions
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{
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enum InstName
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{
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// Base (AArch64)
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Adc,
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Adcs,
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Add,
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Adds,
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Adr,
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Adrp,
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And,
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Ands,
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Asrv,
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B,
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B_Cond,
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Bfm,
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Bic,
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Bics,
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Bl,
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Blr,
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Br,
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Brk,
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Cbnz,
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Cbz,
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Ccmn,
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Ccmp,
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Clrex,
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Cls,
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Clz,
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Crc32b,
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Crc32h,
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Crc32w,
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Crc32x,
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Crc32cb,
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Crc32ch,
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Crc32cw,
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Crc32cx,
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Csdb,
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Csel,
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Csinc,
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Csinv,
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Csneg,
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Dmb,
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Dsb,
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Eon,
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Eor,
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Extr,
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Hint,
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Isb,
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It,
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Ldar,
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Ldaxp,
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Ldaxr,
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Ldp,
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Ldr,
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Ldr_Literal,
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Ldrs,
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Ldxr,
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Ldxp,
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Lslv,
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Lsrv,
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Madd,
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Movk,
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Movn,
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Movz,
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Mrs,
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Msr,
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Msub,
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Nop,
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Orn,
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Orr,
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Prfm,
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Rbit,
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Ret,
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Rev16,
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Rev32,
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Rev64,
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Rorv,
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Sbc,
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Sbcs,
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Sbfm,
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Sdiv,
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Shsub8,
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Smaddl,
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Smsubl,
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Smulh,
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Smull,
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Smulw_,
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Ssat,
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Ssat16,
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Stlr,
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Stlxp,
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Stlxr,
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Stp,
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Str,
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Stxp,
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Stxr,
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Sub,
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Subs,
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Svc,
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Sxtb,
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Sxth,
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Sys,
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Tbnz,
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Tbz,
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Ubfm,
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Udiv,
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Umaddl,
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Umsubl,
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Umulh,
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Und,
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// FP & SIMD (AArch64)
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Abs_S,
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Abs_V,
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Add_S,
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Add_V,
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Addhn_V,
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Addp_S,
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Addp_V,
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Addv_V,
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Aesd_V,
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Aese_V,
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Aesimc_V,
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Aesmc_V,
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And_V,
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Bic_V,
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Bic_Vi,
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Bif_V,
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Bit_V,
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Bsl_V,
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Cls_V,
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Clz_V,
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Cmeq_S,
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Cmeq_V,
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Cmge_S,
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Cmge_V,
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Cmgt_S,
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Cmgt_V,
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Cmhi_S,
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Cmhi_V,
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Cmhs_S,
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Cmhs_V,
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Cmle_S,
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Cmle_V,
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Cmlt_S,
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Cmlt_V,
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Cmtst_S,
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Cmtst_V,
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Cnt_V,
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Dup_Gp,
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Dup_S,
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Dup_V,
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Eor_V,
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Ext_V,
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Fabd_S,
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Fabd_V,
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Fabs_S,
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Fabs_V,
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Facge_S,
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Facge_V,
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Facgt_S,
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Facgt_V,
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Fadd_S,
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Fadd_V,
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Faddp_S,
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Faddp_V,
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Fccmp_S,
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Fccmpe_S,
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Fcmeq_S,
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Fcmeq_V,
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Fcmge_S,
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Fcmge_V,
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Fcmgt_S,
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Fcmgt_V,
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Fcmle_S,
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Fcmle_V,
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Fcmlt_S,
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Fcmlt_V,
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Fcmp_S,
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Fcmpe_S,
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Fcsel_S,
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Fcvt_S,
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Fcvtas_Gp,
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Fcvtas_S,
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Fcvtas_V,
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Fcvtau_Gp,
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Fcvtau_S,
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Fcvtau_V,
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Fcvtl_V,
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Fcvtms_Gp,
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Fcvtms_V,
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Fcvtmu_Gp,
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Fcvtn_V,
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Fcvtns_Gp,
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Fcvtns_S,
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Fcvtns_V,
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Fcvtnu_S,
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Fcvtnu_V,
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Fcvtps_Gp,
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Fcvtpu_Gp,
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Fcvtzs_Gp,
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Fcvtzs_Gp_Fixed,
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Fcvtzs_S,
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Fcvtzs_V,
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Fcvtzs_V_Fixed,
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Fcvtzu_Gp,
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Fcvtzu_Gp_Fixed,
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Fcvtzu_S,
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Fcvtzu_V,
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Fcvtzu_V_Fixed,
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Fdiv_S,
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Fdiv_V,
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Fmadd_S,
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Fmax_S,
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Fmax_V,
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Fmaxnm_S,
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Fmaxnm_V,
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Fmaxnmp_S,
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Fmaxnmp_V,
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Fmaxnmv_V,
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Fmaxp_V,
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Fmaxv_V,
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Fmin_S,
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Fmin_V,
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Fminnm_S,
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Fminnm_V,
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Fminnmp_S,
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Fminnmp_V,
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Fminnmv_V,
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Fminp_V,
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Fminv_V,
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Fmla_Se,
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Fmla_V,
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Fmla_Ve,
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Fmls_Se,
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Fmls_V,
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Fmls_Ve,
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Fmov_S,
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Fmov_Si,
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Fmov_Vi,
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Fmov_Ftoi,
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Fmov_Itof,
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Fmov_Ftoi1,
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Fmov_Itof1,
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Fmsub_S,
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Fmul_S,
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Fmul_Se,
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Fmul_V,
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Fmul_Ve,
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Fmulx_S,
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Fmulx_Se,
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Fmulx_V,
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Fmulx_Ve,
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Fneg_S,
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Fneg_V,
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Fnmadd_S,
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Fnmsub_S,
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Fnmul_S,
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Frecpe_S,
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Frecpe_V,
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Frecps_S,
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Frecps_V,
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Frecpx_S,
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Frinta_S,
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Frinta_V,
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Frinti_S,
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Frinti_V,
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Frintm_S,
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Frintm_V,
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Frintn_S,
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Frintn_V,
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Frintp_S,
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Frintp_V,
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Frintx_S,
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Frintx_V,
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Frintz_S,
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Frintz_V,
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Frsqrte_S,
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Frsqrte_V,
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Frsqrts_S,
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Frsqrts_V,
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Fsqrt_S,
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Fsqrt_V,
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Fsub_S,
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Fsub_V,
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Ins_Gp,
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Ins_V,
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Ld__Vms,
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Ld__Vss,
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Mla_V,
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Mla_Ve,
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Mls_V,
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Mls_Ve,
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Movi_V,
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Mul_V,
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Mul_Ve,
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Mvni_V,
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Neg_S,
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Neg_V,
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Not_V,
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Orn_V,
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Orr_V,
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Orr_Vi,
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Pmull_V,
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Raddhn_V,
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Rbit_V,
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Rev16_V,
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Rev32_V,
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Rev64_V,
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Rshrn_V,
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Rsubhn_V,
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Saba_V,
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Sabal_V,
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Sabd_V,
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Sabdl_V,
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Sadalp_V,
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Saddl_V,
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Saddlp_V,
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Saddlv_V,
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Saddw_V,
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Scvtf_Gp,
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Scvtf_Gp_Fixed,
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Scvtf_S,
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Scvtf_S_Fixed,
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Scvtf_V,
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Scvtf_V_Fixed,
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Sha1c_V,
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Sha1h_V,
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Sha1m_V,
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Sha1p_V,
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Sha1su0_V,
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Sha1su1_V,
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Sha256h_V,
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Sha256h2_V,
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Sha256su0_V,
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Sha256su1_V,
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Shadd_V,
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Shl_S,
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Shl_V,
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Shll_V,
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Shrn_V,
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Shsub_V,
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Sli_S,
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Sli_V,
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Smax_V,
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Smaxp_V,
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Smaxv_V,
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Smin_V,
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Sminp_V,
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Sminv_V,
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Smlal_V,
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Smlal_Ve,
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Smlsl_V,
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Smlsl_Ve,
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Smov_S,
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Smull_V,
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Smull_Ve,
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Sqabs_S,
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Sqabs_V,
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Sqadd_S,
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Sqadd_V,
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Sqdmulh_S,
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Sqdmulh_V,
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Sqdmulh_Ve,
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Sqneg_S,
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Sqneg_V,
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Sqrdmulh_S,
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Sqrdmulh_V,
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Sqrdmulh_Ve,
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Sqrshl_V,
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Sqrshrn_S,
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Sqrshrn_V,
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Sqrshrun_S,
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Sqrshrun_V,
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Sqshl_V,
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Sqshrn_S,
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Sqshrn_V,
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Sqshrun_S,
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Sqshrun_V,
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Sqsub_S,
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Sqsub_V,
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Sqxtn_S,
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Sqxtn_V,
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Sqxtun_S,
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Sqxtun_V,
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Srhadd_V,
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Sri_S,
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Sri_V,
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Srshl_V,
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Srshr_S,
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Srshr_V,
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Srsra_S,
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Srsra_V,
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Sshl_S,
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Sshl_V,
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Sshll_V,
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Sshr_S,
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Sshr_V,
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Ssra_S,
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Ssra_V,
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Ssubl_V,
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Ssubw_V,
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St__Vms,
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St__Vss,
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Sub_S,
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Sub_V,
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Subhn_V,
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Suqadd_S,
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Suqadd_V,
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Tbl_V,
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Tbx_V,
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Trn1_V,
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Trn2_V,
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Uaba_V,
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Uabal_V,
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Uabd_V,
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Uabdl_V,
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Uadalp_V,
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Uaddl_V,
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Uaddlp_V,
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Uaddlv_V,
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Uaddw_V,
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Ucvtf_Gp,
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Ucvtf_Gp_Fixed,
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Ucvtf_S,
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Ucvtf_S_Fixed,
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Ucvtf_V,
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Ucvtf_V_Fixed,
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Uhadd_V,
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Uhsub_V,
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Umax_V,
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Umaxp_V,
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Umaxv_V,
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Umin_V,
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Uminp_V,
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Uminv_V,
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Umlal_V,
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Umlal_Ve,
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Umlsl_V,
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Umlsl_Ve,
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Umov_S,
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Umull_V,
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Umull_Ve,
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Uqadd_S,
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Uqadd_V,
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Uqrshl_V,
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Uqrshrn_S,
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Uqrshrn_V,
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Uqshl_V,
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Uqshrn_S,
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Uqshrn_V,
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Uqsub_S,
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Uqsub_V,
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Uqxtn_S,
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Uqxtn_V,
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Urhadd_V,
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Urshl_V,
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Urshr_S,
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Urshr_V,
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Ursra_S,
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Ursra_V,
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Ushl_S,
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Ushl_V,
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Ushll_V,
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Ushr_S,
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Ushr_V,
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Usqadd_S,
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Usqadd_V,
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Usra_S,
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Usra_V,
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Usubl_V,
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Usubw_V,
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Uzp1_V,
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Uzp2_V,
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Xtn_V,
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Zip1_V,
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Zip2_V,
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// Base (AArch32)
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Bfc,
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Bfi,
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Blx,
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Bx,
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Cmp,
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Cmn,
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Movt,
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Mul,
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Lda,
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Ldab,
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Ldaex,
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Ldaexb,
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Ldaexd,
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Ldaexh,
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Ldah,
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Ldm,
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Ldrb,
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Ldrd,
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Ldrex,
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Ldrexb,
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Ldrexd,
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Ldrexh,
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Ldrh,
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Ldrsb,
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Ldrsh,
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Mcr,
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Mla,
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Mls,
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Mov,
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Mrc,
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Mrrc,
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Mvn,
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Pkh,
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Pld,
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Pop,
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Push,
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Rev,
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Revsh,
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Rsb,
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Rsc,
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Sbfx,
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Shadd8,
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Smla__,
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Smlal,
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Smlal__,
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Smlaw_,
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Smmla,
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Smmls,
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Smul__,
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Smmul,
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Stl,
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Stlb,
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Stlex,
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Stlexb,
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Stlexd,
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Stlexh,
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Stlh,
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Stm,
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Strb,
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Strd,
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Strex,
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Strexb,
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Strexd,
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Strexh,
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Strh,
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Sxtb16,
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Teq,
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Trap,
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Tst,
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Ubfx,
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Uhadd8,
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Uhsub8,
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Umaal,
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Umlal,
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Umull,
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Usat,
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Usat16,
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Uxtb,
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Uxtb16,
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Uxth,
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// FP & SIMD (AArch32)
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Vabd,
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Vabdl,
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Vabs,
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Vadd,
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Vaddl,
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Vaddw,
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Vand,
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Vbic,
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Vbif,
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Vbit,
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Vbsl,
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Vceq,
|
|
Vcge,
|
|
Vcgt,
|
|
Vcle,
|
|
Vclt,
|
|
Vcmp,
|
|
Vcmpe,
|
|
Vcnt,
|
|
Vcvt,
|
|
Vdiv,
|
|
Vdup,
|
|
Veor,
|
|
Vext,
|
|
Vfma,
|
|
Vfms,
|
|
Vfnma,
|
|
Vfnms,
|
|
Vhadd,
|
|
Vld1,
|
|
Vld2,
|
|
Vld3,
|
|
Vld4,
|
|
Vldm,
|
|
Vldr,
|
|
Vmax,
|
|
Vmaxnm,
|
|
Vmin,
|
|
Vminnm,
|
|
Vmla,
|
|
Vmls,
|
|
Vmlsl,
|
|
Vmov,
|
|
Vmovl,
|
|
Vmovn,
|
|
Vmrs,
|
|
Vmsr,
|
|
Vmul,
|
|
Vmull,
|
|
Vmvn,
|
|
Vneg,
|
|
Vnmul,
|
|
Vnmla,
|
|
Vnmls,
|
|
Vorn,
|
|
Vorr,
|
|
Vpadd,
|
|
Vpmax,
|
|
Vpmin,
|
|
Vqrshrn,
|
|
Vqrshrun,
|
|
Vqshrn,
|
|
Vrev,
|
|
Vrint,
|
|
Vrintx,
|
|
Vrshr,
|
|
Vsel,
|
|
Vshl,
|
|
Vshll,
|
|
Vshr,
|
|
Vshrn,
|
|
Vst1,
|
|
Vst2,
|
|
Vst3,
|
|
Vst4,
|
|
Vstm,
|
|
Vstr,
|
|
Vsqrt,
|
|
Vrecpe,
|
|
Vrecps,
|
|
Vrsqrte,
|
|
Vrsqrts,
|
|
Vsra,
|
|
Vsub,
|
|
Vsubw,
|
|
Vtbl,
|
|
Vtrn,
|
|
Vtst,
|
|
Vuzp,
|
|
Vzip,
|
|
}
|
|
}
|