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ARM_Interface: Allow for partial invalidation of instruction cache
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@ -4,6 +4,7 @@
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#pragma once
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#include <cstddef>
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/vfp/asm_vfp.h"
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@ -33,6 +34,13 @@ public:
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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/**
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* Invalidate the code cache at a range of addresses.
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* @param start_address The starting address of the range to invalidate.
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* @param length The length (in bytes) of the range to invalidate.
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*/
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virtual void InvalidateCacheRange(u32 start_address, size_t length) = 0;
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/// Notify CPU emulation that page tables have changed
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virtual void PageTableChanged() = 0;
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@ -187,6 +187,10 @@ void ARM_Dynarmic::ClearInstructionCache() {
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}
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}
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void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, size_t length) {
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jit->InvalidateCacheRange(start_address, length);
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}
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void ARM_Dynarmic::PageTableChanged() {
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current_page_table = Memory::GetCurrentPageTable();
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@ -41,6 +41,7 @@ public:
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void PrepareReschedule() override;
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void ClearInstructionCache() override;
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void InvalidateCacheRange(u32 start_address, size_t length) override;
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void PageTableChanged() override;
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private:
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@ -34,6 +34,10 @@ void ARM_DynCom::ClearInstructionCache() {
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trans_cache_buf_top = 0;
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}
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void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
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ClearInstructionCache();
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}
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void ARM_DynCom::PageTableChanged() {
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ClearInstructionCache();
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}
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@ -19,6 +19,7 @@ public:
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void Step() override;
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void ClearInstructionCache() override;
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void InvalidateCacheRange(u32 start_address, size_t length) override;
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void PageTableChanged() override;
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void SetPC(u32 pc) override;
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