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24b5e87279
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95 Commits

Author SHA1 Message Date
bunnei
24b5e87279 Merge pull request #304 from lioncash/sflags 
armemu: Set GE flags properly for SSUB16, SADD16, SSAX, and SASX.
 2014-12-18 17:46:10 -05:00
Lioncash
e683f654ce armemu: Fix lower-bounds clamping for USAT16 2014-12-18 16:54:01 -05:00
Lioncash
6b632bbe37 armemu: More concise names for USAT16-related variables 2014-12-18 14:25:07 -05:00
Lioncash
4dc8eb40be armemu: Set GE flags correctly for SSUB16, SADD16, SSAX, and SASX. 2014-12-18 11:45:40 -05:00
bunnei
8ac22e7efc Merge pull request #299 from lioncash/join 
Combine SSUB16, SADD16, SASX, and SSAX.
 2014-12-18 10:04:31 -05:00
bunnei
797efbde1a Merge pull request #298 from lioncash/flags 
armemu: Unset GE flags for UADD8 if results are < 0x100
 2014-12-17 22:06:27 -05:00
bunnei
a968adf50e Merge pull request #295 from lioncash/umaal 
armemu: Implement UMAAL
 2014-12-17 21:44:13 -05:00
Lioncash
85c318078d armemu: Combine SSUB16, SADD16, SASX, and SSAX. 2014-12-17 21:17:54 -05:00
bunnei
075126247f Merge pull request #292 from lioncash/backports 
Backport more skyeye fixes from 3dmoo
 2014-12-17 20:58:00 -05:00
Lioncash
41fee1c940 armemu: Unset GE flags for UADD8 if results are < 0x100 
Reference manual states these must be set to zero if this case is true.
 2014-12-17 17:54:49 -05:00
Lioncash
58dc554733 armemu: Fix SSUB16 
Broken from the same reason SADD16 was.

The lo part of the result should only be constructed from the lo halfwords of rm and rn.
The hi part of the result should only be constructed from the hi halfwords of rm and rn.
 2014-12-17 15:40:10 -05:00
bunnei
e6f440ea7f Merge pull request #293 from lioncash/sops 
armemu: Fix SADD16
 2014-12-17 14:54:24 -05:00
bunnei
3e9d4a7917 Merge pull request #287 from lioncash/qaddsub16 
armemu: Join QADD16/QSUB16 and fix saturation clamping.
 2014-12-17 12:34:52 -05:00
Lioncash
5820dba6b7 armemu: Implement UMAAL 2014-12-17 12:21:21 -05:00
Lioncash
5289a496a7 armemu: Fix SADD16 
The lo and hi parts of the result were being constructed as a result of hi and lo halfword intermixing from the rm and rn regs. However the lo part of the result should be constructed only from the lo halfwords of rm and rn, and the hi part of the result should only be constructed from the hi halfwords of rm and rn.
 2014-12-17 09:36:25 -05:00
Normmatt
73211dc8fe armemu: Fix PKHTB 2014-12-17 03:26:12 -05:00
Normmatt
8045df14d2 armemu: Implement REVSH 2014-12-17 03:26:01 -05:00
Normmatt
bc81cc9490 armemu: Fix UXTAB/UXTAH 2014-12-17 03:24:25 -05:00
Normmatt
b5dbd6f2a2 armemu: Fix SXTAB 2014-12-17 03:17:44 -05:00
Normmatt
efebd5589a armemu: Fix SXTAH 2014-12-17 03:16:40 -05:00
bunnei
fdb4ef5210 Merge pull request #289 from lioncash/smops 
Join SMUAD, SMUSD, and SMLAD ops. Also fix them as well.
 2014-12-17 00:08:43 -05:00
Lioncash
d5bcddb77c armemu: Fix SMUAD, SMUSD, and SMLAD 
Wrong values were being multiplied together.
 2014-12-16 03:13:06 -05:00
Lioncash
0f9e3baf39 armemu: Join SMUAD, SMUSD, and SMLAD 2014-12-16 03:11:50 -05:00
Lioncash
4c53799229 armemu: Fix lower-bound signed saturation clamping for QADD16/QSUB16. 2014-12-16 00:11:51 -05:00
Lioncash
49817e89d9 armemu: Join QADD16 and QSUB16 together. 
The only difference between these ops is one adds and one subtracts. Everything is literally the same.
 2014-12-16 00:11:19 -05:00
Lioncash
1c7f77334c armemu: Implement UXTAB16 2014-12-15 20:47:27 -05:00
Lioncash
2b0acd36e1 armemu: Fix UXTB16 
Rotation bits are 10 and 11, not 9 and 10.
 2014-12-14 23:00:31 -05:00
bunnei
d26b7146ce ARM: Pull some SkyEye fixes from 3dmoo. 2014-12-14 21:51:46 -05:00
Yuri Kunde Schlesner
0600e2d8b5 Convert old logging calls to new logging macros 2014-12-13 02:08:02 -02:00
Lioncash
905e3b616a armemu: Fix SSAX 2014-12-08 15:47:20 -05:00
Lioncash
62fd564854 armemu: Fix SASX 2014-12-08 01:44:37 -05:00
Lioncash
b4256431aa armemu: Fix parenthesis warnings regarding bitwise ops 2014-12-07 23:58:12 -05:00
Emmanuel Gil Peyrot
f5d38649c7 Remove trailing spaces in every file but the ones imported from SkyEye, AOSP or generated 2014-11-19 09:03:07 +00:00
Lioncash
64cc6cb6cf Fix documentation of parameters 2014-11-18 08:31:24 -05:00
bunnei
0832cf7cd7 ARM: Merged additional ARMv6 instructions implemented by 3dmoo. 2014-11-02 01:04:54 -05:00
Yuri Kunde Schlesner
d72708c1f5 Add override keyword through the code. 
This was automated using `clang-modernize`.
 2014-10-26 16:18:05 -02:00
bunnei
818ba32746 ARM: Removed unnecessary and unused SkyEye MMU code. 
Added license header back in. I originally removed this because I mostly rewrote the file, but meh
 2014-10-25 14:11:41 -04:00
bunnei
3c823c0028 ARM: Removed unused armos code from SkyEye. 2014-10-25 14:11:40 -04:00
bunnei
53a22b84da ARM: Integrate SkyEye faster "dyncom" interpreter. 
Fixed typo (make protected member public)

Added license header back in. I originally removed this because I mostly rewrote the file, but meh

ARM: Fixed a type error in dyncom interpreter.

ARM: Updated dyncom to use unique_ptr for internal ARM state.
 2014-10-25 14:11:39 -04:00
bunnei
b5e6524594 ARM: Reorganized file structure to move shared SkyEye code to a more common area. 
Removed s_ prefix
 2014-10-25 14:11:39 -04:00
Lioncash
403c84cdab core: Make the ARM disassembler use std::string internally 2014-09-06 14:45:56 -04:00
bunnei
304999dfeb Threading: Fix thread starting to execute first instruction correctly. 2014-08-28 17:51:49 -04:00
Emmanuel Gil Peyrot
ef27770a53 ARM: Remove a forgotten const in vfp. 2014-08-20 17:50:27 +00:00
bunnei
77fc029a00 ARM: Synchronize Citra's SkyEye core with 3dmoo's. 2014-07-23 19:16:40 -04:00
Lioncash
8761461003 core: Kill off type redefenitions in armdefs.h 2014-07-19 22:02:21 -04:00
bunnei
004df76795 Merge branch 'threading' of https://github.com/bunnei/citra 
Conflicts:
	src/core/hle/function_wrappers.h
	src/core/hle/service/gsp.cpp
 2014-06-14 12:13:16 -04:00
bunnei
6cdad8390c arm: fixed a bug where ARM_Interpreter::ExecuteInstructions was actually executing one more instruction than expected 2014-06-05 00:25:32 -04:00
bunnei
9ece9da50d arm: fixed bug in how thread context switch occurs with SkyEye 2014-06-05 00:20:11 -04:00
bunnei
c330a0a1d6 arm: reverting a change made with cb0663de - this has to have been a typo! 2014-06-04 18:41:44 -04:00
bunnei
e8a17ee6fd arm: added option to prepare CPU core (while mid-instruction) for thread reschedule 2014-06-01 21:40:10 -04:00