mirror of
https://github.com/exA-Arcadia/exa-io.git
synced 2024-11-23 22:20:58 +01:00
Update PCB to v1.4
This commit is contained in:
parent
b37abeb8ce
commit
12b1a718ed
38416
td-io.kicad_pcb
38416
td-io.kicad_pcb
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,6 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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@ -72,20 +73,26 @@
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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@ -95,9 +102,14 @@
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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@ -106,7 +118,6 @@
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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@ -116,18 +127,63 @@
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.16,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.024999999999999998,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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},
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"teardrop_options": [
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{
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"td_allow_use_two_tracks": true,
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"td_curve_segcount": 5,
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"td_on_pad_in_zone": false,
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"td_onpadsmd": true,
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"td_onroundshapesonly": false,
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"td_ontrackend": false,
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"td_onviapad": true
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}
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],
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"teardrop_parameters": [
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_round_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_rect_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_track_end",
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [
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0.0,
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0.4,
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@ -333,18 +389,23 @@
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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@ -354,6 +415,7 @@
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"simulation_model_issue": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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@ -371,7 +433,7 @@
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -385,13 +447,15 @@
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6
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}
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],
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"meta": {
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"version": 2
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"version": 3
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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"pcbnew": {
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"last_paths": {
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@ -407,6 +471,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"field_names": [],
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@ -438,7 +504,11 @@
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"page_layout_descr_file": "",
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"plot_directory": "v1.1/",
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"spice_adjust_passive_values": false,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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},
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474
td-io.kicad_sch
474
td-io.kicad_sch
File diff suppressed because it is too large
Load Diff
72
td-io.pretty/Vishay_PowerPAK_MLP44-24L.kicad_mod
Normal file
72
td-io.pretty/Vishay_PowerPAK_MLP44-24L.kicad_mod
Normal file
@ -0,0 +1,72 @@
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(footprint "Vishay_PowerPAK_MLP44-24L" (version 20211014) (generator pcbnew)
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(layer "F.Cu")
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(tedit 0)
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(attr smd)
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(fp_text reference "REF**" (at 0 -3.4 unlocked) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp c4f57582-4080-45a6-a9b5-4be5dc62757b)
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)
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(fp_text value "Vishay_PowerPAK_MLP44-24L" (at 0.045 3.625 unlocked) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp f0072e3b-764d-4f62-befa-15d6bbdb13ce)
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)
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(fp_line (start 1.775 -2.125) (end 2.12 -2.125) (layer "F.SilkS") (width 0.12) (tstamp 0258c08a-be92-4edf-93b5-134521353f54))
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(fp_line (start 2.12 2.125) (end 2.12 1.65) (layer "F.SilkS") (width 0.12) (tstamp 08b975fd-792f-4845-bd45-aa94a9715019))
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(fp_line (start -2.1375 2.125) (end -2.1375 1.65) (layer "F.SilkS") (width 0.12) (tstamp 13853726-09ca-40f2-87c3-a8956bc4af4f))
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(fp_line (start -1.8 2.125) (end -2.1375 2.125) (layer "F.SilkS") (width 0.12) (tstamp 30a2eafc-94ad-42f6-a273-320ae0170f00))
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(fp_line (start 2.12 -2.125) (end 2.12 -1.65) (layer "F.SilkS") (width 0.12) (tstamp 959548e4-215a-42fe-85b9-49abc835c8f6))
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(fp_line (start -1.775 -2.125) (end -2.1625 -2.125) (layer "F.SilkS") (width 0.12) (tstamp b65a6a12-0d08-40f3-8ed6-a5edbc348e2e))
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(fp_line (start 1.645 2.125) (end 2.12 2.125) (layer "F.SilkS") (width 0.12) (tstamp d1c96f7d-e91d-431f-ac4e-25d37441b0c2))
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(fp_rect (start -2 -2) (end 2 2) (layer "Dwgs.User") (width 0.01) (fill none) (tstamp 67dd1d71-2fd5-454b-b66d-8bf245fffe1f))
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(fp_rect (start -2.5 -2.5) (end 2.5 2.5) (layer "F.CrtYd") (width 0.12) (fill none) (tstamp 6f608cd3-f53a-40f2-a369-38a6dae4322e))
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(pad "1" smd rect (at -1.9375 -0.825 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6bdd9c3c-efac-4a57-bb07-e6683205632f))
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(pad "2" smd rect (at -1.9375 -0.375 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp eb99ee24-a3c5-4771-885a-b57f683a81bf))
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(pad "3" smd rect (at -1.9375 0.525 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd724dea-5ddf-4dc5-b197-1222f863928b))
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(pad "4" smd rect (at -1.9375 0.975 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 47b7fa05-79cf-4553-b55a-b508ddfa70b6))
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(pad "5" smd rect (at -1.475 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ca9e0d-a75e-46da-904b-483a5ea040d0))
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(pad "5" smd rect (at -0.45 1.7125) (size 2.35 0.275) (layers "F.Cu" "F.Mask")
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(solder_paste_margin -0.25) (tstamp 97c285fd-8323-4270-8825-22d29170abf0))
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(pad "6" smd rect (at -1.025 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp eb0f64ec-086d-404a-8d10-8cdc064dd95c))
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(pad "7" smd rect (at -0.575 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f0c1cf97-5213-4ff7-91e7-c14dd4cb4024))
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(pad "8" smd rect (at 0.125 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a730d9f1-4d83-4dcc-ba50-2565132a7c7c))
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(pad "9" smd rect (at 0.575 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 17f6e4b1-f741-42f9-8ed9-6f1502385d96))
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(pad "10" smd rect (at 1.025 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7eeef101-2e2f-4d42-8199-398d3debdf3a))
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(pad "11" smd rect (at 1.9375 1.425 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 93dfc21f-0329-45de-8023-66c36e70f4ab))
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(pad "12" smd rect (at 1.9375 0.975 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 74a9825e-2496-4ee4-be7e-f330ba87976b))
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(pad "13" smd rect (at 1.9375 0.525 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 136e9043-9d9b-4add-a5a0-c96121d24080))
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(pad "14" smd rect (at 1.9375 0.075 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 39cbdfe8-4219-489a-b4b0-f7bedc4a85bf))
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(pad "15" smd rect (at 1.9375 -0.375 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 57012bd4-7a89-4c9a-9d58-64dfe4df17cc))
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(pad "16" smd rect (at 1.9375 -0.825 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a91e522a-17a8-4f9b-a0e3-f4ee5d8c32d9))
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(pad "17" smd rect (at 1.9375 -1.275 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7d8cd1b5-f705-49aa-9f3f-48448af87fb2))
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||||
(pad "18" smd rect (at 1.475 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 866dc468-d99d-41c0-9910-848a99f6fbd7))
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||||
(pad "19" smd rect (at 1.025 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4c1ba172-4f35-4009-8d7e-0828fa740a34))
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||||
(pad "20" smd rect (at 0.575 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2895ff56-09b0-46dd-86ee-edf0fd324071))
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||||
(pad "21" smd rect (at 0.125 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e98ce279-a0ab-4dbd-b5f4-222b121fdd94))
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||||
(pad "22" smd rect (at -0.575 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d3ef78ce-773c-4241-8dda-5d93241ca604))
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||||
(pad "23" smd rect (at -1.025 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 976a6cb8-eccc-4a3f-897b-8a4695cb224f))
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||||
(pad "24" smd rect (at -1.475 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 92780cda-ec1c-4999-83e3-268cade2a316))
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||||
(pad "25" smd rect (at 0.4875 -0.75) (size 1.575 1.05) (layers "F.Cu" "F.Paste" "F.Mask")
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||||
(solder_paste_margin -0.25) (tstamp 7b6e123f-2ca8-4dd5-a8b2-190dad2a441d))
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||||
(pad "26" smd rect (at -1.175 -0.75) (size 1.15 1.05) (layers "F.Cu" "F.Paste" "F.Mask")
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||||
(solder_paste_margin -0.25) (tstamp f95ccdc9-0b3f-4e01-951a-2e822c448cd0))
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||||
(pad "27" smd custom (at -0.6625 0.675) (size 2.175 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
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(solder_paste_margin -0.25)
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(options (clearance outline) (anchor rect))
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(primitives
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(gr_poly (pts
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(xy 1.7375 -0.145)
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(xy 1.0875 -0.145)
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(xy 1.0875 0.6)
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(xy -1.0875 0.6)
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(xy -1.0875 -0.6)
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(xy 1.7375 -0.6)
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) (width 0) (fill yes))
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||||
(gr_rect (start 1.0875 -0.6) (end 1.7375 -0.145) (width 0) (fill yes))
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) (tstamp 3445a491-b638-454d-9c2c-20ae481cc70f))
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||||
(pad "28" smd rect (at 0.985 0.99) (size 0.58 0.38) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4e9c65ee-82f1-4318-a1c8-de0c1cf776cc))
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(model "${KICAD6_3DMODEL_DIR}/Package_DFN_QFN.3dshapes/WQFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm.step"
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(offset (xyz 0 0 0))
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||||
(scale (xyz 1 1 1))
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||||
(rotate (xyz 0 0 0))
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||||
)
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||||
)
|
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