2019-10-13 08:02:07 +02:00
|
|
|
using Ryujinx.Graphics.Shader.Decoders;
|
|
|
|
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
|
|
|
using Ryujinx.Graphics.Shader.Translation;
|
|
|
|
|
|
|
|
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
|
|
|
|
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
|
|
|
|
|
|
|
|
namespace Ryujinx.Graphics.Shader.Instructions
|
|
|
|
{
|
|
|
|
static partial class InstEmit
|
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void MovR(EmitterContext context)
|
2019-10-13 08:02:07 +02:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
InstMovR op = context.GetOp<InstMovR>();
|
|
|
|
|
|
|
|
context.Copy(GetDest(op.Dest), GetSrcReg(context, op.SrcA));
|
2019-10-13 08:02:07 +02:00
|
|
|
}
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void MovI(EmitterContext context)
|
2019-11-19 14:45:46 +01:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
InstMovI op = context.GetOp<InstMovI>();
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
context.Copy(GetDest(op.Dest), GetSrcImm(context, op.Imm20));
|
|
|
|
}
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void MovC(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstMovC op = context.GetOp<InstMovC>();
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
context.Copy(GetDest(op.Dest), GetSrcCbuf(context, op.CbufSlot, op.CbufOffset));
|
|
|
|
}
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void Mov32i(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstMov32i op = context.GetOp<InstMov32i>();
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
context.Copy(GetDest(op.Dest), GetSrcImm(context, op.Imm32));
|
|
|
|
}
|
2019-11-19 14:45:46 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void R2pR(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstR2pR op = context.GetOp<InstR2pR>();
|
|
|
|
|
|
|
|
Operand value = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand mask = GetSrcReg(context, op.SrcB);
|
|
|
|
|
|
|
|
EmitR2p(context, value, mask, op.ByteSel, op.Ccpr);
|
2019-11-19 14:45:46 +01:00
|
|
|
}
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void R2pI(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstR2pI op = context.GetOp<InstR2pI>();
|
|
|
|
|
|
|
|
Operand value = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand mask = GetSrcImm(context, Imm20ToSInt(op.Imm20));
|
|
|
|
|
|
|
|
EmitR2p(context, value, mask, op.ByteSel, op.Ccpr);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void R2pC(EmitterContext context)
|
2019-10-13 08:02:07 +02:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
InstR2pC op = context.GetOp<InstR2pC>();
|
|
|
|
|
|
|
|
Operand value = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand mask = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
|
2019-10-13 08:02:07 +02:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
EmitR2p(context, value, mask, op.ByteSel, op.Ccpr);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void S2r(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstS2r op = context.GetOp<InstS2r>();
|
2019-10-13 08:02:07 +02:00
|
|
|
|
|
|
|
Operand src;
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
switch (op.SReg)
|
2019-10-13 08:02:07 +02:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
case SReg.LaneId:
|
|
|
|
src = Attribute(AttributeConsts.LaneId);
|
|
|
|
break;
|
2019-11-08 21:29:41 +01:00
|
|
|
|
2021-10-18 23:38:04 +02:00
|
|
|
case SReg.InvocationId:
|
|
|
|
src = Attribute(AttributeConsts.InvocationId);
|
|
|
|
break;
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
case SReg.YDirection:
|
|
|
|
src = ConstF(1); // TODO: Use value from Y direction GPU register.
|
|
|
|
break;
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
case SReg.ThreadKill:
|
|
|
|
src = context.Config.Stage == ShaderStage.Fragment ? Attribute(AttributeConsts.ThreadKill) : Const(0);
|
2021-04-02 12:50:35 +02:00
|
|
|
break;
|
|
|
|
|
2021-10-18 23:38:04 +02:00
|
|
|
case SReg.InvocationInfo:
|
|
|
|
if (context.Config.Stage != ShaderStage.Compute && context.Config.Stage != ShaderStage.Fragment)
|
|
|
|
{
|
|
|
|
Operand primitiveId = Attribute(AttributeConsts.PrimitiveId);
|
2021-11-08 15:39:30 +01:00
|
|
|
Operand patchVerticesIn;
|
|
|
|
|
|
|
|
if (context.Config.Stage == ShaderStage.TessellationEvaluation)
|
|
|
|
{
|
|
|
|
patchVerticesIn = context.ShiftLeft(Attribute(AttributeConsts.PatchVerticesIn), Const(16));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
InputTopology inputTopology = context.Config.GpuAccessor.QueryPrimitiveTopology();
|
|
|
|
|
|
|
|
int inputVertices = inputTopology switch
|
|
|
|
{
|
|
|
|
InputTopology.Points => 1,
|
|
|
|
InputTopology.Lines or
|
|
|
|
InputTopology.LinesAdjacency => 2,
|
|
|
|
InputTopology.Triangles or
|
|
|
|
InputTopology.TrianglesAdjacency => 3,
|
|
|
|
_ => 1
|
|
|
|
};
|
|
|
|
|
|
|
|
patchVerticesIn = Const(inputVertices << 16);
|
|
|
|
}
|
2021-10-18 23:38:04 +02:00
|
|
|
|
|
|
|
src = context.BitwiseOr(primitiveId, patchVerticesIn);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
src = Const(0);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
case SReg.TId:
|
2019-10-26 19:50:52 +02:00
|
|
|
Operand tidX = Attribute(AttributeConsts.ThreadIdX);
|
|
|
|
Operand tidY = Attribute(AttributeConsts.ThreadIdY);
|
|
|
|
Operand tidZ = Attribute(AttributeConsts.ThreadIdZ);
|
|
|
|
|
|
|
|
tidY = context.ShiftLeft(tidY, Const(16));
|
|
|
|
tidZ = context.ShiftLeft(tidZ, Const(26));
|
|
|
|
|
|
|
|
src = context.BitwiseOr(tidX, context.BitwiseOr(tidY, tidZ));
|
2021-10-12 22:35:31 +02:00
|
|
|
break;
|
2019-10-26 19:50:52 +02:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
case SReg.TIdX:
|
|
|
|
src = Attribute(AttributeConsts.ThreadIdX);
|
|
|
|
break;
|
|
|
|
case SReg.TIdY:
|
|
|
|
src = Attribute(AttributeConsts.ThreadIdY);
|
|
|
|
break;
|
|
|
|
case SReg.TIdZ:
|
|
|
|
src = Attribute(AttributeConsts.ThreadIdZ);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SReg.CtaIdX:
|
|
|
|
src = Attribute(AttributeConsts.CtaIdX);
|
|
|
|
break;
|
|
|
|
case SReg.CtaIdY:
|
|
|
|
src = Attribute(AttributeConsts.CtaIdY);
|
|
|
|
break;
|
|
|
|
case SReg.CtaIdZ:
|
|
|
|
src = Attribute(AttributeConsts.CtaIdZ);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SReg.EqMask:
|
|
|
|
src = Attribute(AttributeConsts.EqMask);
|
|
|
|
break;
|
|
|
|
case SReg.LtMask:
|
|
|
|
src = Attribute(AttributeConsts.LtMask);
|
|
|
|
break;
|
|
|
|
case SReg.LeMask:
|
|
|
|
src = Attribute(AttributeConsts.LeMask);
|
|
|
|
break;
|
|
|
|
case SReg.GtMask:
|
|
|
|
src = Attribute(AttributeConsts.GtMask);
|
|
|
|
break;
|
|
|
|
case SReg.GeMask:
|
|
|
|
src = Attribute(AttributeConsts.GeMask);
|
2019-10-26 19:50:52 +02:00
|
|
|
break;
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
default:
|
|
|
|
src = Const(0);
|
|
|
|
break;
|
2019-10-13 08:02:07 +02:00
|
|
|
}
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
context.Copy(GetDest(op.Dest), src);
|
2019-10-13 08:02:07 +02:00
|
|
|
}
|
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void SelR(EmitterContext context)
|
2019-10-13 08:02:07 +02:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
InstSelR op = context.GetOp<InstSelR>();
|
|
|
|
|
|
|
|
Operand srcA = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand srcB = GetSrcReg(context, op.SrcB);
|
|
|
|
Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
|
2019-10-13 08:02:07 +02:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
EmitSel(context, srcA, srcB, srcPred, op.Dest);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void SelI(EmitterContext context)
|
|
|
|
{
|
|
|
|
InstSelI op = context.GetOp<InstSelI>();
|
2019-10-13 08:02:07 +02:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
Operand srcA = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand srcB = GetSrcImm(context, Imm20ToSInt(op.Imm20));
|
|
|
|
Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
|
2019-10-13 08:02:07 +02:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
EmitSel(context, srcA, srcB, srcPred, op.Dest);
|
2019-10-13 08:02:07 +02:00
|
|
|
}
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
public static void SelC(EmitterContext context)
|
2019-10-31 04:29:22 +01:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
InstSelC op = context.GetOp<InstSelC>();
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
Operand srcA = GetSrcReg(context, op.SrcA);
|
|
|
|
Operand srcB = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
|
|
|
|
Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
EmitSel(context, srcA, srcB, srcPred, op.Dest);
|
|
|
|
}
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
private static void EmitR2p(EmitterContext context, Operand value, Operand mask, ByteSel byteSel, bool ccpr)
|
|
|
|
{
|
|
|
|
Operand Test(Operand value, int bit)
|
|
|
|
{
|
|
|
|
return context.ICompareNotEqual(context.BitwiseAnd(value, Const(1 << bit)), Const(0));
|
|
|
|
}
|
2019-10-31 04:29:22 +01:00
|
|
|
|
2021-10-12 22:35:31 +02:00
|
|
|
if (ccpr)
|
|
|
|
{
|
|
|
|
// TODO: Support Register to condition code flags copy.
|
|
|
|
context.Config.GpuAccessor.Log("R2P.CC not implemented.");
|
|
|
|
}
|
|
|
|
else
|
2019-10-31 04:29:22 +01:00
|
|
|
{
|
2021-10-12 22:35:31 +02:00
|
|
|
int shift = (int)byteSel * 8;
|
|
|
|
|
|
|
|
for (int bit = 0; bit < RegisterConsts.PredsCount; bit++)
|
|
|
|
{
|
|
|
|
Operand pred = Register(bit, RegisterType.Predicate);
|
|
|
|
Operand res = context.ConditionalSelect(Test(mask, bit), Test(value, bit + shift), pred);
|
|
|
|
context.Copy(pred, res);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitSel(EmitterContext context, Operand srcA, Operand srcB, Operand srcPred, int rd)
|
|
|
|
{
|
|
|
|
Operand res = context.ConditionalSelect(srcPred, srcA, srcB);
|
|
|
|
|
|
|
|
context.Copy(GetDest(rd), res);
|
2019-10-31 04:29:22 +01:00
|
|
|
}
|
2019-10-13 08:02:07 +02:00
|
|
|
}
|
|
|
|
}
|