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Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)
* Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
8f6387128a
commit
c818093528
@ -213,15 +213,15 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitQxtn(AILEmitterCtx Context, bool Signed, bool Scalar)
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private static void EmitSaturatingExtNarrow(AILEmitterCtx Context, bool SignedSrc, bool SignedDst, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = (!Scalar ? 8 >> Op.Size : 1);
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int ESize = 8 << Op.Size;
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int TMaxValue = (Signed ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMinValue = (Signed ? -((1 << (ESize - 1))) : 0);
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int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
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int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
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@ -233,14 +233,14 @@ namespace ChocolArm64.Instruction
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AILLabel LblLe = new AILLabel();
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AILLabel LblGeEnd = new AILLabel();
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(TMaxValue);
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Context.Emit(OpCodes.Conv_U8);
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Context.Emit(Signed ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
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Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
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Context.Emit(OpCodes.Pop);
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@ -258,7 +258,7 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I4(TMinValue);
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Context.Emit(OpCodes.Conv_I8);
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Context.Emit(Signed ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
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Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
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Context.Emit(OpCodes.Pop);
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@ -1137,22 +1137,22 @@ namespace ChocolArm64.Instruction
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public static void Sqxtn_S(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: true, Scalar: true);
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: true);
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}
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public static void Sqxtn_V(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: true, Scalar: false);
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: false);
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}
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public static void Sqxtun_S(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: true);
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: true);
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}
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public static void Sqxtun_V(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: false);
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: false);
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}
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public static void Sub_S(AILEmitterCtx Context)
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@ -1243,12 +1243,12 @@ namespace ChocolArm64.Instruction
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public static void Uqxtn_S(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: true);
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EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: true);
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}
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public static void Uqxtn_V(AILEmitterCtx Context)
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{
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EmitQxtn(Context, Signed: false, Scalar: false);
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EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: false);
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}
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}
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}
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@ -851,6 +851,82 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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}
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[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
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public void Sqxtun_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
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{
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uint Opcode = 0x7E212820; // SQXTUN B0, H1
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
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TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
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AArch64.V(1, new Bits(A));
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SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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}
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[Test, Pairwise, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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public void Sqxtun_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
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[ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
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{
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uint Opcode = 0x2E212820; // SQXTUN V0.8B, V1.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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}
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[Test, Pairwise, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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public void Sqxtun_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
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[ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
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{
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uint Opcode = 0x6E212820; // SQXTUN2 V0.16B, V1.8H
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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ulong _X0 = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0(_X0);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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}
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[Test, Description("UQXTN <Vb><d>, <Va><n>")]
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public void Uqxtn_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
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@ -2889,6 +2889,86 @@ namespace Ryujinx.Tests.Cpu.Tester
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Vpart(d, part, result);
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}
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// sqxtun_advsimd.html#SQXTUN_asisdmisc_N
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public static void Sqxtun_S(Bits size, Bits Rn, Bits Rd)
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{
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/* Decode Scalar */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = esize;
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int part = 0;
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int elements = 1;
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(datasize);
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Bits operand = V(2 * datasize, n);
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Bits element;
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bool sat;
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for (int e = 0; e <= elements - 1; e++)
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{
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element = Elem(operand, e, 2 * esize);
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(Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize);
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Elem(result, e, esize, _result);
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sat = _sat;
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if (sat)
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{
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/* FPSR.QC = '1'; */
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FPSR[27] = true; // TODO: Add named fields.
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}
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}
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Vpart(d, part, result);
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}
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// sqxtun_advsimd.html#SQXTUN_asimdmisc_N
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public static void Sqxtun_V(bool Q, Bits size, Bits Rn, Bits Rd)
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{
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/* Decode Vector */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = 64;
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int part = (int)UInt(Q);
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int elements = datasize / esize;
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(datasize);
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Bits operand = V(2 * datasize, n);
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Bits element;
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bool sat;
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for (int e = 0; e <= elements - 1; e++)
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{
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element = Elem(operand, e, 2 * esize);
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(Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize);
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Elem(result, e, esize, _result);
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sat = _sat;
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if (sat)
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{
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/* FPSR.QC = '1'; */
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FPSR[27] = true; // TODO: Add named fields.
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}
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}
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Vpart(d, part, result);
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}
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// uqxtn_advsimd.html#UQXTN_asisdmisc_N
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public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd)
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{
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