mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-11-24 16:30:12 +01:00
InstEmitMemory32: Literal loads always have word-aligned PC (#3104)
This commit is contained in:
parent
f861f0bca2
commit
ce71f9144e
@ -47,6 +47,20 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static Operand GetIntA32AlignedPC(ArmEmitterContext context, int regIndex)
|
||||
{
|
||||
if (regIndex == RegisterAlias.Aarch32Pc)
|
||||
{
|
||||
OpCode32 op = (OpCode32)context.CurrOp;
|
||||
|
||||
return Const((int)(op.GetPc() & 0xfffffffc));
|
||||
}
|
||||
else
|
||||
{
|
||||
return Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
|
||||
}
|
||||
}
|
||||
|
||||
public static Operand GetVecA32(int regIndex)
|
||||
{
|
||||
return Register(regIndex, RegisterType.Vector, OperandType.V128);
|
||||
|
@ -153,7 +153,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
OpCode32Mem op = (OpCode32Mem)context.CurrOp;
|
||||
|
||||
Operand n = context.Copy(GetIntA32(context, op.Rn));
|
||||
Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
|
||||
Operand m = GetMemM(context, setCarry: false);
|
||||
|
||||
Operand temp = default;
|
||||
|
Loading…
Reference in New Issue
Block a user