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https://github.com/ryujinx-mirror/ryujinx.git
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8a7d99cdea
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
274 lines
9.2 KiB
C#
274 lines
9.2 KiB
C#
using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.State;
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using System;
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using System.Collections.Generic;
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using System.Reflection;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics;
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using static ChocolArm64.State.RegisterConsts;
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namespace ChocolArm64.Translation
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{
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class TranslatedSubBuilder
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{
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private ExecutionMode _mode;
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private bool _isComplete;
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private Dictionary<Register, int> _locals;
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private RegisterUsage _regUsage;
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public TranslatedSubBuilder(ExecutionMode mode, bool isComplete = false)
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{
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_mode = mode;
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_isComplete = isComplete;
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}
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public TranslatedSub Build(BasicBlock[] blocks, string name, TranslationTier tier, bool rejit = true)
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{
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_regUsage = new RegisterUsage(blocks[0], blocks.Length);
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DynamicMethod method = new DynamicMethod(name, typeof(long), TranslatedSub.FixedArgTypes);
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TranslatedSub subroutine = new TranslatedSub(method, tier, rejit);
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_locals = new Dictionary<Register, int>();
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Dictionary<ILLabel, Label> labels = new Dictionary<ILLabel, Label>();
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ILGenerator generator = method.GetILGenerator();
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Label GetLabel(ILLabel label)
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{
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if (!labels.TryGetValue(label, out Label ilLabel))
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{
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ilLabel = generator.DefineLabel();
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labels.Add(label, ilLabel);
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}
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return ilLabel;
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}
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foreach (BasicBlock block in blocks)
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{
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for (int index = 0; index < block.Count; index++)
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{
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Operation operation = block.GetOperation(index);
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switch (operation.Type)
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{
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case OperationType.Call:
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generator.Emit(OpCodes.Call, operation.GetArg<MethodInfo>(0));
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break;
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case OperationType.CallVirtual:
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generator.Emit(OpCodes.Callvirt, operation.GetArg<MethodInfo>(0));
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break;
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case OperationType.IL:
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generator.Emit(operation.GetArg<OpCode>(0));
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break;
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case OperationType.ILBranch:
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generator.Emit(operation.GetArg<OpCode>(0), GetLabel(operation.GetArg<ILLabel>(1)));
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break;
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case OperationType.LoadArgument:
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generator.EmitLdarg(operation.GetArg<int>(0));
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break;
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case OperationType.LoadConstant:
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EmitLoadConstant(generator, operation.GetArg(0));
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break;
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case OperationType.LoadContext:
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EmitLoadContext(generator, operation.Parent);
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break;
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case OperationType.LoadField:
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generator.Emit(OpCodes.Ldfld, operation.GetArg<FieldInfo>(0));
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break;
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case OperationType.LoadLocal:
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EmitLoadLocal(
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generator,
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operation.GetArg<int>(0),
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operation.GetArg<RegisterType>(1),
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operation.GetArg<RegisterSize>(2));
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break;
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case OperationType.MarkLabel:
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generator.MarkLabel(GetLabel(operation.GetArg<ILLabel>(0)));
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break;
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case OperationType.StoreContext:
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EmitStoreContext(generator, operation.Parent);
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break;
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case OperationType.StoreLocal:
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EmitStoreLocal(
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generator,
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operation.GetArg<int>(0),
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operation.GetArg<RegisterType>(1),
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operation.GetArg<RegisterSize>(2));
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break;
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}
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}
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}
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subroutine.PrepareMethod();
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return subroutine;
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}
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private static void EmitLoadConstant(ILGenerator generator, object value)
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{
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switch (value)
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{
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case int valI4: generator.EmitLdc_I4(valI4); break;
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case long valI8: generator.Emit(OpCodes.Ldc_I8, valI8); break;
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case float valR4: generator.Emit(OpCodes.Ldc_R4, valR4); break;
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case double valR8: generator.Emit(OpCodes.Ldc_R8, valR8); break;
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}
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}
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private void EmitLoadContext(ILGenerator generator, BasicBlock block)
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{
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RegisterMask inputs = _regUsage.GetInputs(block);
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long intInputs = inputs.IntMask;
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long vecInputs = inputs.VecMask;
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if (Optimizations.AssumeStrictAbiCompliance && _isComplete)
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{
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intInputs = RegisterUsage.ClearCallerSavedIntRegs(intInputs, _mode);
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vecInputs = RegisterUsage.ClearCallerSavedVecRegs(vecInputs, _mode);
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}
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LoadLocals(generator, intInputs, RegisterType.Int);
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LoadLocals(generator, vecInputs, RegisterType.Vector);
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}
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private void LoadLocals(ILGenerator generator, long inputs, RegisterType baseType)
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{
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((inputs & mask) != 0)
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{
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Register reg = GetRegFromBit(bit, baseType);
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generator.EmitLdarg(TranslatedSub.StateArgIdx);
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generator.Emit(OpCodes.Ldfld, reg.GetField());
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generator.EmitStloc(GetLocalIndex(generator, reg));
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}
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}
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}
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private void EmitStoreContext(ILGenerator generator, BasicBlock block)
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{
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RegisterMask outputs = _regUsage.GetOutputs(block);
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long intOutputs = outputs.IntMask;
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long vecOutputs = outputs.VecMask;
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if (Optimizations.AssumeStrictAbiCompliance && _isComplete)
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{
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intOutputs = RegisterUsage.ClearCallerSavedIntRegs(intOutputs, _mode);
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vecOutputs = RegisterUsage.ClearCallerSavedVecRegs(vecOutputs, _mode);
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}
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StoreLocals(generator, intOutputs, RegisterType.Int);
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StoreLocals(generator, vecOutputs, RegisterType.Vector);
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}
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private void StoreLocals(ILGenerator generator, long outputs, RegisterType baseType)
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{
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((outputs & mask) != 0)
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{
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Register reg = GetRegFromBit(bit, baseType);
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generator.EmitLdarg(TranslatedSub.StateArgIdx);
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generator.EmitLdloc(GetLocalIndex(generator, reg));
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generator.Emit(OpCodes.Stfld, reg.GetField());
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}
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}
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}
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private void EmitLoadLocal(ILGenerator generator, int index, RegisterType type, RegisterSize size)
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{
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Register reg = new Register(index, type);
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generator.EmitLdloc(GetLocalIndex(generator, reg));
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if (type == RegisterType.Int && size == RegisterSize.Int32)
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{
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generator.Emit(OpCodes.Conv_U4);
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}
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}
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private void EmitStoreLocal(ILGenerator generator, int index, RegisterType type, RegisterSize size)
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{
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Register reg = new Register(index, type);
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if (type == RegisterType.Int && size == RegisterSize.Int32)
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{
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generator.Emit(OpCodes.Conv_U8);
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}
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generator.EmitStloc(GetLocalIndex(generator, reg));
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}
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private int GetLocalIndex(ILGenerator generator, Register reg)
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{
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if (!_locals.TryGetValue(reg, out int index))
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{
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generator.DeclareLocal(GetFieldType(reg.Type));
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index = _locals.Count;
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_locals.Add(reg, index);
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}
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return index;
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}
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private static Type GetFieldType(RegisterType regType)
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{
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switch (regType)
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{
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case RegisterType.Flag: return typeof(bool);
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case RegisterType.Int: return typeof(ulong);
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case RegisterType.Vector: return typeof(Vector128<float>);
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}
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throw new ArgumentException(nameof(regType));
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}
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private static Register GetRegFromBit(int bit, RegisterType baseType)
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{
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if (bit < RegsCount)
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{
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return new Register(bit, baseType);
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}
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else if (baseType == RegisterType.Int)
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{
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return new Register(bit & RegsMask, RegisterType.Flag);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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}
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} |