mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-04 20:47:56 +01:00
e603b7afbc
* Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update InstEmitSimdCmp.cs * Update SoftFloat.cs * Update InstEmitAluHelper.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdHelper.cs * Update VectorHelper.cs * Update InstEmitSimdCvt.cs * Update InstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update InstEmitSimdArithmetic.cs * Update OpCodeTable.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdCmp.cs * Update InstEmitSimdCvt.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Create CpuTestSimdFcond.cs * Update OpCodeTable.cs * Update InstEmitSimdMove.cs * Update CpuTestSimdIns.cs * Create CpuTestSimdExt.cs * Nit. * Update PackageReference.
222 lines
6.0 KiB
C#
222 lines
6.0 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static class InstEmitAluHelper
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{
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public static void EmitAdcsCCheck(ILEmitterCtx context)
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{
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//C = (Rd == Rn && CIn) || Rd < Rn
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context.EmitSttmp();
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context.EmitLdtmp();
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context.EmitLdtmp();
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EmitDataLoadRn(context);
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context.Emit(OpCodes.Ceq);
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context.EmitLdflg((int)PState.CBit);
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context.Emit(OpCodes.And);
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context.EmitLdtmp();
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EmitDataLoadRn(context);
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context.Emit(OpCodes.Clt_Un);
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context.Emit(OpCodes.Or);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitAddsCCheck(ILEmitterCtx context)
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{
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//C = Rd < Rn
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context.Emit(OpCodes.Dup);
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EmitDataLoadRn(context);
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context.Emit(OpCodes.Clt_Un);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitAddsVCheck(ILEmitterCtx context)
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{
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//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
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context.Emit(OpCodes.Dup);
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EmitDataLoadRn(context);
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context.Emit(OpCodes.Xor);
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EmitDataLoadOpers(context);
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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context.EmitLdc_I(0);
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context.Emit(OpCodes.Clt);
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context.EmitStflg((int)PState.VBit);
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}
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public static void EmitSbcsCCheck(ILEmitterCtx context)
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{
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//C = (Rn == Rm && CIn) || Rn > Rm
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EmitDataLoadOpers(context);
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context.Emit(OpCodes.Ceq);
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context.EmitLdflg((int)PState.CBit);
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context.Emit(OpCodes.And);
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EmitDataLoadOpers(context);
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context.Emit(OpCodes.Cgt_Un);
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context.Emit(OpCodes.Or);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitSubsCCheck(ILEmitterCtx context)
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{
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//C = Rn == Rm || Rn > Rm = !(Rn < Rm)
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EmitDataLoadOpers(context);
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context.Emit(OpCodes.Clt_Un);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.Xor);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitSubsVCheck(ILEmitterCtx context)
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{
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//V = (Rd ^ Rn) & (Rn ^ Rm) < 0
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context.Emit(OpCodes.Dup);
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EmitDataLoadRn(context);
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context.Emit(OpCodes.Xor);
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EmitDataLoadOpers(context);
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.And);
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context.EmitLdc_I(0);
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context.Emit(OpCodes.Clt);
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context.EmitStflg((int)PState.VBit);
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}
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public static void EmitDataLoadRm(ILEmitterCtx context)
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{
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context.EmitLdintzr(((IOpCodeAluRs64)context.CurrOp).Rm);
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}
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public static void EmitDataLoadOpers(ILEmitterCtx context)
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{
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EmitDataLoadRn(context);
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EmitDataLoadOper2(context);
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}
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public static void EmitDataLoadRn(ILEmitterCtx context)
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{
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IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
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if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs64)
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{
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context.EmitLdintzr(op.Rn);
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}
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else
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{
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context.EmitLdint(op.Rn);
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}
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}
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public static void EmitDataLoadOper2(ILEmitterCtx context)
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{
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switch (context.CurrOp)
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{
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case IOpCodeAluImm64 op:
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context.EmitLdc_I(op.Imm);
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break;
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case IOpCodeAluRs64 op:
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context.EmitLdintzr(op.Rm);
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: context.EmitLsl(op.Shift); break;
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case ShiftType.Lsr: context.EmitLsr(op.Shift); break;
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case ShiftType.Asr: context.EmitAsr(op.Shift); break;
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case ShiftType.Ror: context.EmitRor(op.Shift); break;
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}
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break;
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case IOpCodeAluRx64 op:
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context.EmitLdintzr(op.Rm);
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context.EmitCast(op.IntType);
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context.EmitLsl(op.Shift);
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break;
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}
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}
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public static void EmitDataStore(ILEmitterCtx context) => EmitDataStore(context, false);
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public static void EmitDataStoreS(ILEmitterCtx context) => EmitDataStore(context, true);
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public static void EmitDataStore(ILEmitterCtx context, bool setFlags)
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{
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IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
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if (setFlags || op is IOpCodeAluRs64)
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{
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context.EmitStintzr(op.Rd);
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}
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else
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{
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context.EmitStint(op.Rd);
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}
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}
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public static void EmitSetNzcv(ILEmitterCtx context)
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{
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.VBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.ZBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.NBit);
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}
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}
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}
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