mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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650cc41c02
* Implement remaining shader double-precision instructions * Shader cache version bump
266 lines
7.7 KiB
C#
266 lines
7.7 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using System;
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using System.Runtime.CompilerServices;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static class InstEmitHelper
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{
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public static Operand GetZF()
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{
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return Register(0, RegisterType.Flag);
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}
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public static Operand GetNF()
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{
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return Register(1, RegisterType.Flag);
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}
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public static Operand GetCF()
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{
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return Register(2, RegisterType.Flag);
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}
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public static Operand GetVF()
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{
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return Register(3, RegisterType.Flag);
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}
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public static Operand GetDest(int rd)
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{
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return Register(rd, RegisterType.Gpr);
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}
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public static Operand GetDest2(int rd)
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{
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return Register(rd | 1, RegisterType.Gpr);
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}
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public static Operand GetSrcCbuf(EmitterContext context, int cbufSlot, int cbufOffset, bool isFP64 = false)
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{
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if (isFP64)
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{
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return context.PackDouble2x32(
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context.Config.CreateCbuf(cbufSlot, cbufOffset),
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context.Config.CreateCbuf(cbufSlot, cbufOffset + 1));
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}
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else
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{
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return context.Config.CreateCbuf(cbufSlot, cbufOffset);
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}
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}
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public static Operand GetSrcImm(EmitterContext context, int imm, bool isFP64 = false)
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{
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if (isFP64)
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{
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return context.PackDouble2x32(Const(0), Const(imm));
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}
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else
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{
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return Const(imm);
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}
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}
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public static Operand GetSrcReg(EmitterContext context, int reg, bool isFP64 = false)
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{
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if (isFP64)
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{
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return context.PackDouble2x32(Register(reg, RegisterType.Gpr), Register(reg | 1, RegisterType.Gpr));
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}
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else
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{
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return Register(reg, RegisterType.Gpr);
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}
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}
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public static Operand[] GetHalfSrc(
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EmitterContext context,
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HalfSwizzle swizzle,
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int ra,
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bool negate,
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bool absolute)
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{
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Operand[] operands = GetHalfUnpacked(context, GetSrcReg(context, ra), swizzle);
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return FPAbsNeg(context, operands, absolute, negate);
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}
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public static Operand[] GetHalfSrc(
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EmitterContext context,
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HalfSwizzle swizzle,
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int cbufSlot,
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int cbufOffset,
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bool negate,
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bool absolute)
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{
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Operand[] operands = GetHalfUnpacked(context, GetSrcCbuf(context, cbufSlot, cbufOffset), swizzle);
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return FPAbsNeg(context, operands, absolute, negate);
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}
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public static Operand[] GetHalfSrc(EmitterContext context, int immH0, int immH1)
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{
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ushort low = (ushort)(immH0 << 6);
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ushort high = (ushort)(immH1 << 6);
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return new Operand[]
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{
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ConstF((float)Unsafe.As<ushort, Half>(ref low)),
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ConstF((float)Unsafe.As<ushort, Half>(ref high))
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};
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}
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public static Operand[] GetHalfSrc(EmitterContext context, int imm32)
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{
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ushort low = (ushort)imm32;
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ushort high = (ushort)(imm32 >> 16);
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return new Operand[]
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{
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ConstF((float)Unsafe.As<ushort, Half>(ref low)),
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ConstF((float)Unsafe.As<ushort, Half>(ref high))
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};
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}
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public static Operand[] FPAbsNeg(EmitterContext context, Operand[] operands, bool abs, bool neg)
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{
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for (int index = 0; index < operands.Length; index++)
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{
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operands[index] = context.FPAbsNeg(operands[index], abs, neg);
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}
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return operands;
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}
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public static Operand[] GetHalfUnpacked(EmitterContext context, Operand src, HalfSwizzle swizzle)
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{
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switch (swizzle)
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{
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case HalfSwizzle.F16:
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return new Operand[]
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{
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context.UnpackHalf2x16Low (src),
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context.UnpackHalf2x16High(src)
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};
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case HalfSwizzle.F32: return new Operand[] { src, src };
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case HalfSwizzle.H0H0:
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return new Operand[]
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{
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context.UnpackHalf2x16Low(src),
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context.UnpackHalf2x16Low(src)
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};
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case HalfSwizzle.H1H1:
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return new Operand[]
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{
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context.UnpackHalf2x16High(src),
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context.UnpackHalf2x16High(src)
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};
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}
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throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
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}
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public static Operand GetHalfPacked(EmitterContext context, OFmt swizzle, Operand[] results, int rd)
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{
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switch (swizzle)
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{
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case OFmt.F16: return context.PackHalf2x16(results[0], results[1]);
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case OFmt.F32: return results[0];
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case OFmt.MrgH0:
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{
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Operand h1 = GetHalfDest(context, rd, isHigh: true);
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return context.PackHalf2x16(results[0], h1);
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}
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case OFmt.MrgH1:
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{
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Operand h0 = GetHalfDest(context, rd, isHigh: false);
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return context.PackHalf2x16(h0, results[1]);
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}
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}
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throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
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}
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public static Operand GetHalfDest(EmitterContext context, int rd, bool isHigh)
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{
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if (isHigh)
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{
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return context.UnpackHalf2x16High(GetDest(rd));
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}
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else
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{
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return context.UnpackHalf2x16Low(GetDest(rd));
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}
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}
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public static Operand GetPredicate(EmitterContext context, int pred, bool not)
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{
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Operand local = Register(pred, RegisterType.Predicate);
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if (not)
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{
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local = context.BitwiseNot(local);
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}
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return local;
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}
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public static void SetDest(EmitterContext context, Operand value, int rd, bool isFP64)
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{
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if (isFP64)
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{
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context.Copy(GetDest(rd), context.UnpackDouble2x32Low(value));
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context.Copy(GetDest2(rd), context.UnpackDouble2x32High(value));
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}
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else
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{
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context.Copy(GetDest(rd), value);
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}
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}
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public static int Imm16ToSInt(int imm16)
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{
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return (short)imm16;
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}
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public static int Imm20ToFloat(int imm20)
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{
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return imm20 << 12;
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}
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public static int Imm20ToSInt(int imm20)
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{
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return (imm20 << 12) >> 12;
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}
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public static int Imm24ToSInt(int imm24)
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{
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return (imm24 << 8) >> 8;
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}
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public static Operand SignExtendTo32(EmitterContext context, Operand src, int srcBits)
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{
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return context.BitfieldExtractS32(src, Const(0), Const(srcBits));
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}
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public static Operand ZeroExtendTo32(EmitterContext context, Operand src, int srcBits)
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{
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int mask = (int)(uint.MaxValue >> (32 - srcBits));
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return context.BitwiseAnd(src, Const(mask));
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}
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}
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} |