ryujinx

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History

LDj3SNuD a5ad1e9a06 Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104 )

* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

2018-04-25 23:20:22 -03:00

Decoder

[CPU] Fix CBZ/CBNZ with 32 bits operands

2018-04-06 17:22:26 -03:00

Events

Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store

2018-02-25 22:14:58 -03:00

Exceptions

Split main project into core,graphics and chocolarm4 subproject (#29 )

2018-02-20 17:09:23 -03:00

Instruction

Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104 )