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9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
65 lines
2.2 KiB
C#
65 lines
2.2 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using System;
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namespace ChocolArm64.Instructions32
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{
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static class A32InstInterpretHelper
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{
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public static bool IsConditionTrue(CpuThreadState state, Cond cond)
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{
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switch (cond)
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{
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case Cond.Eq: return state.Zero;
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case Cond.Ne: return !state.Zero;
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case Cond.GeUn: return state.Carry;
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case Cond.LtUn: return !state.Carry;
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case Cond.Mi: return state.Negative;
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case Cond.Pl: return !state.Negative;
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case Cond.Vs: return state.Overflow;
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case Cond.Vc: return !state.Overflow;
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case Cond.GtUn: return state.Carry && !state.Zero;
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case Cond.LeUn: return !state.Carry && state.Zero;
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case Cond.Ge: return state.Negative == state.Overflow;
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case Cond.Lt: return state.Negative != state.Overflow;
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case Cond.Gt: return state.Negative == state.Overflow && !state.Zero;
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case Cond.Le: return state.Negative != state.Overflow && state.Zero;
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}
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return true;
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}
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public unsafe static uint GetReg(CpuThreadState state, int reg)
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{
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if ((uint)reg > 15)
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{
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throw new ArgumentOutOfRangeException(nameof(reg));
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}
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fixed (uint* ptr = &state.R0)
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{
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return *(ptr + reg);
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}
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}
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public unsafe static void SetReg(CpuThreadState state, int reg, uint value)
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{
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if ((uint)reg > 15)
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{
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throw new ArgumentOutOfRangeException(nameof(reg));
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}
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fixed (uint* ptr = &state.R0)
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{
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*(ptr + reg) = value;
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}
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}
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public static uint GetPc(CpuThreadState state)
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{
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//Due to the old fetch-decode-execute pipeline of old ARM CPUs,
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//the PC is 4 or 8 bytes (2 instructions) ahead of the current instruction.
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return state.R15 + (state.Thumb ? 2U : 4U);
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}
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}
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} |