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https://github.com/ryujinx-mirror/ryujinx.git
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e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
60 lines
2.0 KiB
C#
60 lines
2.0 KiB
C#
using ChocolArm64.State;
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using System.Reflection.Emit;
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namespace ChocolArm64.Translation
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{
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struct ILOpCodeStoreState : IILEmit
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{
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private ILBlock _block;
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private TranslatedSub _callSub;
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public ILOpCodeStoreState(ILBlock block, TranslatedSub callSub = null)
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{
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_block = block;
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_callSub = callSub;
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}
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public void Emit(ILMethodBuilder context)
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{
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long intOutputs = context.RegUsage.GetIntOutputs(_block);
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long vecOutputs = context.RegUsage.GetVecOutputs(_block);
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if (Optimizations.AssumeStrictAbiCompliance && context.IsSubComplete)
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{
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intOutputs = RegisterUsage.ClearCallerSavedIntRegs(intOutputs, context.IsAarch64);
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vecOutputs = RegisterUsage.ClearCallerSavedVecRegs(vecOutputs, context.IsAarch64);
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}
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if (_callSub != null)
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{
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//Those register are assigned on the callee function, without
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//reading it's value first. We don't need to write them because
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//they are not going to be read on the callee.
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intOutputs &= ~_callSub.IntNiRegsMask;
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vecOutputs &= ~_callSub.VecNiRegsMask;
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}
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StoreLocals(context, intOutputs, RegisterType.Int);
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StoreLocals(context, vecOutputs, RegisterType.Vector);
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}
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private void StoreLocals(ILMethodBuilder context, long outputs, RegisterType baseType)
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{
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((outputs & mask) != 0)
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{
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Register reg = ILMethodBuilder.GetRegFromBit(bit, baseType);
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context.Generator.EmitLdarg(TranslatedSub.StateArgIdx);
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context.Generator.EmitLdloc(context.GetLocalIndex(reg));
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context.Generator.Emit(OpCodes.Stfld, reg.GetField());
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}
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}
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}
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}
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} |