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https://github.com/ryujinx-mirror/ryujinx.git
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c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
141 lines
3.5 KiB
C#
141 lines
3.5 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmit32Helper;
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using static ChocolArm64.Instructions.InstEmitAluHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit32
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{
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public static void Add(ILEmitterCtx context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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EmitAluLoadOpers(context, setCarry: false);
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context.Emit(OpCodes.Add);
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if (op.SetFlags)
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{
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context.EmitZnFlagCheck();
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EmitAddsCCheck(context);
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EmitAddsVCheck(context);
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}
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EmitAluStore(context);
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}
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public static void Cmp(ILEmitterCtx context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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EmitAluLoadOpers(context, setCarry: false);
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context.Emit(OpCodes.Sub);
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context.EmitZnFlagCheck();
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EmitSubsCCheck(context);
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EmitSubsVCheck(context);
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context.Emit(OpCodes.Pop);
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}
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public static void Mov(ILEmitterCtx context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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EmitAluLoadOper2(context);
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if (op.SetFlags)
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{
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context.EmitZnFlagCheck();
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}
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EmitAluStore(context);
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}
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public static void Sub(ILEmitterCtx context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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EmitAluLoadOpers(context, setCarry: false);
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context.Emit(OpCodes.Sub);
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if (op.SetFlags)
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{
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context.EmitZnFlagCheck();
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EmitSubsCCheck(context);
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EmitSubsVCheck(context);
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}
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EmitAluStore(context);
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}
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private static void EmitAluStore(ILEmitterCtx context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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if (op.Rd == RegisterAlias.Aarch32Pc)
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{
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if (op.SetFlags)
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{
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//TODO: Load SPSR etc.
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context.EmitLdflg((int)PState.TBit);
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ILLabel lblThumb = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brtrue_S, lblThumb);
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context.EmitLdc_I4(~3);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblThumb);
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context.EmitLdc_I4(~1);
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context.MarkLabel(lblEnd);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Conv_U8);
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context.Emit(OpCodes.Ret);
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}
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else
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{
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EmitAluWritePc(context);
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}
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}
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else
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{
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context.EmitStint(GetRegisterAlias(context.Mode, op.Rd));
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}
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}
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private static void EmitAluWritePc(ILEmitterCtx context)
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{
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context.EmitStoreState();
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if (IsThumb(context.CurrOp))
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{
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context.EmitLdc_I4(~1);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Conv_U8);
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context.Emit(OpCodes.Ret);
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}
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else
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{
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EmitBxWritePc(context);
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}
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}
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}
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} |