mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
139 lines
4.5 KiB
C#
139 lines
4.5 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Hint(ILEmitterCtx context)
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{
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//Execute as no-op.
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}
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public static void Isb(ILEmitterCtx context)
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{
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//Execute as no-op.
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}
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public static void Mrs(ILEmitterCtx context)
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{
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OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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string propName;
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switch (GetPackedId(op))
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{
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case 0b11_011_0000_0000_001: propName = nameof(CpuThreadState.CtrEl0); break;
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case 0b11_011_0000_0000_111: propName = nameof(CpuThreadState.DczidEl0); break;
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.Fpsr); break;
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case 0b11_011_1101_0000_010: propName = nameof(CpuThreadState.TpidrEl0); break;
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case 0b11_011_1101_0000_011: propName = nameof(CpuThreadState.Tpidr); break;
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case 0b11_011_1110_0000_000: propName = nameof(CpuThreadState.CntfrqEl0); break;
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case 0b11_011_1110_0000_001: propName = nameof(CpuThreadState.CntpctEl0); break;
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default: throw new NotImplementedException($"Unknown MRS at {op.Position:x16}");
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}
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context.EmitCallPropGet(typeof(CpuThreadState), propName);
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PropertyInfo propInfo = typeof(CpuThreadState).GetProperty(propName);
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if (propInfo.PropertyType != typeof(long) &&
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propInfo.PropertyType != typeof(ulong))
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.EmitStintzr(op.Rt);
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}
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public static void Msr(ILEmitterCtx context)
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{
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OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdintzr(op.Rt);
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string propName;
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switch (GetPackedId(op))
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{
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.Fpsr); break;
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case 0b11_011_1101_0000_010: propName = nameof(CpuThreadState.TpidrEl0); break;
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default: throw new NotImplementedException($"Unknown MSR at {op.Position:x16}");
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}
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PropertyInfo propInfo = typeof(CpuThreadState).GetProperty(propName);
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if (propInfo.PropertyType != typeof(long) &&
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propInfo.PropertyType != typeof(ulong))
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{
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context.Emit(OpCodes.Conv_U4);
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}
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context.EmitCallPropSet(typeof(CpuThreadState), propName);
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}
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public static void Nop(ILEmitterCtx context)
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{
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//Do nothing.
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}
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public static void Sys(ILEmitterCtx context)
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{
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//This instruction is used to do some operations on the CPU like cache invalidation,
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//address translation and the like.
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//We treat it as no-op here since we don't have any cache being emulated anyway.
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OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
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switch (GetPackedId(op))
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{
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case 0b11_011_0111_0100_001:
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{
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//DC ZVA
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for (int offs = 0; offs < (4 << CpuThreadState.DczSizeLog2); offs += 8)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdintzr(op.Rt);
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context.EmitLdc_I(offs);
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context.Emit(OpCodes.Add);
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context.EmitLdc_I8(0);
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InstEmitMemoryHelper.EmitWriteCall(context, 3);
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}
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break;
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}
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//No-op
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case 0b11_011_0111_1110_001: //DC CIVAC
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break;
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}
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}
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private static int GetPackedId(OpCodeSystem64 op)
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{
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int id;
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id = op.Op2 << 0;
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id |= op.CRm << 3;
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id |= op.CRn << 7;
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id |= op.Op1 << 11;
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id |= op.Op0 << 14;
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return id;
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}
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}
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}
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